1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "acpi-build.h" 24 #include <stddef.h> 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/osdep.h" 29 #include "qemu/range.h" 30 #include "qemu/error-report.h" 31 #include "hw/pci/pci.h" 32 #include "qom/cpu.h" 33 #include "hw/i386/pc.h" 34 #include "target-i386/cpu.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/i386/acpi-defs.h" 37 #include "hw/acpi/acpi.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/loader.h" 41 #include "hw/isa/isa.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 46 /* Supported chipsets: */ 47 #include "hw/acpi/piix4.h" 48 #include "hw/acpi/pcihp.h" 49 #include "hw/i386/ich9.h" 50 #include "hw/pci/pci_bus.h" 51 #include "hw/pci-host/q35.h" 52 #include "hw/i386/intel_iommu.h" 53 54 #include "hw/i386/q35-acpi-dsdt.hex" 55 #include "hw/i386/acpi-dsdt.hex" 56 57 #include "hw/acpi/aml-build.h" 58 59 #include "qapi/qmp/qint.h" 60 #include "qom/qom-qobject.h" 61 #include "exec/ram_addr.h" 62 63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 65 * a little bit, there should be plenty of free space since the DSDT 66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 67 */ 68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 69 #define ACPI_BUILD_ALIGN_SIZE 0x1000 70 71 #define ACPI_BUILD_TABLE_SIZE 0x20000 72 73 /* Reserve RAM space for tables: add another order of magnitude. */ 74 #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000 75 76 /* #define DEBUG_ACPI_BUILD */ 77 #ifdef DEBUG_ACPI_BUILD 78 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 80 #else 81 #define ACPI_BUILD_DPRINTF(fmt, ...) 82 #endif 83 84 typedef struct AcpiCpuInfo { 85 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 86 } AcpiCpuInfo; 87 88 typedef struct AcpiMcfgInfo { 89 uint64_t mcfg_base; 90 uint32_t mcfg_size; 91 } AcpiMcfgInfo; 92 93 typedef struct AcpiPmInfo { 94 bool s3_disabled; 95 bool s4_disabled; 96 bool pcihp_bridge_en; 97 uint8_t s4_val; 98 uint16_t sci_int; 99 uint8_t acpi_enable_cmd; 100 uint8_t acpi_disable_cmd; 101 uint32_t gpe0_blk; 102 uint32_t gpe0_blk_len; 103 uint32_t io_base; 104 uint16_t cpu_hp_io_base; 105 uint16_t cpu_hp_io_len; 106 uint16_t mem_hp_io_base; 107 uint16_t mem_hp_io_len; 108 uint16_t pcihp_io_base; 109 uint16_t pcihp_io_len; 110 } AcpiPmInfo; 111 112 typedef struct AcpiMiscInfo { 113 bool has_hpet; 114 bool has_tpm; 115 const unsigned char *dsdt_code; 116 unsigned dsdt_size; 117 uint16_t pvpanic_port; 118 uint16_t applesmc_io_base; 119 } AcpiMiscInfo; 120 121 typedef struct AcpiBuildPciBusHotplugState { 122 GArray *device_table; 123 GArray *notify_table; 124 struct AcpiBuildPciBusHotplugState *parent; 125 bool pcihp_bridge_en; 126 } AcpiBuildPciBusHotplugState; 127 128 static void acpi_get_dsdt(AcpiMiscInfo *info) 129 { 130 Object *piix = piix4_pm_find(); 131 Object *lpc = ich9_lpc_find(); 132 assert(!!piix != !!lpc); 133 134 if (piix) { 135 info->dsdt_code = AcpiDsdtAmlCode; 136 info->dsdt_size = sizeof AcpiDsdtAmlCode; 137 } 138 if (lpc) { 139 info->dsdt_code = Q35AcpiDsdtAmlCode; 140 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; 141 } 142 } 143 144 static 145 int acpi_add_cpu_info(Object *o, void *opaque) 146 { 147 AcpiCpuInfo *cpu = opaque; 148 uint64_t apic_id; 149 150 if (object_dynamic_cast(o, TYPE_CPU)) { 151 apic_id = object_property_get_int(o, "apic-id", NULL); 152 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 153 154 set_bit(apic_id, cpu->found_cpus); 155 } 156 157 object_child_foreach(o, acpi_add_cpu_info, opaque); 158 return 0; 159 } 160 161 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 162 { 163 Object *root = object_get_root(); 164 165 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 166 object_child_foreach(root, acpi_add_cpu_info, cpu); 167 } 168 169 static void acpi_get_pm_info(AcpiPmInfo *pm) 170 { 171 Object *piix = piix4_pm_find(); 172 Object *lpc = ich9_lpc_find(); 173 Object *obj = NULL; 174 QObject *o; 175 176 pm->pcihp_io_base = 0; 177 pm->pcihp_io_len = 0; 178 if (piix) { 179 obj = piix; 180 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 181 pm->pcihp_io_base = 182 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 183 pm->pcihp_io_len = 184 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 185 } 186 if (lpc) { 187 obj = lpc; 188 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 189 } 190 assert(obj); 191 192 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 193 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 194 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 195 196 /* Fill in optional s3/s4 related properties */ 197 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 198 if (o) { 199 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 200 } else { 201 pm->s3_disabled = false; 202 } 203 qobject_decref(o); 204 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 205 if (o) { 206 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 207 } else { 208 pm->s4_disabled = false; 209 } 210 qobject_decref(o); 211 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 212 if (o) { 213 pm->s4_val = qint_get_int(qobject_to_qint(o)); 214 } else { 215 pm->s4_val = false; 216 } 217 qobject_decref(o); 218 219 /* Fill in mandatory properties */ 220 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 221 222 pm->acpi_enable_cmd = object_property_get_int(obj, 223 ACPI_PM_PROP_ACPI_ENABLE_CMD, 224 NULL); 225 pm->acpi_disable_cmd = object_property_get_int(obj, 226 ACPI_PM_PROP_ACPI_DISABLE_CMD, 227 NULL); 228 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 229 NULL); 230 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 231 NULL); 232 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 233 NULL); 234 pm->pcihp_bridge_en = 235 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 236 NULL); 237 } 238 239 static void acpi_get_misc_info(AcpiMiscInfo *info) 240 { 241 info->has_hpet = hpet_find(); 242 info->has_tpm = tpm_find(); 243 info->pvpanic_port = pvpanic_port(); 244 info->applesmc_io_base = applesmc_port(); 245 } 246 247 static void acpi_get_pci_info(PcPciInfo *info) 248 { 249 Object *pci_host; 250 bool ambiguous; 251 252 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 253 g_assert(!ambiguous); 254 g_assert(pci_host); 255 256 info->w32.begin = object_property_get_int(pci_host, 257 PCI_HOST_PROP_PCI_HOLE_START, 258 NULL); 259 info->w32.end = object_property_get_int(pci_host, 260 PCI_HOST_PROP_PCI_HOLE_END, 261 NULL); 262 info->w64.begin = object_property_get_int(pci_host, 263 PCI_HOST_PROP_PCI_HOLE64_START, 264 NULL); 265 info->w64.end = object_property_get_int(pci_host, 266 PCI_HOST_PROP_PCI_HOLE64_END, 267 NULL); 268 } 269 270 #define ACPI_BUILD_APPNAME "Bochs" 271 #define ACPI_BUILD_APPNAME6 "BOCHS " 272 #define ACPI_BUILD_APPNAME4 "BXPC" 273 274 #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables" 275 #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp" 276 #define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log" 277 278 static void 279 build_header(GArray *linker, GArray *table_data, 280 AcpiTableHeader *h, const char *sig, int len, uint8_t rev) 281 { 282 memcpy(&h->signature, sig, 4); 283 h->length = cpu_to_le32(len); 284 h->revision = rev; 285 memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6); 286 memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4); 287 memcpy(h->oem_table_id + 4, sig, 4); 288 h->oem_revision = cpu_to_le32(1); 289 memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4); 290 h->asl_compiler_revision = cpu_to_le32(1); 291 h->checksum = 0; 292 /* Checksum to be filled in by Guest linker */ 293 bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE, 294 table_data->data, h, len, &h->checksum); 295 } 296 297 /* End here */ 298 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 299 300 static inline void *acpi_data_push(GArray *table_data, unsigned size) 301 { 302 unsigned off = table_data->len; 303 g_array_set_size(table_data, off + size); 304 return table_data->data + off; 305 } 306 307 static unsigned acpi_data_len(GArray *table) 308 { 309 #if GLIB_CHECK_VERSION(2, 22, 0) 310 assert(g_array_get_element_size(table) == 1); 311 #endif 312 return table->len; 313 } 314 315 static void acpi_align_size(GArray *blob, unsigned align) 316 { 317 /* Align size to multiple of given size. This reduces the chance 318 * we need to change size in the future (breaking cross version migration). 319 */ 320 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 321 } 322 323 static inline void acpi_add_table(GArray *table_offsets, GArray *table_data) 324 { 325 uint32_t offset = cpu_to_le32(table_data->len); 326 g_array_append_val(table_offsets, offset); 327 } 328 329 /* FACS */ 330 static void 331 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 332 { 333 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 334 memcpy(&facs->signature, "FACS", 4); 335 facs->length = cpu_to_le32(sizeof(*facs)); 336 } 337 338 /* Load chipset information in FADT */ 339 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 340 { 341 fadt->model = 1; 342 fadt->reserved1 = 0; 343 fadt->sci_int = cpu_to_le16(pm->sci_int); 344 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 345 fadt->acpi_enable = pm->acpi_enable_cmd; 346 fadt->acpi_disable = pm->acpi_disable_cmd; 347 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 348 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 349 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 350 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 351 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 352 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 353 fadt->pm1_evt_len = 4; 354 fadt->pm1_cnt_len = 2; 355 fadt->pm_tmr_len = 4; 356 fadt->gpe0_blk_len = pm->gpe0_blk_len; 357 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 358 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 359 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 360 (1 << ACPI_FADT_F_PROC_C1) | 361 (1 << ACPI_FADT_F_SLP_BUTTON) | 362 (1 << ACPI_FADT_F_RTC_S4)); 363 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 364 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 365 * For more than 8 CPUs, "Clustered Logical" mode has to be used 366 */ 367 if (max_cpus > 8) { 368 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 369 } 370 } 371 372 373 /* FADT */ 374 static void 375 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 376 unsigned facs, unsigned dsdt) 377 { 378 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 379 380 fadt->firmware_ctrl = cpu_to_le32(facs); 381 /* FACS address to be filled by Guest linker */ 382 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 383 ACPI_BUILD_TABLE_FILE, 384 table_data, &fadt->firmware_ctrl, 385 sizeof fadt->firmware_ctrl); 386 387 fadt->dsdt = cpu_to_le32(dsdt); 388 /* DSDT address to be filled by Guest linker */ 389 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 390 ACPI_BUILD_TABLE_FILE, 391 table_data, &fadt->dsdt, 392 sizeof fadt->dsdt); 393 394 fadt_setup(fadt, pm); 395 396 build_header(linker, table_data, 397 (void *)fadt, "FACP", sizeof(*fadt), 1); 398 } 399 400 static void 401 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, 402 PcGuestInfo *guest_info) 403 { 404 int madt_start = table_data->len; 405 406 AcpiMultipleApicTable *madt; 407 AcpiMadtIoApic *io_apic; 408 AcpiMadtIntsrcovr *intsrcovr; 409 AcpiMadtLocalNmi *local_nmi; 410 int i; 411 412 madt = acpi_data_push(table_data, sizeof *madt); 413 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 414 madt->flags = cpu_to_le32(1); 415 416 for (i = 0; i < guest_info->apic_id_limit; i++) { 417 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 418 apic->type = ACPI_APIC_PROCESSOR; 419 apic->length = sizeof(*apic); 420 apic->processor_id = i; 421 apic->local_apic_id = i; 422 if (test_bit(i, cpu->found_cpus)) { 423 apic->flags = cpu_to_le32(1); 424 } else { 425 apic->flags = cpu_to_le32(0); 426 } 427 } 428 io_apic = acpi_data_push(table_data, sizeof *io_apic); 429 io_apic->type = ACPI_APIC_IO; 430 io_apic->length = sizeof(*io_apic); 431 #define ACPI_BUILD_IOAPIC_ID 0x0 432 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 433 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 434 io_apic->interrupt = cpu_to_le32(0); 435 436 if (guest_info->apic_xrupt_override) { 437 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 438 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 439 intsrcovr->length = sizeof(*intsrcovr); 440 intsrcovr->source = 0; 441 intsrcovr->gsi = cpu_to_le32(2); 442 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 443 } 444 for (i = 1; i < 16; i++) { 445 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 446 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 447 /* No need for a INT source override structure. */ 448 continue; 449 } 450 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 451 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 452 intsrcovr->length = sizeof(*intsrcovr); 453 intsrcovr->source = i; 454 intsrcovr->gsi = cpu_to_le32(i); 455 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 456 } 457 458 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 459 local_nmi->type = ACPI_APIC_LOCAL_NMI; 460 local_nmi->length = sizeof(*local_nmi); 461 local_nmi->processor_id = 0xff; /* all processors */ 462 local_nmi->flags = cpu_to_le16(0); 463 local_nmi->lint = 1; /* ACPI_LINT1 */ 464 465 build_header(linker, table_data, 466 (void *)(table_data->data + madt_start), "APIC", 467 table_data->len - madt_start, 1); 468 } 469 470 #include "hw/i386/ssdt-tpm.hex" 471 472 /* Assign BSEL property to all buses. In the future, this can be changed 473 * to only assign to buses that support hotplug. 474 */ 475 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 476 { 477 unsigned *bsel_alloc = opaque; 478 unsigned *bus_bsel; 479 480 if (qbus_is_hotpluggable(BUS(bus))) { 481 bus_bsel = g_malloc(sizeof *bus_bsel); 482 483 *bus_bsel = (*bsel_alloc)++; 484 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 485 bus_bsel, NULL); 486 } 487 488 return bsel_alloc; 489 } 490 491 static void acpi_set_pci_info(void) 492 { 493 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 494 unsigned bsel_alloc = 0; 495 496 if (bus) { 497 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 498 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 499 } 500 } 501 502 static void build_append_pcihp_notify_entry(Aml *method, int slot) 503 { 504 Aml *if_ctx; 505 int32_t devfn = PCI_DEVFN(slot, 0); 506 507 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot))); 508 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 509 aml_append(method, if_ctx); 510 } 511 512 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 513 bool pcihp_bridge_en) 514 { 515 Aml *dev, *notify_method, *method; 516 QObject *bsel; 517 PCIBus *sec; 518 int i; 519 520 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 521 if (bsel) { 522 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 523 524 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 525 notify_method = aml_method("DVNT", 2); 526 } 527 528 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 529 DeviceClass *dc; 530 PCIDeviceClass *pc; 531 PCIDevice *pdev = bus->devices[i]; 532 int slot = PCI_SLOT(i); 533 bool hotplug_enabled_dev; 534 bool bridge_in_acpi; 535 536 if (!pdev) { 537 if (bsel) { /* add hotplug slots for non present devices */ 538 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 539 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 540 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 541 method = aml_method("_EJ0", 1); 542 aml_append(method, 543 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 544 ); 545 aml_append(dev, method); 546 aml_append(parent_scope, dev); 547 548 build_append_pcihp_notify_entry(notify_method, slot); 549 } 550 continue; 551 } 552 553 pc = PCI_DEVICE_GET_CLASS(pdev); 554 dc = DEVICE_GET_CLASS(pdev); 555 556 /* When hotplug for bridges is enabled, bridges are 557 * described in ACPI separately (see build_pci_bus_end). 558 * In this case they aren't themselves hot-pluggable. 559 * Hotplugged bridges *are* hot-pluggable. 560 */ 561 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 562 !DEVICE(pdev)->hotplugged; 563 564 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 565 566 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 567 continue; 568 } 569 570 /* start to compose PCI slot descriptor */ 571 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 572 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 573 574 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 575 /* add VGA specific AML methods */ 576 int s3d; 577 578 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 579 s3d = 3; 580 } else { 581 s3d = 0; 582 } 583 584 method = aml_method("_S1D", 0); 585 aml_append(method, aml_return(aml_int(0))); 586 aml_append(dev, method); 587 588 method = aml_method("_S2D", 0); 589 aml_append(method, aml_return(aml_int(0))); 590 aml_append(dev, method); 591 592 method = aml_method("_S3D", 0); 593 aml_append(method, aml_return(aml_int(s3d))); 594 aml_append(dev, method); 595 } else if (hotplug_enabled_dev) { 596 /* add _SUN/_EJ0 to make slot hotpluggable */ 597 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 598 599 method = aml_method("_EJ0", 1); 600 aml_append(method, 601 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 602 ); 603 aml_append(dev, method); 604 605 if (bsel) { 606 build_append_pcihp_notify_entry(notify_method, slot); 607 } 608 } else if (bridge_in_acpi) { 609 /* 610 * device is coldplugged bridge, 611 * add child device descriptions into its scope 612 */ 613 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 614 615 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 616 } 617 /* slot descriptor has been composed, add it into parent context */ 618 aml_append(parent_scope, dev); 619 } 620 621 if (bsel) { 622 aml_append(parent_scope, notify_method); 623 } 624 625 /* Append PCNT method to notify about events on local and child buses. 626 * Add unconditionally for root since DSDT expects it. 627 */ 628 method = aml_method("PCNT", 0); 629 630 /* If bus supports hotplug select it and notify about local events */ 631 if (bsel) { 632 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 633 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 634 aml_append(method, 635 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 636 ); 637 aml_append(method, 638 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 639 ); 640 } 641 642 /* Notify about child bus events in any case */ 643 if (pcihp_bridge_en) { 644 QLIST_FOREACH(sec, &bus->child, sibling) { 645 int32_t devfn = sec->parent_dev->devfn; 646 647 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 648 } 649 } 650 aml_append(parent_scope, method); 651 } 652 653 static void 654 build_ssdt(GArray *table_data, GArray *linker, 655 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 656 PcPciInfo *pci, PcGuestInfo *guest_info) 657 { 658 MachineState *machine = MACHINE(qdev_get_machine()); 659 uint32_t nr_mem = machine->ram_slots; 660 unsigned acpi_cpus = guest_info->apic_id_limit; 661 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; 662 int i; 663 664 ssdt = init_aml_allocator(); 665 /* The current AML generator can cover the APIC ID range [0..255], 666 * inclusive, for VCPU hotplug. */ 667 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 668 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 669 670 /* Reserve space for header */ 671 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 672 673 scope = aml_scope("\\_SB.PCI0"); 674 /* build PCI0._CRS */ 675 crs = aml_resource_template(); 676 aml_append(crs, 677 aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode, 678 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); 679 aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 680 681 aml_append(crs, 682 aml_word_io(aml_min_fixed, aml_max_fixed, 683 aml_pos_decode, aml_entire_range, 684 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 685 aml_append(crs, 686 aml_word_io(aml_min_fixed, aml_max_fixed, 687 aml_pos_decode, aml_entire_range, 688 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); 689 aml_append(crs, 690 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 691 aml_cacheable, aml_ReadWrite, 692 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 693 aml_append(crs, 694 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 695 aml_non_cacheable, aml_ReadWrite, 696 0, pci->w32.begin, pci->w32.end - 1, 0, 697 pci->w32.end - pci->w32.begin)); 698 if (pci->w64.begin) { 699 aml_append(crs, 700 aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 701 aml_cacheable, aml_ReadWrite, 702 0, pci->w64.begin, pci->w64.end - 1, 0, 703 pci->w64.end - pci->w64.begin)); 704 } 705 aml_append(scope, aml_name_decl("_CRS", crs)); 706 707 /* reserve GPE0 block resources */ 708 dev = aml_device("GPE0"); 709 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 710 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 711 /* device present, functioning, decoding, not shown in UI */ 712 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 713 crs = aml_resource_template(); 714 aml_append(crs, 715 aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 716 ); 717 aml_append(dev, aml_name_decl("_CRS", crs)); 718 aml_append(scope, dev); 719 720 /* reserve PCIHP resources */ 721 if (pm->pcihp_io_len) { 722 dev = aml_device("PHPR"); 723 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 724 aml_append(dev, 725 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 726 /* device present, functioning, decoding, not shown in UI */ 727 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 728 crs = aml_resource_template(); 729 aml_append(crs, 730 aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 731 pm->pcihp_io_len) 732 ); 733 aml_append(dev, aml_name_decl("_CRS", crs)); 734 aml_append(scope, dev); 735 } 736 aml_append(ssdt, scope); 737 738 /* create S3_ / S4_ / S5_ packages if necessary */ 739 scope = aml_scope("\\"); 740 if (!pm->s3_disabled) { 741 pkg = aml_package(4); 742 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 743 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 744 aml_append(pkg, aml_int(0)); /* reserved */ 745 aml_append(pkg, aml_int(0)); /* reserved */ 746 aml_append(scope, aml_name_decl("_S3", pkg)); 747 } 748 749 if (!pm->s4_disabled) { 750 pkg = aml_package(4); 751 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 752 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 753 aml_append(pkg, aml_int(pm->s4_val)); 754 aml_append(pkg, aml_int(0)); /* reserved */ 755 aml_append(pkg, aml_int(0)); /* reserved */ 756 aml_append(scope, aml_name_decl("_S4", pkg)); 757 } 758 759 pkg = aml_package(4); 760 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 761 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 762 aml_append(pkg, aml_int(0)); /* reserved */ 763 aml_append(pkg, aml_int(0)); /* reserved */ 764 aml_append(scope, aml_name_decl("_S5", pkg)); 765 aml_append(ssdt, scope); 766 767 if (misc->applesmc_io_base) { 768 scope = aml_scope("\\_SB.PCI0.ISA"); 769 dev = aml_device("SMC"); 770 771 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 772 /* device present, functioning, decoding, not shown in UI */ 773 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 774 775 crs = aml_resource_template(); 776 aml_append(crs, 777 aml_io(aml_decode16, misc->applesmc_io_base, misc->applesmc_io_base, 778 0x01, APPLESMC_MAX_DATA_LENGTH) 779 ); 780 aml_append(crs, aml_irq_no_flags(6)); 781 aml_append(dev, aml_name_decl("_CRS", crs)); 782 783 aml_append(scope, dev); 784 aml_append(ssdt, scope); 785 } 786 787 if (misc->pvpanic_port) { 788 scope = aml_scope("\\_SB.PCI0.ISA"); 789 790 dev = aml_device("PEVR"); 791 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 792 793 crs = aml_resource_template(); 794 aml_append(crs, 795 aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 796 ); 797 aml_append(dev, aml_name_decl("_CRS", crs)); 798 799 aml_append(dev, aml_operation_region("PEOR", aml_system_io, 800 misc->pvpanic_port, 1)); 801 field = aml_field("PEOR", aml_byte_acc); 802 aml_append(field, aml_named_field("PEPT", 8)); 803 aml_append(dev, field); 804 805 method = aml_method("RDPT", 0); 806 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 807 aml_append(method, aml_return(aml_local(0))); 808 aml_append(dev, method); 809 810 method = aml_method("WRPT", 1); 811 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 812 aml_append(dev, method); 813 814 aml_append(scope, dev); 815 aml_append(ssdt, scope); 816 } 817 818 sb_scope = aml_scope("_SB"); 819 { 820 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 821 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 822 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 823 aml_append(dev, 824 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 825 ); 826 /* device present, functioning, decoding, not shown in UI */ 827 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 828 crs = aml_resource_template(); 829 aml_append(crs, 830 aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 831 pm->cpu_hp_io_len) 832 ); 833 aml_append(dev, aml_name_decl("_CRS", crs)); 834 aml_append(sb_scope, dev); 835 /* declare CPU hotplug MMIO region and PRS field to access it */ 836 aml_append(sb_scope, aml_operation_region( 837 "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 838 field = aml_field("PRST", aml_byte_acc); 839 aml_append(field, aml_named_field("PRS", 256)); 840 aml_append(sb_scope, field); 841 842 /* build Processor object for each processor */ 843 for (i = 0; i < acpi_cpus; i++) { 844 dev = aml_processor(i, 0, 0, "CP%.02X", i); 845 846 method = aml_method("_MAT", 0); 847 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); 848 aml_append(dev, method); 849 850 method = aml_method("_STA", 0); 851 aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); 852 aml_append(dev, method); 853 854 method = aml_method("_EJ0", 1); 855 aml_append(method, 856 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) 857 ); 858 aml_append(dev, method); 859 860 aml_append(sb_scope, dev); 861 } 862 863 /* build this code: 864 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 865 */ 866 /* Arg0 = Processor ID = APIC ID */ 867 method = aml_method("NTFY", 2); 868 for (i = 0; i < acpi_cpus; i++) { 869 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 870 aml_append(ifctx, 871 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 872 ); 873 aml_append(method, ifctx); 874 } 875 aml_append(sb_scope, method); 876 877 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 878 * 879 * Note: The ability to create variable-sized packages was first 880 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 881 * ith up to 255 elements. Windows guests up to win2k8 fail when 882 * VarPackageOp is used. 883 */ 884 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 885 aml_varpackage(acpi_cpus); 886 887 for (i = 0; i < acpi_cpus; i++) { 888 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 889 aml_append(pkg, aml_int(b)); 890 } 891 aml_append(sb_scope, aml_name_decl("CPON", pkg)); 892 893 /* build memory devices */ 894 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 895 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); 896 aml_append(scope, 897 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) 898 ); 899 900 crs = aml_resource_template(); 901 aml_append(crs, 902 aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, 903 pm->mem_hp_io_len) 904 ); 905 aml_append(scope, aml_name_decl("_CRS", crs)); 906 907 aml_append(scope, aml_operation_region( 908 stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io, 909 pm->mem_hp_io_base, pm->mem_hp_io_len) 910 ); 911 912 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc); 913 aml_append(field, /* read only */ 914 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); 915 aml_append(field, /* read only */ 916 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); 917 aml_append(field, /* read only */ 918 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); 919 aml_append(field, /* read only */ 920 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); 921 aml_append(field, /* read only */ 922 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); 923 aml_append(scope, field); 924 925 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc); 926 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 927 aml_append(field, /* 1 if enabled, read only */ 928 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); 929 aml_append(field, 930 /*(read) 1 if has a insert event. (write) 1 to clear event */ 931 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); 932 aml_append(scope, field); 933 934 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc); 935 aml_append(field, /* DIMM selector, write only */ 936 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); 937 aml_append(field, /* _OST event code, write only */ 938 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); 939 aml_append(field, /* _OST status code, write only */ 940 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); 941 aml_append(scope, field); 942 943 aml_append(sb_scope, scope); 944 945 for (i = 0; i < nr_mem; i++) { 946 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." 947 const char *s; 948 949 dev = aml_device("MP%02X", i); 950 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 951 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 952 953 method = aml_method("_CRS", 0); 954 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); 955 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 956 aml_append(dev, method); 957 958 method = aml_method("_STA", 0); 959 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); 960 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 961 aml_append(dev, method); 962 963 method = aml_method("_PXM", 0); 964 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); 965 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 966 aml_append(dev, method); 967 968 method = aml_method("_OST", 3); 969 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); 970 aml_append(method, aml_return(aml_call4( 971 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 972 ))); 973 aml_append(dev, method); 974 975 aml_append(sb_scope, dev); 976 } 977 978 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 979 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... 980 */ 981 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2); 982 for (i = 0; i < nr_mem; i++) { 983 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 984 aml_append(ifctx, 985 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 986 ); 987 aml_append(method, ifctx); 988 } 989 aml_append(sb_scope, method); 990 991 { 992 Object *pci_host; 993 PCIBus *bus = NULL; 994 bool ambiguous; 995 996 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 997 if (!ambiguous && pci_host) { 998 bus = PCI_HOST_BRIDGE(pci_host)->bus; 999 } 1000 1001 if (bus) { 1002 Aml *scope = aml_scope("PCI0"); 1003 /* Scan all PCI buses. Generate tables to support hotplug. */ 1004 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1005 aml_append(sb_scope, scope); 1006 } 1007 } 1008 aml_append(ssdt, sb_scope); 1009 } 1010 1011 /* copy AML table into ACPI tables blob and patch header there */ 1012 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); 1013 build_header(linker, table_data, 1014 (void *)(table_data->data + table_data->len - ssdt->buf->len), 1015 "SSDT", ssdt->buf->len, 1); 1016 free_aml_allocator(); 1017 } 1018 1019 static void 1020 build_hpet(GArray *table_data, GArray *linker) 1021 { 1022 Acpi20Hpet *hpet; 1023 1024 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1025 /* Note timer_block_id value must be kept in sync with value advertised by 1026 * emulated hpet 1027 */ 1028 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1029 hpet->addr.address = cpu_to_le64(HPET_BASE); 1030 build_header(linker, table_data, 1031 (void *)hpet, "HPET", sizeof(*hpet), 1); 1032 } 1033 1034 static void 1035 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 1036 { 1037 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1038 uint64_t log_area_start_address = acpi_data_len(tcpalog); 1039 1040 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1041 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1042 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 1043 1044 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 1045 false /* high memory */); 1046 1047 /* log area start address to be filled by Guest linker */ 1048 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1049 ACPI_BUILD_TPMLOG_FILE, 1050 table_data, &tcpa->log_area_start_address, 1051 sizeof(tcpa->log_area_start_address)); 1052 1053 build_header(linker, table_data, 1054 (void *)tcpa, "TCPA", sizeof(*tcpa), 2); 1055 1056 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1057 } 1058 1059 static void 1060 build_tpm_ssdt(GArray *table_data, GArray *linker) 1061 { 1062 void *tpm_ptr; 1063 1064 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml)); 1065 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml)); 1066 } 1067 1068 typedef enum { 1069 MEM_AFFINITY_NOFLAGS = 0, 1070 MEM_AFFINITY_ENABLED = (1 << 0), 1071 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 1072 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 1073 } MemoryAffinityFlags; 1074 1075 static void 1076 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 1077 uint64_t len, int node, MemoryAffinityFlags flags) 1078 { 1079 numamem->type = ACPI_SRAT_MEMORY; 1080 numamem->length = sizeof(*numamem); 1081 memset(numamem->proximity, 0, 4); 1082 numamem->proximity[0] = node; 1083 numamem->flags = cpu_to_le32(flags); 1084 numamem->base_addr = cpu_to_le64(base); 1085 numamem->range_length = cpu_to_le64(len); 1086 } 1087 1088 static void 1089 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 1090 { 1091 AcpiSystemResourceAffinityTable *srat; 1092 AcpiSratProcessorAffinity *core; 1093 AcpiSratMemoryAffinity *numamem; 1094 1095 int i; 1096 uint64_t curnode; 1097 int srat_start, numa_start, slots; 1098 uint64_t mem_len, mem_base, next_base; 1099 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1100 ram_addr_t hotplugabble_address_space_size = 1101 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 1102 NULL); 1103 1104 srat_start = table_data->len; 1105 1106 srat = acpi_data_push(table_data, sizeof *srat); 1107 srat->reserved1 = cpu_to_le32(1); 1108 core = (void *)(srat + 1); 1109 1110 for (i = 0; i < guest_info->apic_id_limit; ++i) { 1111 core = acpi_data_push(table_data, sizeof *core); 1112 core->type = ACPI_SRAT_PROCESSOR; 1113 core->length = sizeof(*core); 1114 core->local_apic_id = i; 1115 curnode = guest_info->node_cpu[i]; 1116 core->proximity_lo = curnode; 1117 memset(core->proximity_hi, 0, 3); 1118 core->local_sapic_eid = 0; 1119 core->flags = cpu_to_le32(1); 1120 } 1121 1122 1123 /* the memory map is a bit tricky, it contains at least one hole 1124 * from 640k-1M and possibly another one from 3.5G-4G. 1125 */ 1126 next_base = 0; 1127 numa_start = table_data->len; 1128 1129 numamem = acpi_data_push(table_data, sizeof *numamem); 1130 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 1131 next_base = 1024 * 1024; 1132 for (i = 1; i < guest_info->numa_nodes + 1; ++i) { 1133 mem_base = next_base; 1134 mem_len = guest_info->node_mem[i - 1]; 1135 if (i == 1) { 1136 mem_len -= 1024 * 1024; 1137 } 1138 next_base = mem_base + mem_len; 1139 1140 /* Cut out the ACPI_PCI hole */ 1141 if (mem_base <= guest_info->ram_size_below_4g && 1142 next_base > guest_info->ram_size_below_4g) { 1143 mem_len -= next_base - guest_info->ram_size_below_4g; 1144 if (mem_len > 0) { 1145 numamem = acpi_data_push(table_data, sizeof *numamem); 1146 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1147 MEM_AFFINITY_ENABLED); 1148 } 1149 mem_base = 1ULL << 32; 1150 mem_len = next_base - guest_info->ram_size_below_4g; 1151 next_base += (1ULL << 32) - guest_info->ram_size_below_4g; 1152 } 1153 numamem = acpi_data_push(table_data, sizeof *numamem); 1154 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1155 MEM_AFFINITY_ENABLED); 1156 } 1157 slots = (table_data->len - numa_start) / sizeof *numamem; 1158 for (; slots < guest_info->numa_nodes + 2; slots++) { 1159 numamem = acpi_data_push(table_data, sizeof *numamem); 1160 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1161 } 1162 1163 /* 1164 * Entry is required for Windows to enable memory hotplug in OS. 1165 * Memory devices may override proximity set by this entry, 1166 * providing _PXM method if necessary. 1167 */ 1168 if (hotplugabble_address_space_size) { 1169 numamem = acpi_data_push(table_data, sizeof *numamem); 1170 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base, 1171 hotplugabble_address_space_size, 0, 1172 MEM_AFFINITY_HOTPLUGGABLE | 1173 MEM_AFFINITY_ENABLED); 1174 } 1175 1176 build_header(linker, table_data, 1177 (void *)(table_data->data + srat_start), 1178 "SRAT", 1179 table_data->len - srat_start, 1); 1180 } 1181 1182 static void 1183 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 1184 { 1185 AcpiTableMcfg *mcfg; 1186 const char *sig; 1187 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 1188 1189 mcfg = acpi_data_push(table_data, len); 1190 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 1191 /* Only a single allocation so no need to play with segments */ 1192 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 1193 mcfg->allocation[0].start_bus_number = 0; 1194 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 1195 1196 /* MCFG is used for ECAM which can be enabled or disabled by guest. 1197 * To avoid table size changes (which create migration issues), 1198 * always create the table even if there are no allocations, 1199 * but set the signature to a reserved value in this case. 1200 * ACPI spec requires OSPMs to ignore such tables. 1201 */ 1202 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 1203 /* Reserved signature: ignored by OSPM */ 1204 sig = "QEMU"; 1205 } else { 1206 sig = "MCFG"; 1207 } 1208 build_header(linker, table_data, (void *)mcfg, sig, len, 1); 1209 } 1210 1211 static void 1212 build_dmar_q35(GArray *table_data, GArray *linker) 1213 { 1214 int dmar_start = table_data->len; 1215 1216 AcpiTableDmar *dmar; 1217 AcpiDmarHardwareUnit *drhd; 1218 1219 dmar = acpi_data_push(table_data, sizeof(*dmar)); 1220 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 1221 dmar->flags = 0; /* No intr_remap for now */ 1222 1223 /* DMAR Remapping Hardware Unit Definition structure */ 1224 drhd = acpi_data_push(table_data, sizeof(*drhd)); 1225 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 1226 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 1227 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 1228 drhd->pci_segment = cpu_to_le16(0); 1229 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 1230 1231 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 1232 "DMAR", table_data->len - dmar_start, 1); 1233 } 1234 1235 static void 1236 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) 1237 { 1238 AcpiTableHeader *dsdt; 1239 1240 assert(misc->dsdt_code && misc->dsdt_size); 1241 1242 dsdt = acpi_data_push(table_data, misc->dsdt_size); 1243 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); 1244 1245 memset(dsdt, 0, sizeof *dsdt); 1246 build_header(linker, table_data, dsdt, "DSDT", 1247 misc->dsdt_size, 1); 1248 } 1249 1250 /* Build final rsdt table */ 1251 static void 1252 build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets) 1253 { 1254 AcpiRsdtDescriptorRev1 *rsdt; 1255 size_t rsdt_len; 1256 int i; 1257 1258 rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len; 1259 rsdt = acpi_data_push(table_data, rsdt_len); 1260 memcpy(rsdt->table_offset_entry, table_offsets->data, 1261 sizeof(uint32_t) * table_offsets->len); 1262 for (i = 0; i < table_offsets->len; ++i) { 1263 /* rsdt->table_offset_entry to be filled by Guest linker */ 1264 bios_linker_loader_add_pointer(linker, 1265 ACPI_BUILD_TABLE_FILE, 1266 ACPI_BUILD_TABLE_FILE, 1267 table_data, &rsdt->table_offset_entry[i], 1268 sizeof(uint32_t)); 1269 } 1270 build_header(linker, table_data, 1271 (void *)rsdt, "RSDT", rsdt_len, 1); 1272 } 1273 1274 static GArray * 1275 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 1276 { 1277 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 1278 1279 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 1280 true /* fseg memory */); 1281 1282 memcpy(&rsdp->signature, "RSD PTR ", 8); 1283 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 1284 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 1285 /* Address to be filled by Guest linker */ 1286 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 1287 ACPI_BUILD_TABLE_FILE, 1288 rsdp_table, &rsdp->rsdt_physical_address, 1289 sizeof rsdp->rsdt_physical_address); 1290 rsdp->checksum = 0; 1291 /* Checksum to be filled by Guest linker */ 1292 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 1293 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 1294 1295 return rsdp_table; 1296 } 1297 1298 typedef 1299 struct AcpiBuildTables { 1300 GArray *table_data; 1301 GArray *rsdp; 1302 GArray *tcpalog; 1303 GArray *linker; 1304 } AcpiBuildTables; 1305 1306 static inline void acpi_build_tables_init(AcpiBuildTables *tables) 1307 { 1308 tables->rsdp = g_array_new(false, true /* clear */, 1); 1309 tables->table_data = g_array_new(false, true /* clear */, 1); 1310 tables->tcpalog = g_array_new(false, true /* clear */, 1); 1311 tables->linker = bios_linker_loader_init(); 1312 } 1313 1314 static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) 1315 { 1316 void *linker_data = bios_linker_loader_cleanup(tables->linker); 1317 g_free(linker_data); 1318 g_array_free(tables->rsdp, true); 1319 g_array_free(tables->table_data, true); 1320 g_array_free(tables->tcpalog, mfre); 1321 } 1322 1323 typedef 1324 struct AcpiBuildState { 1325 /* Copy of table in RAM (for patching). */ 1326 ram_addr_t table_ram; 1327 /* Is table patched? */ 1328 uint8_t patched; 1329 PcGuestInfo *guest_info; 1330 void *rsdp; 1331 ram_addr_t rsdp_ram; 1332 ram_addr_t linker_ram; 1333 } AcpiBuildState; 1334 1335 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 1336 { 1337 Object *pci_host; 1338 QObject *o; 1339 bool ambiguous; 1340 1341 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 1342 g_assert(!ambiguous); 1343 g_assert(pci_host); 1344 1345 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 1346 if (!o) { 1347 return false; 1348 } 1349 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 1350 qobject_decref(o); 1351 1352 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 1353 assert(o); 1354 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 1355 qobject_decref(o); 1356 return true; 1357 } 1358 1359 static bool acpi_has_iommu(void) 1360 { 1361 bool ambiguous; 1362 Object *intel_iommu; 1363 1364 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 1365 &ambiguous); 1366 return intel_iommu && !ambiguous; 1367 } 1368 1369 static 1370 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) 1371 { 1372 GArray *table_offsets; 1373 unsigned facs, ssdt, dsdt, rsdt; 1374 AcpiCpuInfo cpu; 1375 AcpiPmInfo pm; 1376 AcpiMiscInfo misc; 1377 AcpiMcfgInfo mcfg; 1378 PcPciInfo pci; 1379 uint8_t *u; 1380 size_t aml_len = 0; 1381 GArray *tables_blob = tables->table_data; 1382 1383 acpi_get_cpu_info(&cpu); 1384 acpi_get_pm_info(&pm); 1385 acpi_get_dsdt(&misc); 1386 acpi_get_misc_info(&misc); 1387 acpi_get_pci_info(&pci); 1388 1389 table_offsets = g_array_new(false, true /* clear */, 1390 sizeof(uint32_t)); 1391 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 1392 1393 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 1394 64 /* Ensure FACS is aligned */, 1395 false /* high memory */); 1396 1397 /* 1398 * FACS is pointed to by FADT. 1399 * We place it first since it's the only table that has alignment 1400 * requirements. 1401 */ 1402 facs = tables_blob->len; 1403 build_facs(tables_blob, tables->linker, guest_info); 1404 1405 /* DSDT is pointed to by FADT */ 1406 dsdt = tables_blob->len; 1407 build_dsdt(tables_blob, tables->linker, &misc); 1408 1409 /* Count the size of the DSDT and SSDT, we will need it for legacy 1410 * sizing of ACPI tables. 1411 */ 1412 aml_len += tables_blob->len - dsdt; 1413 1414 /* ACPI tables pointed to by RSDT */ 1415 acpi_add_table(table_offsets, tables_blob); 1416 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); 1417 1418 ssdt = tables_blob->len; 1419 acpi_add_table(table_offsets, tables_blob); 1420 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, 1421 guest_info); 1422 aml_len += tables_blob->len - ssdt; 1423 1424 acpi_add_table(table_offsets, tables_blob); 1425 build_madt(tables_blob, tables->linker, &cpu, guest_info); 1426 1427 if (misc.has_hpet) { 1428 acpi_add_table(table_offsets, tables_blob); 1429 build_hpet(tables_blob, tables->linker); 1430 } 1431 if (misc.has_tpm) { 1432 acpi_add_table(table_offsets, tables_blob); 1433 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 1434 1435 acpi_add_table(table_offsets, tables_blob); 1436 build_tpm_ssdt(tables_blob, tables->linker); 1437 } 1438 if (guest_info->numa_nodes) { 1439 acpi_add_table(table_offsets, tables_blob); 1440 build_srat(tables_blob, tables->linker, guest_info); 1441 } 1442 if (acpi_get_mcfg(&mcfg)) { 1443 acpi_add_table(table_offsets, tables_blob); 1444 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 1445 } 1446 if (acpi_has_iommu()) { 1447 acpi_add_table(table_offsets, tables_blob); 1448 build_dmar_q35(tables_blob, tables->linker); 1449 } 1450 1451 /* Add tables supplied by user (if any) */ 1452 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 1453 unsigned len = acpi_table_len(u); 1454 1455 acpi_add_table(table_offsets, tables_blob); 1456 g_array_append_vals(tables_blob, u, len); 1457 } 1458 1459 /* RSDT is pointed to by RSDP */ 1460 rsdt = tables_blob->len; 1461 build_rsdt(tables_blob, tables->linker, table_offsets); 1462 1463 /* RSDP is in FSEG memory, so allocate it separately */ 1464 build_rsdp(tables->rsdp, tables->linker, rsdt); 1465 1466 /* We'll expose it all to Guest so we want to reduce 1467 * chance of size changes. 1468 * 1469 * We used to align the tables to 4k, but of course this would 1470 * too simple to be enough. 4k turned out to be too small an 1471 * alignment very soon, and in fact it is almost impossible to 1472 * keep the table size stable for all (max_cpus, max_memory_slots) 1473 * combinations. So the table size is always 64k for pc-i440fx-2.1 1474 * and we give an error if the table grows beyond that limit. 1475 * 1476 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 1477 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 1478 * than 2.0 and we can always pad the smaller tables with zeros. We can 1479 * then use the exact size of the 2.0 tables. 1480 * 1481 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 1482 */ 1483 if (guest_info->legacy_acpi_table_size) { 1484 /* Subtracting aml_len gives the size of fixed tables. Then add the 1485 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 1486 */ 1487 int legacy_aml_len = 1488 guest_info->legacy_acpi_table_size + 1489 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 1490 int legacy_table_size = 1491 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 1492 ACPI_BUILD_ALIGN_SIZE); 1493 if (tables_blob->len > legacy_table_size) { 1494 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 1495 error_report("Warning: migration may not work."); 1496 } 1497 g_array_set_size(tables_blob, legacy_table_size); 1498 } else { 1499 /* Make sure we have a buffer in case we need to resize the tables. */ 1500 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1501 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 1502 error_report("Warning: ACPI tables are larger than 64k."); 1503 error_report("Warning: migration may not work."); 1504 error_report("Warning: please remove CPUs, NUMA nodes, " 1505 "memory slots or PCI bridges."); 1506 } 1507 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1508 } 1509 1510 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 1511 1512 /* Cleanup memory that's no longer used. */ 1513 g_array_free(table_offsets, true); 1514 } 1515 1516 static void acpi_ram_update(ram_addr_t ram, GArray *data) 1517 { 1518 uint32_t size = acpi_data_len(data); 1519 1520 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 1521 qemu_ram_resize(ram, size, &error_abort); 1522 1523 memcpy(qemu_get_ram_ptr(ram), data->data, size); 1524 cpu_physical_memory_set_dirty_range_nocode(ram, size); 1525 } 1526 1527 static void acpi_build_update(void *build_opaque, uint32_t offset) 1528 { 1529 AcpiBuildState *build_state = build_opaque; 1530 AcpiBuildTables tables; 1531 1532 /* No state to update or already patched? Nothing to do. */ 1533 if (!build_state || build_state->patched) { 1534 return; 1535 } 1536 build_state->patched = 1; 1537 1538 acpi_build_tables_init(&tables); 1539 1540 acpi_build(build_state->guest_info, &tables); 1541 1542 acpi_ram_update(build_state->table_ram, tables.table_data); 1543 1544 if (build_state->rsdp) { 1545 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 1546 } else { 1547 acpi_ram_update(build_state->rsdp_ram, tables.rsdp); 1548 } 1549 1550 acpi_ram_update(build_state->linker_ram, tables.linker); 1551 acpi_build_tables_cleanup(&tables, true); 1552 } 1553 1554 static void acpi_build_reset(void *build_opaque) 1555 { 1556 AcpiBuildState *build_state = build_opaque; 1557 build_state->patched = 0; 1558 } 1559 1560 static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob, 1561 const char *name, uint64_t max_size) 1562 { 1563 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 1564 name, acpi_build_update, build_state); 1565 } 1566 1567 static const VMStateDescription vmstate_acpi_build = { 1568 .name = "acpi_build", 1569 .version_id = 1, 1570 .minimum_version_id = 1, 1571 .fields = (VMStateField[]) { 1572 VMSTATE_UINT8(patched, AcpiBuildState), 1573 VMSTATE_END_OF_LIST() 1574 }, 1575 }; 1576 1577 void acpi_setup(PcGuestInfo *guest_info) 1578 { 1579 AcpiBuildTables tables; 1580 AcpiBuildState *build_state; 1581 1582 if (!guest_info->fw_cfg) { 1583 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 1584 return; 1585 } 1586 1587 if (!guest_info->has_acpi_build) { 1588 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 1589 return; 1590 } 1591 1592 if (!acpi_enabled) { 1593 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 1594 return; 1595 } 1596 1597 build_state = g_malloc0(sizeof *build_state); 1598 1599 build_state->guest_info = guest_info; 1600 1601 acpi_set_pci_info(); 1602 1603 acpi_build_tables_init(&tables); 1604 acpi_build(build_state->guest_info, &tables); 1605 1606 /* Now expose it all to Guest */ 1607 build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data, 1608 ACPI_BUILD_TABLE_FILE, 1609 ACPI_BUILD_TABLE_MAX_SIZE); 1610 assert(build_state->table_ram != RAM_ADDR_MAX); 1611 1612 build_state->linker_ram = 1613 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 1614 1615 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 1616 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 1617 1618 if (!guest_info->rsdp_in_ram) { 1619 /* 1620 * Keep for compatibility with old machine types. 1621 * Though RSDP is small, its contents isn't immutable, so 1622 * we'll update it along with the rest of tables on guest access. 1623 */ 1624 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 1625 1626 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 1627 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, 1628 acpi_build_update, build_state, 1629 build_state->rsdp, rsdp_size); 1630 build_state->rsdp_ram = (ram_addr_t)-1; 1631 } else { 1632 build_state->rsdp = NULL; 1633 build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp, 1634 ACPI_BUILD_RSDP_FILE, 0); 1635 } 1636 1637 qemu_register_reset(acpi_build_reset, build_state); 1638 acpi_build_reset(build_state); 1639 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 1640 1641 /* Cleanup tables but don't free the memory: we track it 1642 * in build_state. 1643 */ 1644 acpi_build_tables_cleanup(&tables, false); 1645 } 1646