1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/ich9.h" 59 #include "hw/acpi/pcihp.h" 60 #include "hw/i386/fw_cfg.h" 61 #include "hw/i386/pc.h" 62 #include "hw/pci/pci_bus.h" 63 #include "hw/pci-host/i440fx.h" 64 #include "hw/pci-host/q35.h" 65 #include "hw/i386/x86-iommu.h" 66 67 #include "hw/acpi/aml-build.h" 68 #include "hw/acpi/utils.h" 69 #include "hw/acpi/pci.h" 70 #include "hw/acpi/cxl.h" 71 #include "hw/acpi/acpi_generic_initiator.h" 72 73 #include "qom/qom-qobject.h" 74 #include "hw/i386/amd_iommu.h" 75 #include "hw/i386/intel_iommu.h" 76 #include "hw/virtio/virtio-iommu.h" 77 78 #include "hw/acpi/hmat.h" 79 #include "hw/acpi/viot.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_ALIGN_SIZE 0x1000 89 90 #define ACPI_BUILD_TABLE_SIZE 0x20000 91 92 /* #define DEBUG_ACPI_BUILD */ 93 #ifdef DEBUG_ACPI_BUILD 94 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 96 #else 97 #define ACPI_BUILD_DPRINTF(fmt, ...) 98 #endif 99 100 typedef struct AcpiPmInfo { 101 bool s3_disabled; 102 bool s4_disabled; 103 bool pcihp_bridge_en; 104 bool smi_on_cpuhp; 105 bool smi_on_cpu_unplug; 106 bool pcihp_root_en; 107 uint8_t s4_val; 108 AcpiFadtData fadt; 109 uint16_t cpu_hp_io_base; 110 uint16_t pcihp_io_base; 111 uint16_t pcihp_io_len; 112 } AcpiPmInfo; 113 114 typedef struct AcpiMiscInfo { 115 bool has_hpet; 116 #ifdef CONFIG_TPM 117 TPMVersion tpm_version; 118 #endif 119 } AcpiMiscInfo; 120 121 typedef struct FwCfgTPMConfig { 122 uint32_t tpmppi_address; 123 uint8_t tpm_version; 124 uint8_t tpmppi_version; 125 } QEMU_PACKED FwCfgTPMConfig; 126 127 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 128 129 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 130 .space_id = AML_AS_SYSTEM_IO, 131 .address = NVDIMM_ACPI_IO_BASE, 132 .bit_width = NVDIMM_ACPI_IO_LEN << 3 133 }; 134 135 static void init_common_fadt_data(MachineState *ms, Object *o, 136 AcpiFadtData *data) 137 { 138 X86MachineState *x86ms = X86_MACHINE(ms); 139 /* 140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 141 * behavior for compatibility irrelevant to smm_enabled, which doesn't 142 * comforms to ACPI spec. 143 */ 144 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 145 true : x86_machine_is_smm_enabled(x86ms); 146 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 147 AmlAddressSpace as = AML_AS_SYSTEM_IO; 148 AcpiFadtData fadt = { 149 .rev = 3, 150 .flags = 151 (1 << ACPI_FADT_F_WBINVD) | 152 (1 << ACPI_FADT_F_PROC_C1) | 153 (1 << ACPI_FADT_F_SLP_BUTTON) | 154 (1 << ACPI_FADT_F_RTC_S4) | 155 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 156 /* APIC destination mode ("Flat Logical") has an upper limit of 8 157 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 158 * used 159 */ 160 ((ms->smp.max_cpus > 8) ? 161 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 162 .int_model = 1 /* Multiple APIC */, 163 .rtc_century = RTC_CENTURY, 164 .plvl2_lat = 0xfff /* C2 state not supported */, 165 .plvl3_lat = 0xfff /* C3 state not supported */, 166 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 167 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 168 .acpi_enable_cmd = 169 smm_enabled ? 170 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 171 0, 172 .acpi_disable_cmd = 173 smm_enabled ? 174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 175 0, 176 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 177 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 178 .address = io + 0x04 }, 179 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 180 .gpe0_blk = { .space_id = as, .bit_width = 181 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 182 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 183 }, 184 }; 185 186 /* 187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 188 * Flags, bit offset 1 - 8042. 189 */ 190 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 191 192 *data = fadt; 193 } 194 195 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 196 { 197 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL); 198 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL); 199 Object *obj = piix ? piix : lpc; 200 QObject *o; 201 pm->cpu_hp_io_base = 0; 202 pm->pcihp_io_base = 0; 203 pm->pcihp_io_len = 0; 204 pm->smi_on_cpuhp = false; 205 pm->smi_on_cpu_unplug = false; 206 207 assert(obj); 208 init_common_fadt_data(machine, obj, &pm->fadt); 209 if (piix) { 210 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 211 pm->fadt.rev = 1; 212 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 213 } 214 if (lpc) { 215 uint64_t smi_features = object_property_get_uint(lpc, 216 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 217 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 218 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 219 pm->fadt.reset_reg = r; 220 pm->fadt.reset_val = 0xf; 221 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 222 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 223 pm->smi_on_cpuhp = 224 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 225 pm->smi_on_cpu_unplug = 226 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 227 } 228 pm->pcihp_io_base = 229 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 230 pm->pcihp_io_len = 231 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 232 233 /* Fill in optional s3/s4 related properties */ 234 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 235 if (o) { 236 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 237 } else { 238 pm->s3_disabled = false; 239 } 240 qobject_unref(o); 241 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 242 if (o) { 243 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 244 } else { 245 pm->s4_disabled = false; 246 } 247 qobject_unref(o); 248 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 249 if (o) { 250 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 251 } else { 252 pm->s4_val = false; 253 } 254 qobject_unref(o); 255 256 pm->pcihp_bridge_en = 257 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 258 NULL); 259 pm->pcihp_root_en = 260 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 261 NULL); 262 } 263 264 static void acpi_get_misc_info(AcpiMiscInfo *info) 265 { 266 info->has_hpet = hpet_find(); 267 #ifdef CONFIG_TPM 268 info->tpm_version = tpm_get_version(tpm_find()); 269 #endif 270 } 271 272 /* 273 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 274 * On i386 arch we only have two pci hosts, so we can look only for them. 275 */ 276 Object *acpi_get_i386_pci_host(void) 277 { 278 PCIHostState *host; 279 280 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 281 if (!host) { 282 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 283 } 284 285 return OBJECT(host); 286 } 287 288 static void acpi_get_pci_holes(Range *hole, Range *hole64) 289 { 290 Object *pci_host; 291 292 pci_host = acpi_get_i386_pci_host(); 293 294 if (!pci_host) { 295 return; 296 } 297 298 range_set_bounds1(hole, 299 object_property_get_uint(pci_host, 300 PCI_HOST_PROP_PCI_HOLE_START, 301 NULL), 302 object_property_get_uint(pci_host, 303 PCI_HOST_PROP_PCI_HOLE_END, 304 NULL)); 305 range_set_bounds1(hole64, 306 object_property_get_uint(pci_host, 307 PCI_HOST_PROP_PCI_HOLE64_START, 308 NULL), 309 object_property_get_uint(pci_host, 310 PCI_HOST_PROP_PCI_HOLE64_END, 311 NULL)); 312 } 313 314 static void acpi_align_size(GArray *blob, unsigned align) 315 { 316 /* Align size to multiple of given size. This reduces the chance 317 * we need to change size in the future (breaking cross version migration). 318 */ 319 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 320 } 321 322 /* 323 * ACPI spec 1.0b, 324 * 5.2.6 Firmware ACPI Control Structure 325 */ 326 static void 327 build_facs(GArray *table_data) 328 { 329 const char *sig = "FACS"; 330 const uint8_t reserved[40] = {}; 331 332 g_array_append_vals(table_data, sig, 4); /* Signature */ 333 build_append_int_noprefix(table_data, 64, 4); /* Length */ 334 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 335 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 336 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 337 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 338 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 339 } 340 341 Aml *aml_pci_device_dsm(void) 342 { 343 Aml *method; 344 345 method = aml_method("_DSM", 4, AML_SERIALIZED); 346 { 347 Aml *params = aml_local(0); 348 Aml *pkg = aml_package(2); 349 aml_append(pkg, aml_int(0)); 350 aml_append(pkg, aml_int(0)); 351 aml_append(method, aml_store(pkg, params)); 352 aml_append(method, 353 aml_store(aml_name("BSEL"), aml_index(params, aml_int(0)))); 354 aml_append(method, 355 aml_store(aml_name("ASUN"), aml_index(params, aml_int(1)))); 356 aml_append(method, 357 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 358 aml_arg(2), aml_arg(3), params)) 359 ); 360 } 361 return method; 362 } 363 364 static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar) 365 { 366 Aml *UUID, *ifctx1; 367 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 368 369 aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar)); 370 /* 371 * PCI Firmware Specification 3.1 372 * 4.6. _DSM Definitions for PCI 373 */ 374 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 375 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 376 { 377 /* call is for unsupported UUID, bail out */ 378 aml_append(ifctx1, aml_return(retvar)); 379 } 380 aml_append(ctx, ifctx1); 381 382 ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2))); 383 { 384 /* call is for unsupported REV, bail out */ 385 aml_append(ifctx1, aml_return(retvar)); 386 } 387 aml_append(ctx, ifctx1); 388 } 389 390 static Aml *aml_pci_edsm(void) 391 { 392 Aml *method, *ifctx; 393 Aml *zero = aml_int(0); 394 Aml *func = aml_arg(2); 395 Aml *ret = aml_local(0); 396 Aml *aidx = aml_local(1); 397 Aml *params = aml_arg(4); 398 399 method = aml_method("EDSM", 5, AML_SERIALIZED); 400 401 /* get supported functions */ 402 ifctx = aml_if(aml_equal(func, zero)); 403 { 404 /* 1: have supported functions */ 405 /* 7: support for function 7 */ 406 const uint8_t caps = 1 | BIT(7); 407 build_append_pci_dsm_func0_common(ifctx, ret); 408 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); 409 aml_append(ifctx, aml_return(ret)); 410 } 411 aml_append(method, ifctx); 412 413 /* handle specific functions requests */ 414 /* 415 * PCI Firmware Specification 3.1 416 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 417 * Operating Systems 418 */ 419 ifctx = aml_if(aml_equal(func, aml_int(7))); 420 { 421 Aml *pkg = aml_package(2); 422 aml_append(pkg, zero); 423 /* optional, if not impl. should return null string */ 424 aml_append(pkg, aml_string("%s", "")); 425 aml_append(ifctx, aml_store(pkg, ret)); 426 427 /* 428 * IASL is fine when initializing Package with computational data, 429 * however it makes guest unhappy /it fails to process such AML/. 430 * So use runtime assignment to set acpi-index after initializer 431 * to make OSPM happy. 432 */ 433 aml_append(ifctx, 434 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); 435 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); 436 aml_append(ifctx, aml_return(ret)); 437 } 438 aml_append(method, ifctx); 439 440 return method; 441 } 442 443 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev) 444 { 445 Aml *method; 446 447 g_assert(pdev->acpi_index != 0); 448 method = aml_method("_DSM", 4, AML_SERIALIZED); 449 { 450 Aml *params = aml_local(0); 451 Aml *pkg = aml_package(1); 452 aml_append(pkg, aml_int(pdev->acpi_index)); 453 aml_append(method, aml_store(pkg, params)); 454 aml_append(method, 455 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1), 456 aml_arg(2), aml_arg(3), params)) 457 ); 458 } 459 return method; 460 } 461 462 static void build_append_pcihp_notify_entry(Aml *method, int slot) 463 { 464 Aml *if_ctx; 465 int32_t devfn = PCI_DEVFN(slot, 0); 466 467 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 468 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 469 aml_append(method, if_ctx); 470 } 471 472 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) 473 { 474 const PCIDevice *pdev = bus->devices[devfn]; 475 476 if (PCI_FUNC(devfn)) { 477 if (IS_PCI_BRIDGE(pdev)) { 478 /* 479 * Ignore only hotplugged PCI bridges on !0 functions, but 480 * allow describing cold plugged bridges on all functions 481 */ 482 if (DEVICE(pdev)->hotplugged) { 483 return true; 484 } 485 } 486 } 487 return false; 488 } 489 490 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) 491 { 492 PCIDevice *pdev = bus->devices[devfn]; 493 if (pdev) { 494 return is_devfn_ignored_generic(devfn, bus) || 495 !DEVICE_GET_CLASS(pdev)->hotpluggable || 496 /* Cold plugged bridges aren't themselves hot-pluggable */ 497 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); 498 } else { /* non populated slots */ 499 /* 500 * hotplug is supported only for non-multifunction device 501 * so generate device description only for function 0 502 */ 503 if (PCI_FUNC(devfn) || 504 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { 505 return true; 506 } 507 } 508 return false; 509 } 510 511 void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus) 512 { 513 int devfn; 514 Aml *dev, *notify_method = NULL, *method; 515 QObject *bsel = object_property_get_qobject(OBJECT(bus), 516 ACPI_PCIHP_PROP_BSEL, NULL); 517 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 518 qobject_unref(bsel); 519 520 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 521 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 522 523 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 524 int slot = PCI_SLOT(devfn); 525 int adr = slot << 16 | PCI_FUNC(devfn); 526 527 if (is_devfn_ignored_hotplug(devfn, bus)) { 528 continue; 529 } 530 531 if (bus->devices[devfn]) { 532 dev = aml_scope("S%.02X", devfn); 533 } else { 534 dev = aml_device("S%.02X", devfn); 535 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 536 } 537 538 /* 539 * Can't declare _SUN here for every device as it changes 'slot' 540 * enumeration order in linux kernel, so use another variable for it 541 */ 542 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 543 aml_append(dev, aml_pci_device_dsm()); 544 545 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 546 /* add _EJ0 to make slot hotpluggable */ 547 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 548 aml_append(method, 549 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 550 ); 551 aml_append(dev, method); 552 553 build_append_pcihp_notify_entry(notify_method, slot); 554 555 /* device descriptor has been composed, add it into parent context */ 556 aml_append(parent_scope, dev); 557 } 558 aml_append(parent_scope, notify_method); 559 } 560 561 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) 562 { 563 int devfn; 564 Aml *dev; 565 566 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 567 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 568 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); 569 PCIDevice *pdev = bus->devices[devfn]; 570 571 if (!pdev || is_devfn_ignored_generic(devfn, bus)) { 572 continue; 573 } 574 575 /* start to compose PCI device descriptor */ 576 dev = aml_device("S%.02X", devfn); 577 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 578 579 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); 580 /* add _DSM if device has acpi-index set */ 581 if (pdev->acpi_index && 582 !object_property_get_bool(OBJECT(pdev), "hotpluggable", 583 &error_abort)) { 584 aml_append(dev, aml_pci_static_endpoint_dsm(pdev)); 585 } 586 587 /* device descriptor has been composed, add it into parent context */ 588 aml_append(parent_scope, dev); 589 } 590 } 591 592 static bool build_append_notfication_callback(Aml *parent_scope, 593 const PCIBus *bus) 594 { 595 Aml *method; 596 PCIBus *sec; 597 QObject *bsel; 598 int nr_notifiers = 0; 599 GQueue *pcnt_bus_list = g_queue_new(); 600 601 QLIST_FOREACH(sec, &bus->child, sibling) { 602 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn); 603 if (pci_bus_is_root(sec)) { 604 continue; 605 } 606 nr_notifiers = nr_notifiers + 607 build_append_notfication_callback(br_scope, sec); 608 /* 609 * add new child scope to parent 610 * and keep track of bus that have PCNT, 611 * bus list is used later to call children PCNTs from this level PCNT 612 */ 613 if (nr_notifiers) { 614 g_queue_push_tail(pcnt_bus_list, sec); 615 aml_append(parent_scope, br_scope); 616 } 617 } 618 619 /* 620 * Append PCNT method to notify about events on local and child buses. 621 * ps: hostbridge might not have hotplug (bsel) enabled but might have 622 * child bridges that do have bsel. 623 */ 624 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 625 626 /* If bus supports hotplug select it and notify about local events */ 627 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 628 if (bsel) { 629 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 630 631 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 632 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 633 aml_int(1))); /* Device Check */ 634 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 635 aml_int(3))); /* Eject Request */ 636 nr_notifiers++; 637 } 638 639 /* Notify about child bus events in any case */ 640 while ((sec = g_queue_pop_head(pcnt_bus_list))) { 641 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn)); 642 } 643 644 aml_append(parent_scope, method); 645 qobject_unref(bsel); 646 g_queue_free(pcnt_bus_list); 647 return !!nr_notifiers; 648 } 649 650 static Aml *aml_pci_pdsm(void) 651 { 652 Aml *method, *ifctx, *ifctx1; 653 Aml *ret = aml_local(0); 654 Aml *caps = aml_local(1); 655 Aml *acpi_index = aml_local(2); 656 Aml *zero = aml_int(0); 657 Aml *one = aml_int(1); 658 Aml *func = aml_arg(2); 659 Aml *params = aml_arg(4); 660 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 661 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 662 663 method = aml_method("PDSM", 5, AML_SERIALIZED); 664 665 /* get supported functions */ 666 ifctx = aml_if(aml_equal(func, zero)); 667 { 668 build_append_pci_dsm_func0_common(ifctx, ret); 669 670 aml_append(ifctx, aml_store(zero, caps)); 671 aml_append(ifctx, 672 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 673 /* 674 * advertise function 7 if device has acpi-index 675 * acpi_index values: 676 * 0: not present (default value) 677 * FFFFFFFF: not supported (old QEMU without PIDX reg) 678 * other: device's acpi-index 679 */ 680 ifctx1 = aml_if(aml_lnot( 681 aml_or(aml_equal(acpi_index, zero), 682 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 683 )); 684 { 685 /* have supported functions */ 686 aml_append(ifctx1, aml_or(caps, one, caps)); 687 /* support for function 7 */ 688 aml_append(ifctx1, 689 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 690 } 691 aml_append(ifctx, ifctx1); 692 693 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 694 aml_append(ifctx, aml_return(ret)); 695 } 696 aml_append(method, ifctx); 697 698 /* handle specific functions requests */ 699 /* 700 * PCI Firmware Specification 3.1 701 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 702 * Operating Systems 703 */ 704 ifctx = aml_if(aml_equal(func, aml_int(7))); 705 { 706 Aml *pkg = aml_package(2); 707 708 aml_append(pkg, zero); 709 /* 710 * optional, if not impl. should return null string 711 */ 712 aml_append(pkg, aml_string("%s", "")); 713 aml_append(ifctx, aml_store(pkg, ret)); 714 715 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 716 /* 717 * update acpi-index to actual value 718 */ 719 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); 720 aml_append(ifctx, aml_return(ret)); 721 } 722 723 aml_append(method, ifctx); 724 return method; 725 } 726 727 /* 728 * build_prt - Define interrupt routing rules 729 * 730 * Returns an array of 128 routes, one for each device, 731 * based on device location. 732 * The main goal is to equally distribute the interrupts 733 * over the 4 existing ACPI links (works only for i440fx). 734 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]". 735 * 736 */ 737 static Aml *build_prt(bool is_pci0_prt) 738 { 739 const int nroutes = 128; 740 Aml *rt_pkg, *method; 741 int pin; 742 743 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 744 rt_pkg = aml_varpackage(nroutes); 745 746 for (pin = 0; pin < nroutes; pin++) { 747 Aml *pkg = aml_package(4); 748 int slot = pin >> 2; 749 750 aml_append(pkg, aml_int((slot << 16) | 0xFFFF)); 751 aml_append(pkg, aml_int(pin & 3)); 752 /* device 1 is the power-management device, needs SCI */ 753 if (is_pci0_prt && pin == 4) { 754 aml_append(pkg, aml_name("%s", "LNKS")); 755 } else { 756 static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"}; 757 int hash = (slot + pin) & 3; 758 aml_append(pkg, aml_name("%s", link_name[hash])); 759 } 760 aml_append(pkg, aml_int(0)); 761 aml_append(rt_pkg, pkg); 762 } 763 764 aml_append(method, aml_return(rt_pkg)); 765 766 return method; 767 } 768 769 static void build_hpet_aml(Aml *table) 770 { 771 Aml *crs; 772 Aml *field; 773 Aml *method; 774 Aml *if_ctx; 775 Aml *scope = aml_scope("_SB"); 776 Aml *dev = aml_device("HPET"); 777 Aml *zero = aml_int(0); 778 Aml *id = aml_local(0); 779 Aml *period = aml_local(1); 780 781 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 782 aml_append(dev, aml_name_decl("_UID", zero)); 783 784 aml_append(dev, 785 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 786 HPET_LEN)); 787 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 788 aml_append(field, aml_named_field("VEND", 32)); 789 aml_append(field, aml_named_field("PRD", 32)); 790 aml_append(dev, field); 791 792 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 793 aml_append(method, aml_store(aml_name("VEND"), id)); 794 aml_append(method, aml_store(aml_name("PRD"), period)); 795 aml_append(method, aml_shiftright(id, aml_int(16), id)); 796 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 797 aml_equal(id, aml_int(0xffff)))); 798 { 799 aml_append(if_ctx, aml_return(zero)); 800 } 801 aml_append(method, if_ctx); 802 803 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 804 aml_lgreater(period, aml_int(100000000)))); 805 { 806 aml_append(if_ctx, aml_return(zero)); 807 } 808 aml_append(method, if_ctx); 809 810 aml_append(method, aml_return(aml_int(0x0F))); 811 aml_append(dev, method); 812 813 crs = aml_resource_template(); 814 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 815 aml_append(dev, aml_name_decl("_CRS", crs)); 816 817 aml_append(scope, dev); 818 aml_append(table, scope); 819 } 820 821 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 822 { 823 Aml *dev; 824 Aml *method; 825 Aml *crs; 826 827 dev = aml_device("VMBS"); 828 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 829 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 830 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 831 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 832 833 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 834 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 835 aml_name("STA"))); 836 aml_append(dev, method); 837 838 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 839 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 840 aml_name("STA"))); 841 aml_append(dev, method); 842 843 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 844 aml_append(method, aml_return(aml_name("STA"))); 845 aml_append(dev, method); 846 847 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 848 849 crs = aml_resource_template(); 850 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 851 aml_append(dev, aml_name_decl("_CRS", crs)); 852 853 return dev; 854 } 855 856 static void build_dbg_aml(Aml *table) 857 { 858 Aml *field; 859 Aml *method; 860 Aml *while_ctx; 861 Aml *scope = aml_scope("\\"); 862 Aml *buf = aml_local(0); 863 Aml *len = aml_local(1); 864 Aml *idx = aml_local(2); 865 866 aml_append(scope, 867 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 868 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 869 aml_append(field, aml_named_field("DBGB", 8)); 870 aml_append(scope, field); 871 872 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 873 874 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 875 aml_append(method, aml_to_buffer(buf, buf)); 876 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 877 aml_append(method, aml_store(aml_int(0), idx)); 878 879 while_ctx = aml_while(aml_lless(idx, len)); 880 aml_append(while_ctx, 881 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 882 aml_append(while_ctx, aml_increment(idx)); 883 aml_append(method, while_ctx); 884 885 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 886 aml_append(scope, method); 887 888 aml_append(table, scope); 889 } 890 891 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 892 { 893 Aml *dev; 894 Aml *crs; 895 Aml *method; 896 uint32_t irqs[] = {5, 10, 11}; 897 898 dev = aml_device("%s", name); 899 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 900 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 901 902 crs = aml_resource_template(); 903 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 904 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 905 aml_append(dev, aml_name_decl("_PRS", crs)); 906 907 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 908 aml_append(method, aml_return(aml_call1("IQST", reg))); 909 aml_append(dev, method); 910 911 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 912 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 913 aml_append(dev, method); 914 915 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 916 aml_append(method, aml_return(aml_call1("IQCR", reg))); 917 aml_append(dev, method); 918 919 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 920 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 921 aml_append(method, aml_store(aml_name("PRRI"), reg)); 922 aml_append(dev, method); 923 924 return dev; 925 } 926 927 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 928 { 929 Aml *dev; 930 Aml *crs; 931 Aml *method; 932 uint32_t irqs; 933 934 dev = aml_device("%s", name); 935 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 936 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 937 938 crs = aml_resource_template(); 939 irqs = gsi; 940 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 941 AML_SHARED, &irqs, 1)); 942 aml_append(dev, aml_name_decl("_PRS", crs)); 943 944 aml_append(dev, aml_name_decl("_CRS", crs)); 945 946 /* 947 * _DIS can be no-op because the interrupt cannot be disabled. 948 */ 949 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 950 aml_append(dev, method); 951 952 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 953 aml_append(dev, method); 954 955 return dev; 956 } 957 958 /* _CRS method - get current settings */ 959 static Aml *build_iqcr_method(bool is_piix4) 960 { 961 Aml *if_ctx; 962 uint32_t irqs; 963 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 964 Aml *crs = aml_resource_template(); 965 966 irqs = 0; 967 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 968 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 969 aml_append(method, aml_name_decl("PRR0", crs)); 970 971 aml_append(method, 972 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 973 974 if (is_piix4) { 975 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 976 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 977 aml_append(method, if_ctx); 978 } else { 979 aml_append(method, 980 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 981 aml_name("PRRI"))); 982 } 983 984 aml_append(method, aml_return(aml_name("PRR0"))); 985 return method; 986 } 987 988 /* _STA method - get status */ 989 static Aml *build_irq_status_method(void) 990 { 991 Aml *if_ctx; 992 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 993 994 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 995 aml_append(if_ctx, aml_return(aml_int(0x09))); 996 aml_append(method, if_ctx); 997 aml_append(method, aml_return(aml_int(0x0B))); 998 return method; 999 } 1000 1001 static void build_piix4_pci0_int(Aml *table) 1002 { 1003 Aml *dev; 1004 Aml *crs; 1005 Aml *method; 1006 uint32_t irqs; 1007 Aml *sb_scope = aml_scope("_SB"); 1008 Aml *pci0_scope = aml_scope("PCI0"); 1009 1010 aml_append(pci0_scope, build_prt(true)); 1011 aml_append(sb_scope, pci0_scope); 1012 1013 aml_append(sb_scope, build_irq_status_method()); 1014 aml_append(sb_scope, build_iqcr_method(true)); 1015 1016 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1017 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1018 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1019 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1020 1021 dev = aml_device("LNKS"); 1022 { 1023 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1024 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1025 1026 crs = aml_resource_template(); 1027 irqs = 9; 1028 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1029 AML_ACTIVE_HIGH, AML_SHARED, 1030 &irqs, 1)); 1031 aml_append(dev, aml_name_decl("_PRS", crs)); 1032 1033 /* The SCI cannot be disabled and is always attached to GSI 9, 1034 * so these are no-ops. We only need this link to override the 1035 * polarity to active high and match the content of the MADT. 1036 */ 1037 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1038 aml_append(method, aml_return(aml_int(0x0b))); 1039 aml_append(dev, method); 1040 1041 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1042 aml_append(dev, method); 1043 1044 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1045 aml_append(method, aml_return(aml_name("_PRS"))); 1046 aml_append(dev, method); 1047 1048 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1049 aml_append(dev, method); 1050 } 1051 aml_append(sb_scope, dev); 1052 1053 aml_append(table, sb_scope); 1054 } 1055 1056 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1057 { 1058 int i; 1059 int head; 1060 Aml *pkg; 1061 char base = name[3] < 'E' ? 'A' : 'E'; 1062 char *s = g_strdup(name); 1063 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1064 1065 assert(strlen(s) == 4); 1066 1067 head = name[3] - base; 1068 for (i = 0; i < 4; i++) { 1069 if (head + i > 3) { 1070 head = i * -1; 1071 } 1072 s[3] = base + head + i; 1073 pkg = aml_package(4); 1074 aml_append(pkg, a_nr); 1075 aml_append(pkg, aml_int(i)); 1076 aml_append(pkg, aml_name("%s", s)); 1077 aml_append(pkg, aml_int(0)); 1078 aml_append(ctx, pkg); 1079 } 1080 g_free(s); 1081 } 1082 1083 static Aml *build_q35_routing_table(const char *str) 1084 { 1085 int i; 1086 Aml *pkg; 1087 char *name = g_strdup_printf("%s ", str); 1088 1089 pkg = aml_package(128); 1090 for (i = 0; i < 0x18; i++) { 1091 name[3] = 'E' + (i & 0x3); 1092 append_q35_prt_entry(pkg, i, name); 1093 } 1094 1095 name[3] = 'E'; 1096 append_q35_prt_entry(pkg, 0x18, name); 1097 1098 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1099 for (i = 0x0019; i < 0x1e; i++) { 1100 name[3] = 'A'; 1101 append_q35_prt_entry(pkg, i, name); 1102 } 1103 1104 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1105 name[3] = 'E'; 1106 append_q35_prt_entry(pkg, 0x1e, name); 1107 name[3] = 'A'; 1108 append_q35_prt_entry(pkg, 0x1f, name); 1109 1110 g_free(name); 1111 return pkg; 1112 } 1113 1114 static void build_q35_pci0_int(Aml *table) 1115 { 1116 Aml *method; 1117 Aml *sb_scope = aml_scope("_SB"); 1118 Aml *pci0_scope = aml_scope("PCI0"); 1119 1120 /* Zero => PIC mode, One => APIC Mode */ 1121 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1122 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1123 { 1124 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1125 } 1126 aml_append(table, method); 1127 1128 aml_append(pci0_scope, 1129 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1130 aml_append(pci0_scope, 1131 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1132 1133 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1134 { 1135 Aml *if_ctx; 1136 Aml *else_ctx; 1137 1138 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1139 section 6.2.8.1 */ 1140 /* Note: we provide the same info as the PCI routing 1141 table of the Bochs BIOS */ 1142 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1143 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1144 aml_append(method, if_ctx); 1145 else_ctx = aml_else(); 1146 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1147 aml_append(method, else_ctx); 1148 } 1149 aml_append(pci0_scope, method); 1150 aml_append(sb_scope, pci0_scope); 1151 1152 aml_append(sb_scope, build_irq_status_method()); 1153 aml_append(sb_scope, build_iqcr_method(false)); 1154 1155 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1156 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1157 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1158 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1159 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1160 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1161 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1162 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1163 1164 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1165 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1166 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1167 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1168 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1169 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1170 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1171 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1172 1173 aml_append(table, sb_scope); 1174 } 1175 1176 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1177 { 1178 Aml *dev; 1179 Aml *resource_template; 1180 1181 /* DRAM controller */ 1182 dev = aml_device("DRAC"); 1183 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1184 1185 resource_template = aml_resource_template(); 1186 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1187 aml_append(resource_template, 1188 aml_qword_memory(AML_POS_DECODE, 1189 AML_MIN_FIXED, 1190 AML_MAX_FIXED, 1191 AML_NON_CACHEABLE, 1192 AML_READ_WRITE, 1193 0x0000000000000000, 1194 mcfg->base, 1195 mcfg->base + mcfg->size - 1, 1196 0x0000000000000000, 1197 mcfg->size)); 1198 } else { 1199 aml_append(resource_template, 1200 aml_dword_memory(AML_POS_DECODE, 1201 AML_MIN_FIXED, 1202 AML_MAX_FIXED, 1203 AML_NON_CACHEABLE, 1204 AML_READ_WRITE, 1205 0x0000000000000000, 1206 mcfg->base, 1207 mcfg->base + mcfg->size - 1, 1208 0x0000000000000000, 1209 mcfg->size)); 1210 } 1211 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1212 1213 return dev; 1214 } 1215 1216 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1217 { 1218 Aml *scope; 1219 Aml *field; 1220 Aml *method; 1221 1222 scope = aml_scope("_SB.PCI0"); 1223 1224 aml_append(scope, 1225 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1226 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1227 aml_append(field, aml_named_field("PCIU", 32)); 1228 aml_append(field, aml_named_field("PCID", 32)); 1229 aml_append(scope, field); 1230 1231 aml_append(scope, 1232 aml_operation_region("SEJ", AML_SYSTEM_IO, 1233 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1234 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1235 aml_append(field, aml_named_field("B0EJ", 32)); 1236 aml_append(scope, field); 1237 1238 aml_append(scope, 1239 aml_operation_region("BNMR", AML_SYSTEM_IO, 1240 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1241 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1242 aml_append(field, aml_named_field("BNUM", 32)); 1243 aml_append(field, aml_named_field("PIDX", 32)); 1244 aml_append(scope, field); 1245 1246 aml_append(scope, aml_mutex("BLCK", 0)); 1247 1248 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1249 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1250 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1251 aml_append(method, 1252 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1253 aml_append(method, aml_release(aml_name("BLCK"))); 1254 aml_append(method, aml_return(aml_int(0))); 1255 aml_append(scope, method); 1256 1257 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1258 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1259 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1260 aml_append(method, 1261 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1262 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1263 aml_append(method, aml_release(aml_name("BLCK"))); 1264 aml_append(method, aml_return(aml_local(0))); 1265 aml_append(scope, method); 1266 1267 aml_append(scope, aml_pci_pdsm()); 1268 1269 aml_append(table, scope); 1270 } 1271 1272 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1273 { 1274 Aml *if_ctx; 1275 Aml *if_ctx2; 1276 Aml *else_ctx; 1277 Aml *method; 1278 Aml *a_cwd1 = aml_name("CDW1"); 1279 Aml *a_ctrl = aml_local(0); 1280 1281 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1282 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1283 1284 if_ctx = aml_if(aml_equal( 1285 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1286 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1287 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1288 1289 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1290 1291 /* 1292 * Always allow native PME, AER (no dependencies) 1293 * Allow SHPC (PCI bridges can have SHPC controller) 1294 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1295 */ 1296 aml_append(if_ctx, aml_and(a_ctrl, 1297 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1298 1299 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1300 /* Unknown revision */ 1301 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1302 aml_append(if_ctx, if_ctx2); 1303 1304 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1305 /* Capabilities bits were masked */ 1306 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1307 aml_append(if_ctx, if_ctx2); 1308 1309 /* Update DWORD3 in the buffer */ 1310 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1311 aml_append(method, if_ctx); 1312 1313 else_ctx = aml_else(); 1314 /* Unrecognized UUID */ 1315 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1316 aml_append(method, else_ctx); 1317 1318 aml_append(method, aml_return(aml_arg(3))); 1319 return method; 1320 } 1321 1322 static void build_acpi0017(Aml *table) 1323 { 1324 Aml *dev, *scope, *method; 1325 1326 scope = aml_scope("_SB"); 1327 dev = aml_device("CXLM"); 1328 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1329 1330 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1331 aml_append(method, aml_return(aml_int(0x0B))); 1332 aml_append(dev, method); 1333 build_cxl_dsm_method(dev); 1334 1335 aml_append(scope, dev); 1336 aml_append(table, scope); 1337 } 1338 1339 static void 1340 build_dsdt(GArray *table_data, BIOSLinker *linker, 1341 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1342 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1343 { 1344 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE, 1345 NULL); 1346 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL); 1347 CrsRangeEntry *entry; 1348 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1349 CrsRangeSet crs_range_set; 1350 PCMachineState *pcms = PC_MACHINE(machine); 1351 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1352 X86MachineState *x86ms = X86_MACHINE(machine); 1353 AcpiMcfgInfo mcfg; 1354 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1355 uint32_t nr_mem = machine->ram_slots; 1356 int root_bus_limit = 0xFF; 1357 PCIBus *bus = NULL; 1358 #ifdef CONFIG_TPM 1359 TPMIf *tpm = tpm_find(); 1360 #endif 1361 bool cxl_present = false; 1362 int i; 1363 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1364 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1365 .oem_table_id = x86ms->oem_table_id }; 1366 1367 assert(!!i440fx != !!q35); 1368 1369 acpi_table_begin(&table, table_data); 1370 dsdt = init_aml_allocator(); 1371 1372 build_dbg_aml(dsdt); 1373 if (i440fx) { 1374 sb_scope = aml_scope("_SB"); 1375 dev = aml_device("PCI0"); 1376 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1377 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1378 aml_append(dev, aml_pci_edsm()); 1379 aml_append(sb_scope, dev); 1380 aml_append(dsdt, sb_scope); 1381 1382 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1383 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1384 } 1385 build_piix4_pci0_int(dsdt); 1386 } else if (q35) { 1387 sb_scope = aml_scope("_SB"); 1388 dev = aml_device("PCI0"); 1389 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1390 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1391 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1392 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1393 aml_append(dev, aml_pci_edsm()); 1394 aml_append(sb_scope, dev); 1395 if (mcfg_valid) { 1396 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1397 } 1398 1399 if (pm->smi_on_cpuhp) { 1400 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1401 dev = aml_device("PCI0.SMI0"); 1402 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1403 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1404 crs = aml_resource_template(); 1405 aml_append(crs, 1406 aml_io( 1407 AML_DECODE16, 1408 pm->fadt.smi_cmd, 1409 pm->fadt.smi_cmd, 1410 1, 1411 2) 1412 ); 1413 aml_append(dev, aml_name_decl("_CRS", crs)); 1414 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1415 aml_int(pm->fadt.smi_cmd), 2)); 1416 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1417 AML_WRITE_AS_ZEROS); 1418 aml_append(field, aml_named_field("SMIC", 8)); 1419 aml_append(field, aml_reserved_field(8)); 1420 aml_append(dev, field); 1421 aml_append(sb_scope, dev); 1422 } 1423 1424 aml_append(dsdt, sb_scope); 1425 1426 if (pm->pcihp_bridge_en) { 1427 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1428 } 1429 build_q35_pci0_int(dsdt); 1430 } 1431 1432 if (misc->has_hpet) { 1433 build_hpet_aml(dsdt); 1434 } 1435 1436 if (vmbus_bridge) { 1437 sb_scope = aml_scope("_SB"); 1438 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1439 aml_append(dsdt, sb_scope); 1440 } 1441 1442 scope = aml_scope("_GPE"); 1443 { 1444 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1445 if (machine->nvdimms_state->is_enabled) { 1446 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1447 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1448 aml_int(0x80))); 1449 aml_append(scope, method); 1450 } 1451 } 1452 aml_append(dsdt, scope); 1453 1454 if (pcmc->legacy_cpu_hotplug) { 1455 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1456 } else { 1457 CPUHotplugFeatures opts = { 1458 .acpi_1_compatible = true, .has_legacy_cphp = true, 1459 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1460 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1461 }; 1462 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, 1463 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", 1464 AML_SYSTEM_IO); 1465 } 1466 1467 if (pcms->memhp_io_base && nr_mem) { 1468 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1469 "\\_GPE._E03", AML_SYSTEM_IO, 1470 pcms->memhp_io_base); 1471 } 1472 1473 crs_range_set_init(&crs_range_set); 1474 bus = PC_MACHINE(machine)->pcibus; 1475 if (bus) { 1476 QLIST_FOREACH(bus, &bus->child, sibling) { 1477 uint8_t bus_num = pci_bus_num(bus); 1478 uint8_t numa_node = pci_bus_numa_node(bus); 1479 1480 /* look only for expander root buses */ 1481 if (!pci_bus_is_root(bus)) { 1482 continue; 1483 } 1484 1485 if (bus_num < root_bus_limit) { 1486 root_bus_limit = bus_num - 1; 1487 } 1488 1489 scope = aml_scope("\\_SB"); 1490 1491 if (pci_bus_is_cxl(bus)) { 1492 dev = aml_device("CL%.02X", bus_num); 1493 } else { 1494 dev = aml_device("PC%.02X", bus_num); 1495 } 1496 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1497 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1498 if (pci_bus_is_cxl(bus)) { 1499 struct Aml *aml_pkg = aml_package(2); 1500 1501 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1502 aml_append(aml_pkg, aml_eisaid("PNP0A08")); 1503 aml_append(aml_pkg, aml_eisaid("PNP0A03")); 1504 aml_append(dev, aml_name_decl("_CID", aml_pkg)); 1505 build_cxl_osc_method(dev); 1506 } else if (pci_bus_is_express(bus)) { 1507 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1508 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1509 1510 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1511 aml_append(dev, build_q35_osc_method(true)); 1512 } else { 1513 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1514 } 1515 1516 if (numa_node != NUMA_NODE_UNASSIGNED) { 1517 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1518 } 1519 1520 aml_append(dev, build_prt(false)); 1521 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1522 0, 0, 0, 0); 1523 aml_append(dev, aml_name_decl("_CRS", crs)); 1524 aml_append(scope, dev); 1525 aml_append(dsdt, scope); 1526 1527 /* Handle the ranges for the PXB expanders */ 1528 if (pci_bus_is_cxl(bus)) { 1529 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1530 uint64_t base = mr->addr; 1531 1532 cxl_present = true; 1533 crs_range_insert(crs_range_set.mem_ranges, base, 1534 base + memory_region_size(mr) - 1); 1535 } 1536 } 1537 } 1538 1539 if (cxl_present) { 1540 build_acpi0017(dsdt); 1541 } 1542 1543 /* 1544 * At this point crs_range_set has all the ranges used by pci 1545 * busses *other* than PCI0. These ranges will be excluded from 1546 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1547 * too. 1548 */ 1549 if (mcfg_valid) { 1550 crs_range_insert(crs_range_set.mem_ranges, 1551 mcfg.base, mcfg.base + mcfg.size - 1); 1552 } 1553 1554 scope = aml_scope("\\_SB.PCI0"); 1555 /* build PCI0._CRS */ 1556 crs = aml_resource_template(); 1557 aml_append(crs, 1558 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1559 0x0000, 0x0, root_bus_limit, 1560 0x0000, root_bus_limit + 1)); 1561 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1562 1563 aml_append(crs, 1564 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1565 AML_POS_DECODE, AML_ENTIRE_RANGE, 1566 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1567 1568 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1569 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1570 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1571 aml_append(crs, 1572 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1573 AML_POS_DECODE, AML_ENTIRE_RANGE, 1574 0x0000, entry->base, entry->limit, 1575 0x0000, entry->limit - entry->base + 1)); 1576 } 1577 1578 aml_append(crs, 1579 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1580 AML_CACHEABLE, AML_READ_WRITE, 1581 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1582 1583 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1584 range_lob(pci_hole), 1585 range_upb(pci_hole)); 1586 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1587 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1588 aml_append(crs, 1589 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1590 AML_NON_CACHEABLE, AML_READ_WRITE, 1591 0, entry->base, entry->limit, 1592 0, entry->limit - entry->base + 1)); 1593 } 1594 1595 if (!range_is_empty(pci_hole64)) { 1596 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1597 range_lob(pci_hole64), 1598 range_upb(pci_hole64)); 1599 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1600 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1601 aml_append(crs, 1602 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1603 AML_MAX_FIXED, 1604 AML_CACHEABLE, AML_READ_WRITE, 1605 0, entry->base, entry->limit, 1606 0, entry->limit - entry->base + 1)); 1607 } 1608 } 1609 1610 #ifdef CONFIG_TPM 1611 if (TPM_IS_TIS_ISA(tpm_find())) { 1612 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1613 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1614 } 1615 #endif 1616 aml_append(scope, aml_name_decl("_CRS", crs)); 1617 1618 /* reserve GPE0 block resources */ 1619 dev = aml_device("GPE0"); 1620 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1621 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1622 /* device present, functioning, decoding, not shown in UI */ 1623 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1624 crs = aml_resource_template(); 1625 aml_append(crs, 1626 aml_io( 1627 AML_DECODE16, 1628 pm->fadt.gpe0_blk.address, 1629 pm->fadt.gpe0_blk.address, 1630 1, 1631 pm->fadt.gpe0_blk.bit_width / 8) 1632 ); 1633 aml_append(dev, aml_name_decl("_CRS", crs)); 1634 aml_append(scope, dev); 1635 1636 crs_range_set_free(&crs_range_set); 1637 1638 /* reserve PCIHP resources */ 1639 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1640 dev = aml_device("PHPR"); 1641 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1642 aml_append(dev, 1643 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1644 /* device present, functioning, decoding, not shown in UI */ 1645 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1646 crs = aml_resource_template(); 1647 aml_append(crs, 1648 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1649 pm->pcihp_io_len) 1650 ); 1651 aml_append(dev, aml_name_decl("_CRS", crs)); 1652 aml_append(scope, dev); 1653 } 1654 aml_append(dsdt, scope); 1655 1656 /* create S3_ / S4_ / S5_ packages if necessary */ 1657 scope = aml_scope("\\"); 1658 if (!pm->s3_disabled) { 1659 pkg = aml_package(4); 1660 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1661 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1662 aml_append(pkg, aml_int(0)); /* reserved */ 1663 aml_append(pkg, aml_int(0)); /* reserved */ 1664 aml_append(scope, aml_name_decl("_S3", pkg)); 1665 } 1666 1667 if (!pm->s4_disabled) { 1668 pkg = aml_package(4); 1669 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1670 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1671 aml_append(pkg, aml_int(pm->s4_val)); 1672 aml_append(pkg, aml_int(0)); /* reserved */ 1673 aml_append(pkg, aml_int(0)); /* reserved */ 1674 aml_append(scope, aml_name_decl("_S4", pkg)); 1675 } 1676 1677 pkg = aml_package(4); 1678 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1679 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1680 aml_append(pkg, aml_int(0)); /* reserved */ 1681 aml_append(pkg, aml_int(0)); /* reserved */ 1682 aml_append(scope, aml_name_decl("_S5", pkg)); 1683 aml_append(dsdt, scope); 1684 1685 /* create fw_cfg node, unconditionally */ 1686 { 1687 scope = aml_scope("\\_SB.PCI0"); 1688 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1689 aml_append(dsdt, scope); 1690 } 1691 1692 sb_scope = aml_scope("\\_SB"); 1693 { 1694 Object *pci_host = acpi_get_i386_pci_host(); 1695 1696 if (pci_host) { 1697 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus; 1698 Aml *ascope = aml_scope("PCI0"); 1699 /* Scan all PCI buses. Generate tables to support hotplug. */ 1700 build_append_pci_bus_devices(ascope, pbus); 1701 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) { 1702 build_append_pcihp_slots(ascope, pbus); 1703 } 1704 aml_append(sb_scope, ascope); 1705 } 1706 } 1707 1708 #ifdef CONFIG_TPM 1709 if (TPM_IS_CRB(tpm)) { 1710 dev = aml_device("TPM"); 1711 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1712 aml_append(dev, aml_name_decl("_STR", 1713 aml_string("TPM 2.0 Device"))); 1714 crs = aml_resource_template(); 1715 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1716 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1717 aml_append(dev, aml_name_decl("_CRS", crs)); 1718 1719 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1720 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1721 1722 tpm_build_ppi_acpi(tpm, dev); 1723 1724 aml_append(sb_scope, dev); 1725 } 1726 #endif 1727 1728 if (pcms->sgx_epc.size != 0) { 1729 uint64_t epc_base = pcms->sgx_epc.base; 1730 uint64_t epc_size = pcms->sgx_epc.size; 1731 1732 dev = aml_device("EPC"); 1733 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1734 aml_append(dev, aml_name_decl("_STR", 1735 aml_unicode("Enclave Page Cache 1.0"))); 1736 crs = aml_resource_template(); 1737 aml_append(crs, 1738 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1739 AML_MAX_FIXED, AML_NON_CACHEABLE, 1740 AML_READ_WRITE, 0, epc_base, 1741 epc_base + epc_size - 1, 0, epc_size)); 1742 aml_append(dev, aml_name_decl("_CRS", crs)); 1743 1744 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1745 aml_append(method, aml_return(aml_int(0x0f))); 1746 aml_append(dev, method); 1747 1748 aml_append(sb_scope, dev); 1749 } 1750 aml_append(dsdt, sb_scope); 1751 1752 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1753 bool has_pcnt; 1754 1755 Object *pci_host = acpi_get_i386_pci_host(); 1756 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus; 1757 1758 scope = aml_scope("\\_SB.PCI0"); 1759 has_pcnt = build_append_notfication_callback(scope, b); 1760 if (has_pcnt) { 1761 aml_append(dsdt, scope); 1762 } 1763 1764 scope = aml_scope("_GPE"); 1765 { 1766 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1767 if (has_pcnt) { 1768 aml_append(method, 1769 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1770 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1771 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1772 } 1773 aml_append(scope, method); 1774 } 1775 aml_append(dsdt, scope); 1776 } 1777 1778 /* copy AML table into ACPI tables blob and patch header there */ 1779 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1780 acpi_table_end(linker, &table); 1781 free_aml_allocator(); 1782 } 1783 1784 /* 1785 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1786 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1787 */ 1788 static void 1789 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1790 const char *oem_table_id) 1791 { 1792 AcpiTable table = { .sig = "HPET", .rev = 1, 1793 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1794 1795 acpi_table_begin(&table, table_data); 1796 /* Note timer_block_id value must be kept in sync with value advertised by 1797 * emulated hpet 1798 */ 1799 /* Event Timer Block ID */ 1800 build_append_int_noprefix(table_data, 0x8086a201, 4); 1801 /* BASE_ADDRESS */ 1802 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1803 /* HPET Number */ 1804 build_append_int_noprefix(table_data, 0, 1); 1805 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1806 build_append_int_noprefix(table_data, 0, 2); 1807 /* Page Protection And OEM Attribute */ 1808 build_append_int_noprefix(table_data, 0, 1); 1809 acpi_table_end(linker, &table); 1810 } 1811 1812 #ifdef CONFIG_TPM 1813 /* 1814 * TCPA Description Table 1815 * 1816 * Following Level 00, Rev 00.37 of specs: 1817 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1818 * 7.1.2 ACPI Table Layout 1819 */ 1820 static void 1821 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1822 const char *oem_id, const char *oem_table_id) 1823 { 1824 unsigned log_addr_offset; 1825 AcpiTable table = { .sig = "TCPA", .rev = 2, 1826 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1827 1828 acpi_table_begin(&table, table_data); 1829 /* Platform Class */ 1830 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1831 /* Log Area Minimum Length (LAML) */ 1832 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1833 /* Log Area Start Address (LASA) */ 1834 log_addr_offset = table_data->len; 1835 build_append_int_noprefix(table_data, 0, 8); 1836 1837 /* allocate/reserve space for TPM log area */ 1838 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1839 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1840 false /* high memory */); 1841 /* log area start address to be filled by Guest linker */ 1842 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1843 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1844 1845 acpi_table_end(linker, &table); 1846 } 1847 #endif 1848 1849 #define HOLE_640K_START (640 * KiB) 1850 #define HOLE_640K_END (1 * MiB) 1851 1852 /* 1853 * ACPI spec, Revision 3.0 1854 * 5.2.15 System Resource Affinity Table (SRAT) 1855 */ 1856 static void 1857 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1858 { 1859 int i; 1860 int numa_mem_start, slots; 1861 uint64_t mem_len, mem_base, next_base; 1862 MachineClass *mc = MACHINE_GET_CLASS(machine); 1863 X86MachineState *x86ms = X86_MACHINE(machine); 1864 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1865 int nb_numa_nodes = machine->numa_state->num_nodes; 1866 NodeInfo *numa_info = machine->numa_state->nodes; 1867 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1868 .oem_table_id = x86ms->oem_table_id }; 1869 1870 acpi_table_begin(&table, table_data); 1871 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1872 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1873 1874 for (i = 0; i < apic_ids->len; i++) { 1875 int node_id = apic_ids->cpus[i].props.node_id; 1876 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1877 1878 if (apic_id < 255) { 1879 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1880 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1881 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1882 /* Proximity Domain [7:0] */ 1883 build_append_int_noprefix(table_data, node_id, 1); 1884 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1885 /* Flags, Table 5-36 */ 1886 build_append_int_noprefix(table_data, 1, 4); 1887 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1888 /* Proximity Domain [31:8] */ 1889 build_append_int_noprefix(table_data, 0, 3); 1890 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1891 } else { 1892 /* 1893 * ACPI spec, Revision 4.0 1894 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1895 */ 1896 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1897 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1898 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1899 /* Proximity Domain */ 1900 build_append_int_noprefix(table_data, node_id, 4); 1901 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1902 /* Flags, Table 5-39 */ 1903 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1904 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1905 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1906 } 1907 } 1908 1909 /* the memory map is a bit tricky, it contains at least one hole 1910 * from 640k-1M and possibly another one from 3.5G-4G. 1911 */ 1912 next_base = 0; 1913 numa_mem_start = table_data->len; 1914 1915 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1916 mem_base = next_base; 1917 mem_len = numa_info[i - 1].node_mem; 1918 next_base = mem_base + mem_len; 1919 1920 /* Cut out the 640K hole */ 1921 if (mem_base <= HOLE_640K_START && 1922 next_base > HOLE_640K_START) { 1923 mem_len -= next_base - HOLE_640K_START; 1924 if (mem_len > 0) { 1925 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1926 MEM_AFFINITY_ENABLED); 1927 } 1928 1929 /* Check for the rare case: 640K < RAM < 1M */ 1930 if (next_base <= HOLE_640K_END) { 1931 next_base = HOLE_640K_END; 1932 continue; 1933 } 1934 mem_base = HOLE_640K_END; 1935 mem_len = next_base - HOLE_640K_END; 1936 } 1937 1938 /* Cut out the ACPI_PCI hole */ 1939 if (mem_base <= x86ms->below_4g_mem_size && 1940 next_base > x86ms->below_4g_mem_size) { 1941 mem_len -= next_base - x86ms->below_4g_mem_size; 1942 if (mem_len > 0) { 1943 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1944 MEM_AFFINITY_ENABLED); 1945 } 1946 mem_base = x86ms->above_4g_mem_start; 1947 mem_len = next_base - x86ms->below_4g_mem_size; 1948 next_base = mem_base + mem_len; 1949 } 1950 1951 if (mem_len > 0) { 1952 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1953 MEM_AFFINITY_ENABLED); 1954 } 1955 } 1956 1957 if (machine->nvdimms_state->is_enabled) { 1958 nvdimm_build_srat(table_data); 1959 } 1960 1961 sgx_epc_build_srat(table_data); 1962 1963 /* 1964 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1965 * without these entries. But I recall there were issues the last time I 1966 * tried to remove it with some ancient guest OS, however I can't remember 1967 * what that was so keep this around for now 1968 */ 1969 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1970 for (; slots < nb_numa_nodes + 2; slots++) { 1971 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1972 } 1973 1974 build_srat_generic_pci_initiator(table_data); 1975 1976 /* 1977 * Entry is required for Windows to enable memory hotplug in OS 1978 * and for Linux to enable SWIOTLB when booted with less than 1979 * 4G of RAM. Windows works better if the entry sets proximity 1980 * to the highest NUMA node in the machine. 1981 * Memory devices may override proximity set by this entry, 1982 * providing _PXM method if necessary. 1983 */ 1984 if (machine->device_memory) { 1985 build_srat_memory(table_data, machine->device_memory->base, 1986 memory_region_size(&machine->device_memory->mr), 1987 nb_numa_nodes - 1, 1988 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 1989 } 1990 1991 acpi_table_end(linker, &table); 1992 } 1993 1994 /* 1995 * Insert DMAR scope for PCI bridges and endpoint devices 1996 */ 1997 static void 1998 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 1999 { 2000 const size_t device_scope_size = 6 /* device scope structure */ + 2001 2 /* 1 path entry */; 2002 GArray *scope_blob = opaque; 2003 2004 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2005 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2006 build_append_int_noprefix(scope_blob, 0x02, 1); 2007 } else { 2008 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2009 build_append_int_noprefix(scope_blob, 0x01, 1); 2010 } 2011 2012 /* length */ 2013 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2014 /* reserved */ 2015 build_append_int_noprefix(scope_blob, 0, 2); 2016 /* enumeration_id */ 2017 build_append_int_noprefix(scope_blob, 0, 1); 2018 /* bus */ 2019 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2020 /* device */ 2021 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2022 /* function */ 2023 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2024 } 2025 2026 /* For a given PCI host bridge, walk and insert DMAR scope */ 2027 static int 2028 dmar_host_bridges(Object *obj, void *opaque) 2029 { 2030 GArray *scope_blob = opaque; 2031 2032 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2033 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2034 2035 if (bus && !pci_bus_bypass_iommu(bus)) { 2036 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2037 } 2038 } 2039 2040 return 0; 2041 } 2042 2043 /* 2044 * Intel ® Virtualization Technology for Directed I/O 2045 * Architecture Specification. Revision 3.3 2046 * 8.1 DMA Remapping Reporting Structure 2047 */ 2048 static void 2049 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2050 const char *oem_table_id) 2051 { 2052 uint8_t dmar_flags = 0; 2053 uint8_t rsvd10[10] = {}; 2054 /* Root complex IOAPIC uses one path only */ 2055 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2056 2 /* 1 path entry */; 2057 X86IOMMUState *iommu = x86_iommu_get_default(); 2058 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2059 GArray *scope_blob = g_array_new(false, true, 1); 2060 2061 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2062 .oem_table_id = oem_table_id }; 2063 2064 /* 2065 * A PCI bus walk, for each PCI host bridge. 2066 * Insert scope for each PCI bridge and endpoint device which 2067 * is attached to a bus with iommu enabled. 2068 */ 2069 object_child_foreach_recursive(object_get_root(), 2070 dmar_host_bridges, scope_blob); 2071 2072 assert(iommu); 2073 if (x86_iommu_ir_supported(iommu)) { 2074 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2075 } 2076 2077 acpi_table_begin(&table, table_data); 2078 /* Host Address Width */ 2079 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2080 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2081 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2082 2083 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2084 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2085 /* Length */ 2086 build_append_int_noprefix(table_data, 2087 16 + ioapic_scope_size + scope_blob->len, 2); 2088 /* Flags */ 2089 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2090 1); 2091 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2092 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2093 /* Register Base Address */ 2094 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2095 2096 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2097 * 8.3.1 (version Oct. 2014 or later). */ 2098 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2099 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2100 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2101 /* Enumeration ID */ 2102 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2103 /* Start Bus Number */ 2104 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2105 /* Path, {Device, Function} pair */ 2106 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2107 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2108 2109 /* Add scope found above */ 2110 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2111 g_array_free(scope_blob, true); 2112 2113 if (iommu->dt_supported) { 2114 /* 8.5 Root Port ATS Capability Reporting Structure */ 2115 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2116 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2117 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2118 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2119 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2120 } 2121 2122 acpi_table_end(linker, &table); 2123 } 2124 2125 /* 2126 * Windows ACPI Emulated Devices Table 2127 * (Version 1.0 - April 6, 2009) 2128 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2129 * 2130 * Helpful to speedup Windows guests and ignored by others. 2131 */ 2132 static void 2133 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2134 const char *oem_table_id) 2135 { 2136 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2137 .oem_table_id = oem_table_id }; 2138 2139 acpi_table_begin(&table, table_data); 2140 /* 2141 * Set "ACPI PM timer good" flag. 2142 * 2143 * Tells Windows guests that our ACPI PM timer is reliable in the 2144 * sense that guest can read it only once to obtain a reliable value. 2145 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2146 */ 2147 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2148 acpi_table_end(linker, &table); 2149 } 2150 2151 /* 2152 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2153 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2154 */ 2155 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2156 2157 /* 2158 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2159 * necessary for the PCI topology. 2160 */ 2161 static void 2162 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2163 { 2164 GArray *table_data = opaque; 2165 uint32_t entry; 2166 2167 /* "Select" IVHD entry, type 0x2 */ 2168 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2169 build_append_int_noprefix(table_data, entry, 4); 2170 2171 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2172 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2173 uint8_t sec = pci_bus_num(sec_bus); 2174 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2175 2176 if (pci_bus_is_express(sec_bus)) { 2177 /* 2178 * Walk the bus if there are subordinates, otherwise use a range 2179 * to cover an entire leaf bus. We could potentially also use a 2180 * range for traversed buses, but we'd need to take care not to 2181 * create both Select and Range entries covering the same device. 2182 * This is easier and potentially more compact. 2183 * 2184 * An example bare metal system seems to use Select entries for 2185 * root ports without a slot (ie. built-ins) and Range entries 2186 * when there is a slot. The same system also only hard-codes 2187 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2188 * making no effort to support nested bridges. We attempt to 2189 * be more thorough here. 2190 */ 2191 if (sec == sub) { /* leaf bus */ 2192 /* "Start of Range" IVHD entry, type 0x3 */ 2193 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2194 build_append_int_noprefix(table_data, entry, 4); 2195 /* "End of Range" IVHD entry, type 0x4 */ 2196 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2197 build_append_int_noprefix(table_data, entry, 4); 2198 } else { 2199 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2200 } 2201 } else { 2202 /* 2203 * If the secondary bus is conventional, then we need to create an 2204 * Alias range for everything downstream. The range covers the 2205 * first devfn on the secondary bus to the last devfn on the 2206 * subordinate bus. The alias target depends on legacy versus 2207 * express bridges, just as in pci_device_iommu_address_space(). 2208 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2209 */ 2210 uint16_t dev_id_a, dev_id_b; 2211 2212 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2213 2214 if (pci_is_express(dev) && 2215 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2216 dev_id_b = dev_id_a; 2217 } else { 2218 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2219 } 2220 2221 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2222 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2223 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2224 2225 /* "End of Range" IVHD entry, type 0x4 */ 2226 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2227 build_append_int_noprefix(table_data, entry, 4); 2228 } 2229 } 2230 } 2231 2232 /* For all PCI host bridges, walk and insert IVHD entries */ 2233 static int 2234 ivrs_host_bridges(Object *obj, void *opaque) 2235 { 2236 GArray *ivhd_blob = opaque; 2237 2238 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2239 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2240 2241 if (bus && !pci_bus_bypass_iommu(bus)) { 2242 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2243 } 2244 } 2245 2246 return 0; 2247 } 2248 2249 static void 2250 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2251 const char *oem_table_id) 2252 { 2253 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2254 GArray *ivhd_blob = g_array_new(false, true, 1); 2255 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2256 .oem_table_id = oem_table_id }; 2257 uint64_t feature_report; 2258 2259 acpi_table_begin(&table, table_data); 2260 /* IVinfo - IO virtualization information common to all 2261 * IOMMU units in a system 2262 */ 2263 build_append_int_noprefix(table_data, 2264 (1UL << 0) | /* EFRSup */ 2265 (40UL << 8), /* PASize */ 2266 4); 2267 /* reserved */ 2268 build_append_int_noprefix(table_data, 0, 8); 2269 2270 /* 2271 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2272 * complete set of IVHD entries. Do this into a separate blob so that we 2273 * can calculate the total IVRS table length here and then append the new 2274 * blob further below. Fall back to an entry covering all devices, which 2275 * is sufficient when no aliases are present. 2276 */ 2277 object_child_foreach_recursive(object_get_root(), 2278 ivrs_host_bridges, ivhd_blob); 2279 2280 if (!ivhd_blob->len) { 2281 /* 2282 * Type 1 device entry reporting all devices 2283 * These are 4-byte device entries currently reporting the range of 2284 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2285 */ 2286 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2287 } 2288 2289 /* 2290 * When interrupt remapping is supported, we add a special IVHD device 2291 * for type IO-APIC 2292 * Refer to spec - Table 95: IVHD device entry type codes 2293 * 2294 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2295 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2296 */ 2297 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2298 build_append_int_noprefix(ivhd_blob, 2299 (0x1ull << 56) | /* type IOAPIC */ 2300 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2301 0x48, /* special device */ 2302 8); 2303 } 2304 2305 /* IVHD definition - type 10h */ 2306 build_append_int_noprefix(table_data, 0x10, 1); 2307 /* virtualization flags */ 2308 build_append_int_noprefix(table_data, 2309 (1UL << 0) | /* HtTunEn */ 2310 (1UL << 4) | /* iotblSup */ 2311 (1UL << 6) | /* PrefSup */ 2312 (1UL << 7), /* PPRSup */ 2313 1); 2314 2315 /* IVHD length */ 2316 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); 2317 /* DeviceID */ 2318 build_append_int_noprefix(table_data, 2319 object_property_get_int(OBJECT(&s->pci), "addr", 2320 &error_abort), 2); 2321 /* Capability offset */ 2322 build_append_int_noprefix(table_data, s->pci.capab_offset, 2); 2323 /* IOMMU base address */ 2324 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2325 /* PCI Segment Group */ 2326 build_append_int_noprefix(table_data, 0, 2); 2327 /* IOMMU info */ 2328 build_append_int_noprefix(table_data, 0, 2); 2329 /* IOMMU Feature Reporting */ 2330 feature_report = (48UL << 30) | /* HATS */ 2331 (48UL << 28) | /* GATS */ 2332 (1UL << 2) | /* GTSup */ 2333 (1UL << 6); /* GASup */ 2334 if (s->xtsup) { 2335 feature_report |= (1UL << 0); /* XTSup */ 2336 } 2337 build_append_int_noprefix(table_data, feature_report, 4); 2338 2339 /* IVHD entries as found above */ 2340 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2341 2342 /* IVHD definition - type 11h */ 2343 build_append_int_noprefix(table_data, 0x11, 1); 2344 /* virtualization flags */ 2345 build_append_int_noprefix(table_data, 2346 (1UL << 0) | /* HtTunEn */ 2347 (1UL << 4), /* iotblSup */ 2348 1); 2349 2350 /* IVHD length */ 2351 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); 2352 /* DeviceID */ 2353 build_append_int_noprefix(table_data, 2354 object_property_get_int(OBJECT(&s->pci), "addr", 2355 &error_abort), 2); 2356 /* Capability offset */ 2357 build_append_int_noprefix(table_data, s->pci.capab_offset, 2); 2358 /* IOMMU base address */ 2359 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2360 /* PCI Segment Group */ 2361 build_append_int_noprefix(table_data, 0, 2); 2362 /* IOMMU info */ 2363 build_append_int_noprefix(table_data, 0, 2); 2364 /* IOMMU Attributes */ 2365 build_append_int_noprefix(table_data, 0, 4); 2366 /* EFR Register Image */ 2367 build_append_int_noprefix(table_data, 2368 amdvi_extended_feature_register(s), 2369 8); 2370 /* EFR Register Image 2 */ 2371 build_append_int_noprefix(table_data, 0, 8); 2372 2373 /* IVHD entries as found above */ 2374 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2375 2376 g_array_free(ivhd_blob, TRUE); 2377 acpi_table_end(linker, &table); 2378 } 2379 2380 typedef 2381 struct AcpiBuildState { 2382 /* Copy of table in RAM (for patching). */ 2383 MemoryRegion *table_mr; 2384 /* Is table patched? */ 2385 uint8_t patched; 2386 MemoryRegion *rsdp_mr; 2387 MemoryRegion *linker_mr; 2388 } AcpiBuildState; 2389 2390 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2391 { 2392 Object *pci_host; 2393 QObject *o; 2394 2395 pci_host = acpi_get_i386_pci_host(); 2396 if (!pci_host) { 2397 return false; 2398 } 2399 2400 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2401 if (!o) { 2402 return false; 2403 } 2404 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2405 qobject_unref(o); 2406 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2407 return false; 2408 } 2409 2410 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2411 assert(o); 2412 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2413 qobject_unref(o); 2414 return true; 2415 } 2416 2417 static 2418 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2419 { 2420 PCMachineState *pcms = PC_MACHINE(machine); 2421 X86MachineState *x86ms = X86_MACHINE(machine); 2422 DeviceState *iommu = pcms->iommu; 2423 GArray *table_offsets; 2424 unsigned facs, dsdt, rsdt; 2425 AcpiPmInfo pm; 2426 AcpiMiscInfo misc; 2427 AcpiMcfgInfo mcfg; 2428 Range pci_hole = {}, pci_hole64 = {}; 2429 uint8_t *u; 2430 GArray *tables_blob = tables->table_data; 2431 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2432 Object *vmgenid_dev; 2433 char *oem_id; 2434 char *oem_table_id; 2435 2436 acpi_get_pm_info(machine, &pm); 2437 acpi_get_misc_info(&misc); 2438 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2439 acpi_get_slic_oem(&slic_oem); 2440 2441 if (slic_oem.id) { 2442 oem_id = slic_oem.id; 2443 } else { 2444 oem_id = x86ms->oem_id; 2445 } 2446 2447 if (slic_oem.table_id) { 2448 oem_table_id = slic_oem.table_id; 2449 } else { 2450 oem_table_id = x86ms->oem_table_id; 2451 } 2452 2453 table_offsets = g_array_new(false, true /* clear */, 2454 sizeof(uint32_t)); 2455 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2456 2457 bios_linker_loader_alloc(tables->linker, 2458 ACPI_BUILD_TABLE_FILE, tables_blob, 2459 64 /* Ensure FACS is aligned */, 2460 false /* high memory */); 2461 2462 /* 2463 * FACS is pointed to by FADT. 2464 * We place it first since it's the only table that has alignment 2465 * requirements. 2466 */ 2467 facs = tables_blob->len; 2468 build_facs(tables_blob); 2469 2470 /* DSDT is pointed to by FADT */ 2471 dsdt = tables_blob->len; 2472 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2473 &pci_hole, &pci_hole64, machine); 2474 2475 /* ACPI tables pointed to by RSDT */ 2476 acpi_add_table(table_offsets, tables_blob); 2477 pm.fadt.facs_tbl_offset = &facs; 2478 pm.fadt.dsdt_tbl_offset = &dsdt; 2479 pm.fadt.xdsdt_tbl_offset = &dsdt; 2480 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2481 2482 acpi_add_table(table_offsets, tables_blob); 2483 acpi_build_madt(tables_blob, tables->linker, x86ms, 2484 x86ms->oem_id, x86ms->oem_table_id); 2485 2486 #ifdef CONFIG_ACPI_ERST 2487 { 2488 Object *erst_dev; 2489 erst_dev = find_erst_dev(); 2490 if (erst_dev) { 2491 acpi_add_table(table_offsets, tables_blob); 2492 build_erst(tables_blob, tables->linker, erst_dev, 2493 x86ms->oem_id, x86ms->oem_table_id); 2494 } 2495 } 2496 #endif 2497 2498 vmgenid_dev = find_vmgenid_dev(); 2499 if (vmgenid_dev) { 2500 acpi_add_table(table_offsets, tables_blob); 2501 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2502 tables->vmgenid, tables->linker, x86ms->oem_id); 2503 } 2504 2505 if (misc.has_hpet) { 2506 acpi_add_table(table_offsets, tables_blob); 2507 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2508 x86ms->oem_table_id); 2509 } 2510 #ifdef CONFIG_TPM 2511 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2512 if (misc.tpm_version == TPM_VERSION_1_2) { 2513 acpi_add_table(table_offsets, tables_blob); 2514 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2515 x86ms->oem_id, x86ms->oem_table_id); 2516 } else { /* TPM_VERSION_2_0 */ 2517 acpi_add_table(table_offsets, tables_blob); 2518 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2519 x86ms->oem_id, x86ms->oem_table_id); 2520 } 2521 } 2522 #endif 2523 if (machine->numa_state->num_nodes) { 2524 acpi_add_table(table_offsets, tables_blob); 2525 build_srat(tables_blob, tables->linker, machine); 2526 if (machine->numa_state->have_numa_distance) { 2527 acpi_add_table(table_offsets, tables_blob); 2528 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2529 x86ms->oem_table_id); 2530 } 2531 if (machine->numa_state->hmat_enabled) { 2532 acpi_add_table(table_offsets, tables_blob); 2533 build_hmat(tables_blob, tables->linker, machine->numa_state, 2534 x86ms->oem_id, x86ms->oem_table_id); 2535 } 2536 } 2537 if (acpi_get_mcfg(&mcfg)) { 2538 acpi_add_table(table_offsets, tables_blob); 2539 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2540 x86ms->oem_table_id); 2541 } 2542 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2543 acpi_add_table(table_offsets, tables_blob); 2544 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2545 x86ms->oem_table_id); 2546 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2547 acpi_add_table(table_offsets, tables_blob); 2548 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2549 x86ms->oem_table_id); 2550 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2551 PCIDevice *pdev = PCI_DEVICE(iommu); 2552 2553 acpi_add_table(table_offsets, tables_blob); 2554 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2555 x86ms->oem_id, x86ms->oem_table_id); 2556 } 2557 if (machine->nvdimms_state->is_enabled) { 2558 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2559 machine->nvdimms_state, machine->ram_slots, 2560 x86ms->oem_id, x86ms->oem_table_id); 2561 } 2562 if (pcms->cxl_devices_state.is_enabled) { 2563 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2564 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2565 } 2566 2567 acpi_add_table(table_offsets, tables_blob); 2568 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2569 2570 /* Add tables supplied by user (if any) */ 2571 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2572 unsigned len = acpi_table_len(u); 2573 2574 acpi_add_table(table_offsets, tables_blob); 2575 g_array_append_vals(tables_blob, u, len); 2576 } 2577 2578 /* RSDT is pointed to by RSDP */ 2579 rsdt = tables_blob->len; 2580 build_rsdt(tables_blob, tables->linker, table_offsets, 2581 oem_id, oem_table_id); 2582 2583 /* RSDP is in FSEG memory, so allocate it separately */ 2584 { 2585 AcpiRsdpData rsdp_data = { 2586 .revision = 0, 2587 .oem_id = x86ms->oem_id, 2588 .xsdt_tbl_offset = NULL, 2589 .rsdt_tbl_offset = &rsdt, 2590 }; 2591 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2592 } 2593 2594 /* We'll expose it all to Guest so we want to reduce 2595 * chance of size changes. 2596 * 2597 * We used to align the tables to 4k, but of course this would 2598 * too simple to be enough. 4k turned out to be too small an 2599 * alignment very soon, and in fact it is almost impossible to 2600 * keep the table size stable for all (max_cpus, max_memory_slots) 2601 * combinations. 2602 */ 2603 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2604 2605 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2606 2607 /* Cleanup memory that's no longer used. */ 2608 g_array_free(table_offsets, true); 2609 g_free(slic_oem.id); 2610 g_free(slic_oem.table_id); 2611 } 2612 2613 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2614 { 2615 uint32_t size = acpi_data_len(data); 2616 2617 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2618 memory_region_ram_resize(mr, size, &error_abort); 2619 2620 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2621 memory_region_set_dirty(mr, 0, size); 2622 } 2623 2624 static void acpi_build_update(void *build_opaque) 2625 { 2626 AcpiBuildState *build_state = build_opaque; 2627 AcpiBuildTables tables; 2628 2629 /* No state to update or already patched? Nothing to do. */ 2630 if (!build_state || build_state->patched) { 2631 return; 2632 } 2633 build_state->patched = 1; 2634 2635 acpi_build_tables_init(&tables); 2636 2637 acpi_build(&tables, MACHINE(qdev_get_machine())); 2638 2639 acpi_ram_update(build_state->table_mr, tables.table_data); 2640 2641 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2642 2643 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2644 acpi_build_tables_cleanup(&tables, true); 2645 } 2646 2647 static void acpi_build_reset(void *build_opaque) 2648 { 2649 AcpiBuildState *build_state = build_opaque; 2650 build_state->patched = 0; 2651 } 2652 2653 static const VMStateDescription vmstate_acpi_build = { 2654 .name = "acpi_build", 2655 .version_id = 1, 2656 .minimum_version_id = 1, 2657 .fields = (const VMStateField[]) { 2658 VMSTATE_UINT8(patched, AcpiBuildState), 2659 VMSTATE_END_OF_LIST() 2660 }, 2661 }; 2662 2663 void acpi_setup(void) 2664 { 2665 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2666 X86MachineState *x86ms = X86_MACHINE(pcms); 2667 AcpiBuildTables tables; 2668 AcpiBuildState *build_state; 2669 Object *vmgenid_dev; 2670 #ifdef CONFIG_TPM 2671 TPMIf *tpm; 2672 static FwCfgTPMConfig tpm_config; 2673 #endif 2674 2675 if (!x86ms->fw_cfg) { 2676 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2677 return; 2678 } 2679 2680 if (!pcms->acpi_build_enabled) { 2681 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2682 return; 2683 } 2684 2685 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2686 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2687 return; 2688 } 2689 2690 build_state = g_malloc0(sizeof *build_state); 2691 2692 acpi_build_tables_init(&tables); 2693 acpi_build(&tables, MACHINE(pcms)); 2694 2695 /* Now expose it all to Guest */ 2696 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2697 build_state, tables.table_data, 2698 ACPI_BUILD_TABLE_FILE); 2699 assert(build_state->table_mr != NULL); 2700 2701 build_state->linker_mr = 2702 acpi_add_rom_blob(acpi_build_update, build_state, 2703 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2704 2705 #ifdef CONFIG_TPM 2706 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2707 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2708 2709 tpm = tpm_find(); 2710 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2711 tpm_config = (FwCfgTPMConfig) { 2712 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2713 .tpm_version = tpm_get_version(tpm), 2714 .tpmppi_version = TPM_PPI_VERSION_1_30 2715 }; 2716 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2717 &tpm_config, sizeof tpm_config); 2718 } 2719 #endif 2720 2721 vmgenid_dev = find_vmgenid_dev(); 2722 if (vmgenid_dev) { 2723 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2724 tables.vmgenid); 2725 } 2726 2727 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2728 build_state, tables.rsdp, 2729 ACPI_BUILD_RSDP_FILE); 2730 2731 qemu_register_reset(acpi_build_reset, build_state); 2732 acpi_build_reset(build_state); 2733 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2734 2735 /* Cleanup tables but don't free the memory: we track it 2736 * in build_state. 2737 */ 2738 acpi_build_tables_cleanup(&tables, false); 2739 } 2740