1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/error-report.h" 29 #include "hw/pci/pci.h" 30 #include "qom/cpu.h" 31 #include "target/i386/cpu.h" 32 #include "hw/misc/pvpanic.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/acpi/acpi-defs.h" 35 #include "hw/acpi/acpi.h" 36 #include "hw/acpi/cpu.h" 37 #include "hw/acpi/piix4.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "sysemu/tpm_backend.h" 47 #include "hw/timer/mc146818rtc_regs.h" 48 #include "hw/mem/memory-device.h" 49 #include "sysemu/numa.h" 50 51 /* Supported chipsets: */ 52 #include "hw/acpi/piix4.h" 53 #include "hw/acpi/pcihp.h" 54 #include "hw/i386/ich9.h" 55 #include "hw/pci/pci_bus.h" 56 #include "hw/pci-host/q35.h" 57 #include "hw/i386/x86-iommu.h" 58 59 #include "hw/acpi/aml-build.h" 60 #include "hw/acpi/utils.h" 61 #include "hw/acpi/pci.h" 62 63 #include "qom/qom-qobject.h" 64 #include "hw/i386/amd_iommu.h" 65 #include "hw/i386/intel_iommu.h" 66 67 #include "hw/acpi/ipmi.h" 68 69 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 70 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 71 * a little bit, there should be plenty of free space since the DSDT 72 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 73 */ 74 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 75 #define ACPI_BUILD_ALIGN_SIZE 0x1000 76 77 #define ACPI_BUILD_TABLE_SIZE 0x20000 78 79 /* #define DEBUG_ACPI_BUILD */ 80 #ifdef DEBUG_ACPI_BUILD 81 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 82 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 83 #else 84 #define ACPI_BUILD_DPRINTF(fmt, ...) 85 #endif 86 87 /* Default IOAPIC ID */ 88 #define ACPI_BUILD_IOAPIC_ID 0x0 89 90 typedef struct AcpiPmInfo { 91 bool s3_disabled; 92 bool s4_disabled; 93 bool pcihp_bridge_en; 94 uint8_t s4_val; 95 AcpiFadtData fadt; 96 uint16_t cpu_hp_io_base; 97 uint16_t pcihp_io_base; 98 uint16_t pcihp_io_len; 99 } AcpiPmInfo; 100 101 typedef struct AcpiMiscInfo { 102 bool is_piix4; 103 bool has_hpet; 104 TPMVersion tpm_version; 105 const unsigned char *dsdt_code; 106 unsigned dsdt_size; 107 uint16_t pvpanic_port; 108 uint16_t applesmc_io_base; 109 } AcpiMiscInfo; 110 111 typedef struct AcpiBuildPciBusHotplugState { 112 GArray *device_table; 113 GArray *notify_table; 114 struct AcpiBuildPciBusHotplugState *parent; 115 bool pcihp_bridge_en; 116 } AcpiBuildPciBusHotplugState; 117 118 typedef struct FwCfgTPMConfig { 119 uint32_t tpmppi_address; 120 uint8_t tpm_version; 121 uint8_t tpmppi_version; 122 } QEMU_PACKED FwCfgTPMConfig; 123 124 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 125 126 static void init_common_fadt_data(Object *o, AcpiFadtData *data) 127 { 128 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 129 AmlAddressSpace as = AML_AS_SYSTEM_IO; 130 AcpiFadtData fadt = { 131 .rev = 3, 132 .flags = 133 (1 << ACPI_FADT_F_WBINVD) | 134 (1 << ACPI_FADT_F_PROC_C1) | 135 (1 << ACPI_FADT_F_SLP_BUTTON) | 136 (1 << ACPI_FADT_F_RTC_S4) | 137 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 138 /* APIC destination mode ("Flat Logical") has an upper limit of 8 139 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 140 * used 141 */ 142 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 143 .int_model = 1 /* Multiple APIC */, 144 .rtc_century = RTC_CENTURY, 145 .plvl2_lat = 0xfff /* C2 state not supported */, 146 .plvl3_lat = 0xfff /* C3 state not supported */, 147 .smi_cmd = ACPI_PORT_SMI_CMD, 148 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 149 .acpi_enable_cmd = 150 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 151 .acpi_disable_cmd = 152 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 153 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 154 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 155 .address = io + 0x04 }, 156 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 157 .gpe0_blk = { .space_id = as, .bit_width = 158 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 159 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 160 }, 161 }; 162 *data = fadt; 163 } 164 165 static Object *object_resolve_type_unambiguous(const char *typename) 166 { 167 bool ambig; 168 Object *o = object_resolve_path_type("", typename, &ambig); 169 170 if (ambig || !o) { 171 return NULL; 172 } 173 return o; 174 } 175 176 static void acpi_get_pm_info(AcpiPmInfo *pm) 177 { 178 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 179 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 180 Object *obj = piix ? piix : lpc; 181 QObject *o; 182 pm->cpu_hp_io_base = 0; 183 pm->pcihp_io_base = 0; 184 pm->pcihp_io_len = 0; 185 186 assert(obj); 187 init_common_fadt_data(obj, &pm->fadt); 188 if (piix) { 189 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 190 pm->fadt.rev = 1; 191 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 192 pm->pcihp_io_base = 193 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 194 pm->pcihp_io_len = 195 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 196 } 197 if (lpc) { 198 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 199 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 200 pm->fadt.reset_reg = r; 201 pm->fadt.reset_val = 0xf; 202 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 203 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 204 } 205 206 /* The above need not be conditional on machine type because the reset port 207 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 208 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT); 209 210 /* Fill in optional s3/s4 related properties */ 211 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 212 if (o) { 213 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 214 } else { 215 pm->s3_disabled = false; 216 } 217 qobject_unref(o); 218 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 219 if (o) { 220 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 221 } else { 222 pm->s4_disabled = false; 223 } 224 qobject_unref(o); 225 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 226 if (o) { 227 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 228 } else { 229 pm->s4_val = false; 230 } 231 qobject_unref(o); 232 233 pm->pcihp_bridge_en = 234 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 235 NULL); 236 } 237 238 static void acpi_get_misc_info(AcpiMiscInfo *info) 239 { 240 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 241 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 242 assert(!!piix != !!lpc); 243 244 if (piix) { 245 info->is_piix4 = true; 246 } 247 if (lpc) { 248 info->is_piix4 = false; 249 } 250 251 info->has_hpet = hpet_find(); 252 info->tpm_version = tpm_get_version(tpm_find()); 253 info->pvpanic_port = pvpanic_port(); 254 info->applesmc_io_base = applesmc_port(); 255 } 256 257 /* 258 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 259 * On i386 arch we only have two pci hosts, so we can look only for them. 260 */ 261 static Object *acpi_get_i386_pci_host(void) 262 { 263 PCIHostState *host; 264 265 host = OBJECT_CHECK(PCIHostState, 266 object_resolve_path("/machine/i440fx", NULL), 267 TYPE_PCI_HOST_BRIDGE); 268 if (!host) { 269 host = OBJECT_CHECK(PCIHostState, 270 object_resolve_path("/machine/q35", NULL), 271 TYPE_PCI_HOST_BRIDGE); 272 } 273 274 return OBJECT(host); 275 } 276 277 static void acpi_get_pci_holes(Range *hole, Range *hole64) 278 { 279 Object *pci_host; 280 281 pci_host = acpi_get_i386_pci_host(); 282 g_assert(pci_host); 283 284 range_set_bounds1(hole, 285 object_property_get_uint(pci_host, 286 PCI_HOST_PROP_PCI_HOLE_START, 287 NULL), 288 object_property_get_uint(pci_host, 289 PCI_HOST_PROP_PCI_HOLE_END, 290 NULL)); 291 range_set_bounds1(hole64, 292 object_property_get_uint(pci_host, 293 PCI_HOST_PROP_PCI_HOLE64_START, 294 NULL), 295 object_property_get_uint(pci_host, 296 PCI_HOST_PROP_PCI_HOLE64_END, 297 NULL)); 298 } 299 300 static void acpi_align_size(GArray *blob, unsigned align) 301 { 302 /* Align size to multiple of given size. This reduces the chance 303 * we need to change size in the future (breaking cross version migration). 304 */ 305 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 306 } 307 308 /* FACS */ 309 static void 310 build_facs(GArray *table_data) 311 { 312 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 313 memcpy(&facs->signature, "FACS", 4); 314 facs->length = cpu_to_le32(sizeof(*facs)); 315 } 316 317 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 318 const CPUArchIdList *apic_ids, GArray *entry) 319 { 320 uint32_t apic_id = apic_ids->cpus[uid].arch_id; 321 322 /* ACPI spec says that LAPIC entry for non present 323 * CPU may be omitted from MADT or it must be marked 324 * as disabled. However omitting non present CPU from 325 * MADT breaks hotplug on linux. So possible CPUs 326 * should be put in MADT but kept disabled. 327 */ 328 if (apic_id < 255) { 329 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic); 330 331 apic->type = ACPI_APIC_PROCESSOR; 332 apic->length = sizeof(*apic); 333 apic->processor_id = uid; 334 apic->local_apic_id = apic_id; 335 if (apic_ids->cpus[uid].cpu != NULL) { 336 apic->flags = cpu_to_le32(1); 337 } else { 338 apic->flags = cpu_to_le32(0); 339 } 340 } else { 341 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic); 342 343 apic->type = ACPI_APIC_LOCAL_X2APIC; 344 apic->length = sizeof(*apic); 345 apic->uid = cpu_to_le32(uid); 346 apic->x2apic_id = cpu_to_le32(apic_id); 347 if (apic_ids->cpus[uid].cpu != NULL) { 348 apic->flags = cpu_to_le32(1); 349 } else { 350 apic->flags = cpu_to_le32(0); 351 } 352 } 353 } 354 355 static void 356 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms) 357 { 358 MachineClass *mc = MACHINE_GET_CLASS(pcms); 359 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms)); 360 int madt_start = table_data->len; 361 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev); 362 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev); 363 bool x2apic_mode = false; 364 365 AcpiMultipleApicTable *madt; 366 AcpiMadtIoApic *io_apic; 367 AcpiMadtIntsrcovr *intsrcovr; 368 int i; 369 370 madt = acpi_data_push(table_data, sizeof *madt); 371 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 372 madt->flags = cpu_to_le32(1); 373 374 for (i = 0; i < apic_ids->len; i++) { 375 adevc->madt_cpu(adev, i, apic_ids, table_data); 376 if (apic_ids->cpus[i].arch_id > 254) { 377 x2apic_mode = true; 378 } 379 } 380 381 io_apic = acpi_data_push(table_data, sizeof *io_apic); 382 io_apic->type = ACPI_APIC_IO; 383 io_apic->length = sizeof(*io_apic); 384 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 385 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 386 io_apic->interrupt = cpu_to_le32(0); 387 388 if (pcms->apic_xrupt_override) { 389 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 390 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 391 intsrcovr->length = sizeof(*intsrcovr); 392 intsrcovr->source = 0; 393 intsrcovr->gsi = cpu_to_le32(2); 394 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 395 } 396 for (i = 1; i < 16; i++) { 397 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 398 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 399 /* No need for a INT source override structure. */ 400 continue; 401 } 402 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 403 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 404 intsrcovr->length = sizeof(*intsrcovr); 405 intsrcovr->source = i; 406 intsrcovr->gsi = cpu_to_le32(i); 407 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 408 } 409 410 if (x2apic_mode) { 411 AcpiMadtLocalX2ApicNmi *local_nmi; 412 413 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 414 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI; 415 local_nmi->length = sizeof(*local_nmi); 416 local_nmi->uid = 0xFFFFFFFF; /* all processors */ 417 local_nmi->flags = cpu_to_le16(0); 418 local_nmi->lint = 1; /* ACPI_LINT1 */ 419 } else { 420 AcpiMadtLocalNmi *local_nmi; 421 422 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 423 local_nmi->type = ACPI_APIC_LOCAL_NMI; 424 local_nmi->length = sizeof(*local_nmi); 425 local_nmi->processor_id = 0xff; /* all processors */ 426 local_nmi->flags = cpu_to_le16(0); 427 local_nmi->lint = 1; /* ACPI_LINT1 */ 428 } 429 430 build_header(linker, table_data, 431 (void *)(table_data->data + madt_start), "APIC", 432 table_data->len - madt_start, 1, NULL, NULL); 433 } 434 435 static void build_append_pcihp_notify_entry(Aml *method, int slot) 436 { 437 Aml *if_ctx; 438 int32_t devfn = PCI_DEVFN(slot, 0); 439 440 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 441 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 442 aml_append(method, if_ctx); 443 } 444 445 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 446 bool pcihp_bridge_en) 447 { 448 Aml *dev, *notify_method = NULL, *method; 449 QObject *bsel; 450 PCIBus *sec; 451 int i; 452 453 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 454 if (bsel) { 455 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 456 457 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 458 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 459 } 460 461 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 462 DeviceClass *dc; 463 PCIDeviceClass *pc; 464 PCIDevice *pdev = bus->devices[i]; 465 int slot = PCI_SLOT(i); 466 bool hotplug_enabled_dev; 467 bool bridge_in_acpi; 468 469 if (!pdev) { 470 if (bsel) { /* add hotplug slots for non present devices */ 471 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 472 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 473 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 474 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 475 aml_append(method, 476 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 477 ); 478 aml_append(dev, method); 479 aml_append(parent_scope, dev); 480 481 build_append_pcihp_notify_entry(notify_method, slot); 482 } 483 continue; 484 } 485 486 pc = PCI_DEVICE_GET_CLASS(pdev); 487 dc = DEVICE_GET_CLASS(pdev); 488 489 /* When hotplug for bridges is enabled, bridges are 490 * described in ACPI separately (see build_pci_bus_end). 491 * In this case they aren't themselves hot-pluggable. 492 * Hotplugged bridges *are* hot-pluggable. 493 */ 494 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 495 !DEVICE(pdev)->hotplugged; 496 497 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 498 499 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 500 continue; 501 } 502 503 /* start to compose PCI slot descriptor */ 504 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 505 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 506 507 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 508 /* add VGA specific AML methods */ 509 int s3d; 510 511 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 512 s3d = 3; 513 } else { 514 s3d = 0; 515 } 516 517 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 518 aml_append(method, aml_return(aml_int(0))); 519 aml_append(dev, method); 520 521 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 522 aml_append(method, aml_return(aml_int(0))); 523 aml_append(dev, method); 524 525 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 526 aml_append(method, aml_return(aml_int(s3d))); 527 aml_append(dev, method); 528 } else if (hotplug_enabled_dev) { 529 /* add _SUN/_EJ0 to make slot hotpluggable */ 530 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 531 532 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 533 aml_append(method, 534 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 535 ); 536 aml_append(dev, method); 537 538 if (bsel) { 539 build_append_pcihp_notify_entry(notify_method, slot); 540 } 541 } else if (bridge_in_acpi) { 542 /* 543 * device is coldplugged bridge, 544 * add child device descriptions into its scope 545 */ 546 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 547 548 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 549 } 550 /* slot descriptor has been composed, add it into parent context */ 551 aml_append(parent_scope, dev); 552 } 553 554 if (bsel) { 555 aml_append(parent_scope, notify_method); 556 } 557 558 /* Append PCNT method to notify about events on local and child buses. 559 * Add unconditionally for root since DSDT expects it. 560 */ 561 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 562 563 /* If bus supports hotplug select it and notify about local events */ 564 if (bsel) { 565 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 566 567 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 568 aml_append(method, 569 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 570 ); 571 aml_append(method, 572 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 573 ); 574 } 575 576 /* Notify about child bus events in any case */ 577 if (pcihp_bridge_en) { 578 QLIST_FOREACH(sec, &bus->child, sibling) { 579 int32_t devfn = sec->parent_dev->devfn; 580 581 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 582 continue; 583 } 584 585 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 586 } 587 } 588 aml_append(parent_scope, method); 589 qobject_unref(bsel); 590 } 591 592 /** 593 * build_prt_entry: 594 * @link_name: link name for PCI route entry 595 * 596 * build AML package containing a PCI route entry for @link_name 597 */ 598 static Aml *build_prt_entry(const char *link_name) 599 { 600 Aml *a_zero = aml_int(0); 601 Aml *pkg = aml_package(4); 602 aml_append(pkg, a_zero); 603 aml_append(pkg, a_zero); 604 aml_append(pkg, aml_name("%s", link_name)); 605 aml_append(pkg, a_zero); 606 return pkg; 607 } 608 609 /* 610 * initialize_route - Initialize the interrupt routing rule 611 * through a specific LINK: 612 * if (lnk_idx == idx) 613 * route using link 'link_name' 614 */ 615 static Aml *initialize_route(Aml *route, const char *link_name, 616 Aml *lnk_idx, int idx) 617 { 618 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 619 Aml *pkg = build_prt_entry(link_name); 620 621 aml_append(if_ctx, aml_store(pkg, route)); 622 623 return if_ctx; 624 } 625 626 /* 627 * build_prt - Define interrupt rounting rules 628 * 629 * Returns an array of 128 routes, one for each device, 630 * based on device location. 631 * The main goal is to equaly distribute the interrupts 632 * over the 4 existing ACPI links (works only for i440fx). 633 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 634 * 635 */ 636 static Aml *build_prt(bool is_pci0_prt) 637 { 638 Aml *method, *while_ctx, *pin, *res; 639 640 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 641 res = aml_local(0); 642 pin = aml_local(1); 643 aml_append(method, aml_store(aml_package(128), res)); 644 aml_append(method, aml_store(aml_int(0), pin)); 645 646 /* while (pin < 128) */ 647 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 648 { 649 Aml *slot = aml_local(2); 650 Aml *lnk_idx = aml_local(3); 651 Aml *route = aml_local(4); 652 653 /* slot = pin >> 2 */ 654 aml_append(while_ctx, 655 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 656 /* lnk_idx = (slot + pin) & 3 */ 657 aml_append(while_ctx, 658 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 659 lnk_idx)); 660 661 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 662 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 663 if (is_pci0_prt) { 664 Aml *if_device_1, *if_pin_4, *else_pin_4; 665 666 /* device 1 is the power-management device, needs SCI */ 667 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 668 { 669 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 670 { 671 aml_append(if_pin_4, 672 aml_store(build_prt_entry("LNKS"), route)); 673 } 674 aml_append(if_device_1, if_pin_4); 675 else_pin_4 = aml_else(); 676 { 677 aml_append(else_pin_4, 678 aml_store(build_prt_entry("LNKA"), route)); 679 } 680 aml_append(if_device_1, else_pin_4); 681 } 682 aml_append(while_ctx, if_device_1); 683 } else { 684 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 685 } 686 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 687 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 688 689 /* route[0] = 0x[slot]FFFF */ 690 aml_append(while_ctx, 691 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 692 NULL), 693 aml_index(route, aml_int(0)))); 694 /* route[1] = pin & 3 */ 695 aml_append(while_ctx, 696 aml_store(aml_and(pin, aml_int(3), NULL), 697 aml_index(route, aml_int(1)))); 698 /* res[pin] = route */ 699 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 700 /* pin++ */ 701 aml_append(while_ctx, aml_increment(pin)); 702 } 703 aml_append(method, while_ctx); 704 /* return res*/ 705 aml_append(method, aml_return(res)); 706 707 return method; 708 } 709 710 typedef struct CrsRangeEntry { 711 uint64_t base; 712 uint64_t limit; 713 } CrsRangeEntry; 714 715 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 716 { 717 CrsRangeEntry *entry; 718 719 entry = g_malloc(sizeof(*entry)); 720 entry->base = base; 721 entry->limit = limit; 722 723 g_ptr_array_add(ranges, entry); 724 } 725 726 static void crs_range_free(gpointer data) 727 { 728 CrsRangeEntry *entry = (CrsRangeEntry *)data; 729 g_free(entry); 730 } 731 732 typedef struct CrsRangeSet { 733 GPtrArray *io_ranges; 734 GPtrArray *mem_ranges; 735 GPtrArray *mem_64bit_ranges; 736 } CrsRangeSet; 737 738 static void crs_range_set_init(CrsRangeSet *range_set) 739 { 740 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 741 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 742 range_set->mem_64bit_ranges = 743 g_ptr_array_new_with_free_func(crs_range_free); 744 } 745 746 static void crs_range_set_free(CrsRangeSet *range_set) 747 { 748 g_ptr_array_free(range_set->io_ranges, true); 749 g_ptr_array_free(range_set->mem_ranges, true); 750 g_ptr_array_free(range_set->mem_64bit_ranges, true); 751 } 752 753 static gint crs_range_compare(gconstpointer a, gconstpointer b) 754 { 755 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 756 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 757 758 return (int64_t)entry_a->base - (int64_t)entry_b->base; 759 } 760 761 /* 762 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 763 * interval, computes the 'free' ranges from the same interval. 764 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 765 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 766 */ 767 static void crs_replace_with_free_ranges(GPtrArray *ranges, 768 uint64_t start, uint64_t end) 769 { 770 GPtrArray *free_ranges = g_ptr_array_new(); 771 uint64_t free_base = start; 772 int i; 773 774 g_ptr_array_sort(ranges, crs_range_compare); 775 for (i = 0; i < ranges->len; i++) { 776 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 777 778 if (free_base < used->base) { 779 crs_range_insert(free_ranges, free_base, used->base - 1); 780 } 781 782 free_base = used->limit + 1; 783 } 784 785 if (free_base < end) { 786 crs_range_insert(free_ranges, free_base, end); 787 } 788 789 g_ptr_array_set_size(ranges, 0); 790 for (i = 0; i < free_ranges->len; i++) { 791 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 792 } 793 794 g_ptr_array_free(free_ranges, true); 795 } 796 797 /* 798 * crs_range_merge - merges adjacent ranges in the given array. 799 * Array elements are deleted and replaced with the merged ranges. 800 */ 801 static void crs_range_merge(GPtrArray *range) 802 { 803 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 804 CrsRangeEntry *entry; 805 uint64_t range_base, range_limit; 806 int i; 807 808 if (!range->len) { 809 return; 810 } 811 812 g_ptr_array_sort(range, crs_range_compare); 813 814 entry = g_ptr_array_index(range, 0); 815 range_base = entry->base; 816 range_limit = entry->limit; 817 for (i = 1; i < range->len; i++) { 818 entry = g_ptr_array_index(range, i); 819 if (entry->base - 1 == range_limit) { 820 range_limit = entry->limit; 821 } else { 822 crs_range_insert(tmp, range_base, range_limit); 823 range_base = entry->base; 824 range_limit = entry->limit; 825 } 826 } 827 crs_range_insert(tmp, range_base, range_limit); 828 829 g_ptr_array_set_size(range, 0); 830 for (i = 0; i < tmp->len; i++) { 831 entry = g_ptr_array_index(tmp, i); 832 crs_range_insert(range, entry->base, entry->limit); 833 } 834 g_ptr_array_free(tmp, true); 835 } 836 837 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 838 { 839 Aml *crs = aml_resource_template(); 840 CrsRangeSet temp_range_set; 841 CrsRangeEntry *entry; 842 uint8_t max_bus = pci_bus_num(host->bus); 843 uint8_t type; 844 int devfn; 845 int i; 846 847 crs_range_set_init(&temp_range_set); 848 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 849 uint64_t range_base, range_limit; 850 PCIDevice *dev = host->bus->devices[devfn]; 851 852 if (!dev) { 853 continue; 854 } 855 856 for (i = 0; i < PCI_NUM_REGIONS; i++) { 857 PCIIORegion *r = &dev->io_regions[i]; 858 859 range_base = r->addr; 860 range_limit = r->addr + r->size - 1; 861 862 /* 863 * Work-around for old bioses 864 * that do not support multiple root buses 865 */ 866 if (!range_base || range_base > range_limit) { 867 continue; 868 } 869 870 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 871 crs_range_insert(temp_range_set.io_ranges, 872 range_base, range_limit); 873 } else { /* "memory" */ 874 crs_range_insert(temp_range_set.mem_ranges, 875 range_base, range_limit); 876 } 877 } 878 879 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 880 if (type == PCI_HEADER_TYPE_BRIDGE) { 881 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 882 if (subordinate > max_bus) { 883 max_bus = subordinate; 884 } 885 886 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 887 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 888 889 /* 890 * Work-around for old bioses 891 * that do not support multiple root buses 892 */ 893 if (range_base && range_base <= range_limit) { 894 crs_range_insert(temp_range_set.io_ranges, 895 range_base, range_limit); 896 } 897 898 range_base = 899 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 900 range_limit = 901 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 902 903 /* 904 * Work-around for old bioses 905 * that do not support multiple root buses 906 */ 907 if (range_base && range_base <= range_limit) { 908 uint64_t length = range_limit - range_base + 1; 909 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 910 crs_range_insert(temp_range_set.mem_ranges, 911 range_base, range_limit); 912 } else { 913 crs_range_insert(temp_range_set.mem_64bit_ranges, 914 range_base, range_limit); 915 } 916 } 917 918 range_base = 919 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 920 range_limit = 921 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 922 923 /* 924 * Work-around for old bioses 925 * that do not support multiple root buses 926 */ 927 if (range_base && range_base <= range_limit) { 928 uint64_t length = range_limit - range_base + 1; 929 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 930 crs_range_insert(temp_range_set.mem_ranges, 931 range_base, range_limit); 932 } else { 933 crs_range_insert(temp_range_set.mem_64bit_ranges, 934 range_base, range_limit); 935 } 936 } 937 } 938 } 939 940 crs_range_merge(temp_range_set.io_ranges); 941 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 942 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 943 aml_append(crs, 944 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 945 AML_POS_DECODE, AML_ENTIRE_RANGE, 946 0, entry->base, entry->limit, 0, 947 entry->limit - entry->base + 1)); 948 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 949 } 950 951 crs_range_merge(temp_range_set.mem_ranges); 952 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 953 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 954 aml_append(crs, 955 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 956 AML_MAX_FIXED, AML_NON_CACHEABLE, 957 AML_READ_WRITE, 958 0, entry->base, entry->limit, 0, 959 entry->limit - entry->base + 1)); 960 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 961 } 962 963 crs_range_merge(temp_range_set.mem_64bit_ranges); 964 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 965 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 966 aml_append(crs, 967 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 968 AML_MAX_FIXED, AML_NON_CACHEABLE, 969 AML_READ_WRITE, 970 0, entry->base, entry->limit, 0, 971 entry->limit - entry->base + 1)); 972 crs_range_insert(range_set->mem_64bit_ranges, 973 entry->base, entry->limit); 974 } 975 976 crs_range_set_free(&temp_range_set); 977 978 aml_append(crs, 979 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 980 0, 981 pci_bus_num(host->bus), 982 max_bus, 983 0, 984 max_bus - pci_bus_num(host->bus) + 1)); 985 986 return crs; 987 } 988 989 static void build_hpet_aml(Aml *table) 990 { 991 Aml *crs; 992 Aml *field; 993 Aml *method; 994 Aml *if_ctx; 995 Aml *scope = aml_scope("_SB"); 996 Aml *dev = aml_device("HPET"); 997 Aml *zero = aml_int(0); 998 Aml *id = aml_local(0); 999 Aml *period = aml_local(1); 1000 1001 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1002 aml_append(dev, aml_name_decl("_UID", zero)); 1003 1004 aml_append(dev, 1005 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 1006 HPET_LEN)); 1007 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1008 aml_append(field, aml_named_field("VEND", 32)); 1009 aml_append(field, aml_named_field("PRD", 32)); 1010 aml_append(dev, field); 1011 1012 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1013 aml_append(method, aml_store(aml_name("VEND"), id)); 1014 aml_append(method, aml_store(aml_name("PRD"), period)); 1015 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1016 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1017 aml_equal(id, aml_int(0xffff)))); 1018 { 1019 aml_append(if_ctx, aml_return(zero)); 1020 } 1021 aml_append(method, if_ctx); 1022 1023 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1024 aml_lgreater(period, aml_int(100000000)))); 1025 { 1026 aml_append(if_ctx, aml_return(zero)); 1027 } 1028 aml_append(method, if_ctx); 1029 1030 aml_append(method, aml_return(aml_int(0x0F))); 1031 aml_append(dev, method); 1032 1033 crs = aml_resource_template(); 1034 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1035 aml_append(dev, aml_name_decl("_CRS", crs)); 1036 1037 aml_append(scope, dev); 1038 aml_append(table, scope); 1039 } 1040 1041 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1042 { 1043 Aml *dev, *fdi; 1044 uint8_t maxc, maxh, maxs; 1045 1046 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1047 1048 dev = aml_device("FLP%c", 'A' + idx); 1049 1050 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1051 1052 fdi = aml_package(16); 1053 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1054 aml_append(fdi, 1055 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1056 /* 1057 * the values below are the limits of the drive, and are thus independent 1058 * of the inserted media 1059 */ 1060 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1061 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1062 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1063 /* 1064 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1065 * the drive type, so shall we 1066 */ 1067 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1068 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1069 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1070 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1071 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1072 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1073 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1074 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1075 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1076 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1077 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1078 1079 aml_append(dev, aml_name_decl("_FDI", fdi)); 1080 return dev; 1081 } 1082 1083 static Aml *build_fdc_device_aml(ISADevice *fdc) 1084 { 1085 int i; 1086 Aml *dev; 1087 Aml *crs; 1088 1089 #define ACPI_FDE_MAX_FD 4 1090 uint32_t fde_buf[5] = { 1091 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1092 cpu_to_le32(2) /* tape presence (2 == never present) */ 1093 }; 1094 1095 dev = aml_device("FDC0"); 1096 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1097 1098 crs = aml_resource_template(); 1099 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1100 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1101 aml_append(crs, aml_irq_no_flags(6)); 1102 aml_append(crs, 1103 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1104 aml_append(dev, aml_name_decl("_CRS", crs)); 1105 1106 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1107 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1108 1109 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1110 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1111 aml_append(dev, build_fdinfo_aml(i, type)); 1112 } 1113 } 1114 aml_append(dev, aml_name_decl("_FDE", 1115 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1116 1117 return dev; 1118 } 1119 1120 static Aml *build_rtc_device_aml(void) 1121 { 1122 Aml *dev; 1123 Aml *crs; 1124 1125 dev = aml_device("RTC"); 1126 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1127 crs = aml_resource_template(); 1128 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1129 aml_append(crs, aml_irq_no_flags(8)); 1130 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1131 aml_append(dev, aml_name_decl("_CRS", crs)); 1132 1133 return dev; 1134 } 1135 1136 static Aml *build_kbd_device_aml(void) 1137 { 1138 Aml *dev; 1139 Aml *crs; 1140 Aml *method; 1141 1142 dev = aml_device("KBD"); 1143 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1144 1145 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1146 aml_append(method, aml_return(aml_int(0x0f))); 1147 aml_append(dev, method); 1148 1149 crs = aml_resource_template(); 1150 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1151 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1152 aml_append(crs, aml_irq_no_flags(1)); 1153 aml_append(dev, aml_name_decl("_CRS", crs)); 1154 1155 return dev; 1156 } 1157 1158 static Aml *build_mouse_device_aml(void) 1159 { 1160 Aml *dev; 1161 Aml *crs; 1162 Aml *method; 1163 1164 dev = aml_device("MOU"); 1165 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1166 1167 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1168 aml_append(method, aml_return(aml_int(0x0f))); 1169 aml_append(dev, method); 1170 1171 crs = aml_resource_template(); 1172 aml_append(crs, aml_irq_no_flags(12)); 1173 aml_append(dev, aml_name_decl("_CRS", crs)); 1174 1175 return dev; 1176 } 1177 1178 static Aml *build_lpt_device_aml(void) 1179 { 1180 Aml *dev; 1181 Aml *crs; 1182 Aml *method; 1183 Aml *if_ctx; 1184 Aml *else_ctx; 1185 Aml *zero = aml_int(0); 1186 Aml *is_present = aml_local(0); 1187 1188 dev = aml_device("LPT"); 1189 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1190 1191 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1192 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1193 if_ctx = aml_if(aml_equal(is_present, zero)); 1194 { 1195 aml_append(if_ctx, aml_return(aml_int(0x00))); 1196 } 1197 aml_append(method, if_ctx); 1198 else_ctx = aml_else(); 1199 { 1200 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1201 } 1202 aml_append(method, else_ctx); 1203 aml_append(dev, method); 1204 1205 crs = aml_resource_template(); 1206 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1207 aml_append(crs, aml_irq_no_flags(7)); 1208 aml_append(dev, aml_name_decl("_CRS", crs)); 1209 1210 return dev; 1211 } 1212 1213 static Aml *build_com_device_aml(uint8_t uid) 1214 { 1215 Aml *dev; 1216 Aml *crs; 1217 Aml *method; 1218 Aml *if_ctx; 1219 Aml *else_ctx; 1220 Aml *zero = aml_int(0); 1221 Aml *is_present = aml_local(0); 1222 const char *enabled_field = "CAEN"; 1223 uint8_t irq = 4; 1224 uint16_t io_port = 0x03F8; 1225 1226 assert(uid == 1 || uid == 2); 1227 if (uid == 2) { 1228 enabled_field = "CBEN"; 1229 irq = 3; 1230 io_port = 0x02F8; 1231 } 1232 1233 dev = aml_device("COM%d", uid); 1234 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1235 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1236 1237 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1238 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1239 if_ctx = aml_if(aml_equal(is_present, zero)); 1240 { 1241 aml_append(if_ctx, aml_return(aml_int(0x00))); 1242 } 1243 aml_append(method, if_ctx); 1244 else_ctx = aml_else(); 1245 { 1246 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1247 } 1248 aml_append(method, else_ctx); 1249 aml_append(dev, method); 1250 1251 crs = aml_resource_template(); 1252 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1253 aml_append(crs, aml_irq_no_flags(irq)); 1254 aml_append(dev, aml_name_decl("_CRS", crs)); 1255 1256 return dev; 1257 } 1258 1259 static void build_isa_devices_aml(Aml *table) 1260 { 1261 ISADevice *fdc = pc_find_fdc0(); 1262 bool ambiguous; 1263 1264 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1265 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 1266 1267 aml_append(scope, build_rtc_device_aml()); 1268 aml_append(scope, build_kbd_device_aml()); 1269 aml_append(scope, build_mouse_device_aml()); 1270 if (fdc) { 1271 aml_append(scope, build_fdc_device_aml(fdc)); 1272 } 1273 aml_append(scope, build_lpt_device_aml()); 1274 aml_append(scope, build_com_device_aml(1)); 1275 aml_append(scope, build_com_device_aml(2)); 1276 1277 if (ambiguous) { 1278 error_report("Multiple ISA busses, unable to define IPMI ACPI data"); 1279 } else if (!obj) { 1280 error_report("No ISA bus, unable to define IPMI ACPI data"); 1281 } else { 1282 build_acpi_ipmi_devices(scope, BUS(obj)); 1283 } 1284 1285 aml_append(table, scope); 1286 } 1287 1288 static void build_dbg_aml(Aml *table) 1289 { 1290 Aml *field; 1291 Aml *method; 1292 Aml *while_ctx; 1293 Aml *scope = aml_scope("\\"); 1294 Aml *buf = aml_local(0); 1295 Aml *len = aml_local(1); 1296 Aml *idx = aml_local(2); 1297 1298 aml_append(scope, 1299 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1300 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1301 aml_append(field, aml_named_field("DBGB", 8)); 1302 aml_append(scope, field); 1303 1304 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1305 1306 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1307 aml_append(method, aml_to_buffer(buf, buf)); 1308 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1309 aml_append(method, aml_store(aml_int(0), idx)); 1310 1311 while_ctx = aml_while(aml_lless(idx, len)); 1312 aml_append(while_ctx, 1313 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1314 aml_append(while_ctx, aml_increment(idx)); 1315 aml_append(method, while_ctx); 1316 1317 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1318 aml_append(scope, method); 1319 1320 aml_append(table, scope); 1321 } 1322 1323 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1324 { 1325 Aml *dev; 1326 Aml *crs; 1327 Aml *method; 1328 uint32_t irqs[] = {5, 10, 11}; 1329 1330 dev = aml_device("%s", name); 1331 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1332 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1333 1334 crs = aml_resource_template(); 1335 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1336 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1337 aml_append(dev, aml_name_decl("_PRS", crs)); 1338 1339 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1340 aml_append(method, aml_return(aml_call1("IQST", reg))); 1341 aml_append(dev, method); 1342 1343 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1344 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1345 aml_append(dev, method); 1346 1347 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1348 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1349 aml_append(dev, method); 1350 1351 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1352 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1353 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1354 aml_append(dev, method); 1355 1356 return dev; 1357 } 1358 1359 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1360 { 1361 Aml *dev; 1362 Aml *crs; 1363 Aml *method; 1364 uint32_t irqs; 1365 1366 dev = aml_device("%s", name); 1367 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1368 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1369 1370 crs = aml_resource_template(); 1371 irqs = gsi; 1372 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1373 AML_SHARED, &irqs, 1)); 1374 aml_append(dev, aml_name_decl("_PRS", crs)); 1375 1376 aml_append(dev, aml_name_decl("_CRS", crs)); 1377 1378 /* 1379 * _DIS can be no-op because the interrupt cannot be disabled. 1380 */ 1381 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1382 aml_append(dev, method); 1383 1384 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1385 aml_append(dev, method); 1386 1387 return dev; 1388 } 1389 1390 /* _CRS method - get current settings */ 1391 static Aml *build_iqcr_method(bool is_piix4) 1392 { 1393 Aml *if_ctx; 1394 uint32_t irqs; 1395 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1396 Aml *crs = aml_resource_template(); 1397 1398 irqs = 0; 1399 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1400 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1401 aml_append(method, aml_name_decl("PRR0", crs)); 1402 1403 aml_append(method, 1404 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1405 1406 if (is_piix4) { 1407 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1408 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1409 aml_append(method, if_ctx); 1410 } else { 1411 aml_append(method, 1412 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1413 aml_name("PRRI"))); 1414 } 1415 1416 aml_append(method, aml_return(aml_name("PRR0"))); 1417 return method; 1418 } 1419 1420 /* _STA method - get status */ 1421 static Aml *build_irq_status_method(void) 1422 { 1423 Aml *if_ctx; 1424 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1425 1426 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1427 aml_append(if_ctx, aml_return(aml_int(0x09))); 1428 aml_append(method, if_ctx); 1429 aml_append(method, aml_return(aml_int(0x0B))); 1430 return method; 1431 } 1432 1433 static void build_piix4_pci0_int(Aml *table) 1434 { 1435 Aml *dev; 1436 Aml *crs; 1437 Aml *field; 1438 Aml *method; 1439 uint32_t irqs; 1440 Aml *sb_scope = aml_scope("_SB"); 1441 Aml *pci0_scope = aml_scope("PCI0"); 1442 1443 aml_append(pci0_scope, build_prt(true)); 1444 aml_append(sb_scope, pci0_scope); 1445 1446 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1447 aml_append(field, aml_named_field("PRQ0", 8)); 1448 aml_append(field, aml_named_field("PRQ1", 8)); 1449 aml_append(field, aml_named_field("PRQ2", 8)); 1450 aml_append(field, aml_named_field("PRQ3", 8)); 1451 aml_append(sb_scope, field); 1452 1453 aml_append(sb_scope, build_irq_status_method()); 1454 aml_append(sb_scope, build_iqcr_method(true)); 1455 1456 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1457 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1458 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1459 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1460 1461 dev = aml_device("LNKS"); 1462 { 1463 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1464 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1465 1466 crs = aml_resource_template(); 1467 irqs = 9; 1468 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1469 AML_ACTIVE_HIGH, AML_SHARED, 1470 &irqs, 1)); 1471 aml_append(dev, aml_name_decl("_PRS", crs)); 1472 1473 /* The SCI cannot be disabled and is always attached to GSI 9, 1474 * so these are no-ops. We only need this link to override the 1475 * polarity to active high and match the content of the MADT. 1476 */ 1477 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1478 aml_append(method, aml_return(aml_int(0x0b))); 1479 aml_append(dev, method); 1480 1481 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1482 aml_append(dev, method); 1483 1484 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1485 aml_append(method, aml_return(aml_name("_PRS"))); 1486 aml_append(dev, method); 1487 1488 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1489 aml_append(dev, method); 1490 } 1491 aml_append(sb_scope, dev); 1492 1493 aml_append(table, sb_scope); 1494 } 1495 1496 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1497 { 1498 int i; 1499 int head; 1500 Aml *pkg; 1501 char base = name[3] < 'E' ? 'A' : 'E'; 1502 char *s = g_strdup(name); 1503 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1504 1505 assert(strlen(s) == 4); 1506 1507 head = name[3] - base; 1508 for (i = 0; i < 4; i++) { 1509 if (head + i > 3) { 1510 head = i * -1; 1511 } 1512 s[3] = base + head + i; 1513 pkg = aml_package(4); 1514 aml_append(pkg, a_nr); 1515 aml_append(pkg, aml_int(i)); 1516 aml_append(pkg, aml_name("%s", s)); 1517 aml_append(pkg, aml_int(0)); 1518 aml_append(ctx, pkg); 1519 } 1520 g_free(s); 1521 } 1522 1523 static Aml *build_q35_routing_table(const char *str) 1524 { 1525 int i; 1526 Aml *pkg; 1527 char *name = g_strdup_printf("%s ", str); 1528 1529 pkg = aml_package(128); 1530 for (i = 0; i < 0x18; i++) { 1531 name[3] = 'E' + (i & 0x3); 1532 append_q35_prt_entry(pkg, i, name); 1533 } 1534 1535 name[3] = 'E'; 1536 append_q35_prt_entry(pkg, 0x18, name); 1537 1538 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1539 for (i = 0x0019; i < 0x1e; i++) { 1540 name[3] = 'A'; 1541 append_q35_prt_entry(pkg, i, name); 1542 } 1543 1544 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1545 name[3] = 'E'; 1546 append_q35_prt_entry(pkg, 0x1e, name); 1547 name[3] = 'A'; 1548 append_q35_prt_entry(pkg, 0x1f, name); 1549 1550 g_free(name); 1551 return pkg; 1552 } 1553 1554 static void build_q35_pci0_int(Aml *table) 1555 { 1556 Aml *field; 1557 Aml *method; 1558 Aml *sb_scope = aml_scope("_SB"); 1559 Aml *pci0_scope = aml_scope("PCI0"); 1560 1561 /* Zero => PIC mode, One => APIC Mode */ 1562 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1563 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1564 { 1565 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1566 } 1567 aml_append(table, method); 1568 1569 aml_append(pci0_scope, 1570 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1571 aml_append(pci0_scope, 1572 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1573 1574 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1575 { 1576 Aml *if_ctx; 1577 Aml *else_ctx; 1578 1579 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1580 section 6.2.8.1 */ 1581 /* Note: we provide the same info as the PCI routing 1582 table of the Bochs BIOS */ 1583 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1584 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1585 aml_append(method, if_ctx); 1586 else_ctx = aml_else(); 1587 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1588 aml_append(method, else_ctx); 1589 } 1590 aml_append(pci0_scope, method); 1591 aml_append(sb_scope, pci0_scope); 1592 1593 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1594 aml_append(field, aml_named_field("PRQA", 8)); 1595 aml_append(field, aml_named_field("PRQB", 8)); 1596 aml_append(field, aml_named_field("PRQC", 8)); 1597 aml_append(field, aml_named_field("PRQD", 8)); 1598 aml_append(field, aml_reserved_field(0x20)); 1599 aml_append(field, aml_named_field("PRQE", 8)); 1600 aml_append(field, aml_named_field("PRQF", 8)); 1601 aml_append(field, aml_named_field("PRQG", 8)); 1602 aml_append(field, aml_named_field("PRQH", 8)); 1603 aml_append(sb_scope, field); 1604 1605 aml_append(sb_scope, build_irq_status_method()); 1606 aml_append(sb_scope, build_iqcr_method(false)); 1607 1608 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1609 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1610 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1611 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1612 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1613 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1614 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1615 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1616 1617 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1618 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1619 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1620 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1621 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1622 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1623 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1624 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1625 1626 aml_append(table, sb_scope); 1627 } 1628 1629 static void build_q35_isa_bridge(Aml *table) 1630 { 1631 Aml *dev; 1632 Aml *scope; 1633 Aml *field; 1634 1635 scope = aml_scope("_SB.PCI0"); 1636 dev = aml_device("ISA"); 1637 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1638 1639 /* ICH9 PCI to ISA irq remapping */ 1640 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1641 aml_int(0x60), 0x0C)); 1642 1643 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1644 aml_int(0x80), 0x02)); 1645 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1646 aml_append(field, aml_named_field("COMA", 3)); 1647 aml_append(field, aml_reserved_field(1)); 1648 aml_append(field, aml_named_field("COMB", 3)); 1649 aml_append(field, aml_reserved_field(1)); 1650 aml_append(field, aml_named_field("LPTD", 2)); 1651 aml_append(dev, field); 1652 1653 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1654 aml_int(0x82), 0x02)); 1655 /* enable bits */ 1656 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1657 aml_append(field, aml_named_field("CAEN", 1)); 1658 aml_append(field, aml_named_field("CBEN", 1)); 1659 aml_append(field, aml_named_field("LPEN", 1)); 1660 aml_append(dev, field); 1661 1662 aml_append(scope, dev); 1663 aml_append(table, scope); 1664 } 1665 1666 static void build_piix4_pm(Aml *table) 1667 { 1668 Aml *dev; 1669 Aml *scope; 1670 1671 scope = aml_scope("_SB.PCI0"); 1672 dev = aml_device("PX13"); 1673 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1674 1675 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1676 aml_int(0x00), 0xff)); 1677 aml_append(scope, dev); 1678 aml_append(table, scope); 1679 } 1680 1681 static void build_piix4_isa_bridge(Aml *table) 1682 { 1683 Aml *dev; 1684 Aml *scope; 1685 Aml *field; 1686 1687 scope = aml_scope("_SB.PCI0"); 1688 dev = aml_device("ISA"); 1689 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1690 1691 /* PIIX PCI to ISA irq remapping */ 1692 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1693 aml_int(0x60), 0x04)); 1694 /* enable bits */ 1695 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1696 /* Offset(0x5f),, 7, */ 1697 aml_append(field, aml_reserved_field(0x2f8)); 1698 aml_append(field, aml_reserved_field(7)); 1699 aml_append(field, aml_named_field("LPEN", 1)); 1700 /* Offset(0x67),, 3, */ 1701 aml_append(field, aml_reserved_field(0x38)); 1702 aml_append(field, aml_reserved_field(3)); 1703 aml_append(field, aml_named_field("CAEN", 1)); 1704 aml_append(field, aml_reserved_field(3)); 1705 aml_append(field, aml_named_field("CBEN", 1)); 1706 aml_append(dev, field); 1707 1708 aml_append(scope, dev); 1709 aml_append(table, scope); 1710 } 1711 1712 static void build_piix4_pci_hotplug(Aml *table) 1713 { 1714 Aml *scope; 1715 Aml *field; 1716 Aml *method; 1717 1718 scope = aml_scope("_SB.PCI0"); 1719 1720 aml_append(scope, 1721 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1722 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1723 aml_append(field, aml_named_field("PCIU", 32)); 1724 aml_append(field, aml_named_field("PCID", 32)); 1725 aml_append(scope, field); 1726 1727 aml_append(scope, 1728 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1729 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1730 aml_append(field, aml_named_field("B0EJ", 32)); 1731 aml_append(scope, field); 1732 1733 aml_append(scope, 1734 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1735 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1736 aml_append(field, aml_named_field("BNUM", 32)); 1737 aml_append(scope, field); 1738 1739 aml_append(scope, aml_mutex("BLCK", 0)); 1740 1741 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1742 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1743 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1744 aml_append(method, 1745 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1746 aml_append(method, aml_release(aml_name("BLCK"))); 1747 aml_append(method, aml_return(aml_int(0))); 1748 aml_append(scope, method); 1749 1750 aml_append(table, scope); 1751 } 1752 1753 static Aml *build_q35_osc_method(void) 1754 { 1755 Aml *if_ctx; 1756 Aml *if_ctx2; 1757 Aml *else_ctx; 1758 Aml *method; 1759 Aml *a_cwd1 = aml_name("CDW1"); 1760 Aml *a_ctrl = aml_local(0); 1761 1762 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1763 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1764 1765 if_ctx = aml_if(aml_equal( 1766 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1767 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1768 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1769 1770 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1771 1772 /* 1773 * Always allow native PME, AER (no dependencies) 1774 * Allow SHPC (PCI bridges can have SHPC controller) 1775 */ 1776 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1777 1778 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1779 /* Unknown revision */ 1780 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1781 aml_append(if_ctx, if_ctx2); 1782 1783 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1784 /* Capabilities bits were masked */ 1785 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1786 aml_append(if_ctx, if_ctx2); 1787 1788 /* Update DWORD3 in the buffer */ 1789 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1790 aml_append(method, if_ctx); 1791 1792 else_ctx = aml_else(); 1793 /* Unrecognized UUID */ 1794 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1795 aml_append(method, else_ctx); 1796 1797 aml_append(method, aml_return(aml_arg(3))); 1798 return method; 1799 } 1800 1801 static void 1802 build_dsdt(GArray *table_data, BIOSLinker *linker, 1803 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1804 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1805 { 1806 CrsRangeEntry *entry; 1807 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1808 CrsRangeSet crs_range_set; 1809 PCMachineState *pcms = PC_MACHINE(machine); 1810 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1811 AcpiMcfgInfo mcfg; 1812 uint32_t nr_mem = machine->ram_slots; 1813 int root_bus_limit = 0xFF; 1814 PCIBus *bus = NULL; 1815 TPMIf *tpm = tpm_find(); 1816 int i; 1817 1818 dsdt = init_aml_allocator(); 1819 1820 /* Reserve space for header */ 1821 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1822 1823 build_dbg_aml(dsdt); 1824 if (misc->is_piix4) { 1825 sb_scope = aml_scope("_SB"); 1826 dev = aml_device("PCI0"); 1827 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1828 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1829 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1830 aml_append(sb_scope, dev); 1831 aml_append(dsdt, sb_scope); 1832 1833 build_hpet_aml(dsdt); 1834 build_piix4_pm(dsdt); 1835 build_piix4_isa_bridge(dsdt); 1836 build_isa_devices_aml(dsdt); 1837 build_piix4_pci_hotplug(dsdt); 1838 build_piix4_pci0_int(dsdt); 1839 } else { 1840 sb_scope = aml_scope("_SB"); 1841 dev = aml_device("PCI0"); 1842 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1843 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1844 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1845 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1846 aml_append(dev, build_q35_osc_method()); 1847 aml_append(sb_scope, dev); 1848 aml_append(dsdt, sb_scope); 1849 1850 build_hpet_aml(dsdt); 1851 build_q35_isa_bridge(dsdt); 1852 build_isa_devices_aml(dsdt); 1853 build_q35_pci0_int(dsdt); 1854 } 1855 1856 if (pcmc->legacy_cpu_hotplug) { 1857 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1858 } else { 1859 CPUHotplugFeatures opts = { 1860 .acpi_1_compatible = true, .has_legacy_cphp = true 1861 }; 1862 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1863 "\\_SB.PCI0", "\\_GPE._E02"); 1864 } 1865 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03"); 1866 1867 scope = aml_scope("_GPE"); 1868 { 1869 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1870 1871 if (misc->is_piix4) { 1872 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1873 aml_append(method, 1874 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1875 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1876 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1877 aml_append(scope, method); 1878 } 1879 1880 if (machine->nvdimms_state->is_enabled) { 1881 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1882 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1883 aml_int(0x80))); 1884 aml_append(scope, method); 1885 } 1886 } 1887 aml_append(dsdt, scope); 1888 1889 crs_range_set_init(&crs_range_set); 1890 bus = PC_MACHINE(machine)->bus; 1891 if (bus) { 1892 QLIST_FOREACH(bus, &bus->child, sibling) { 1893 uint8_t bus_num = pci_bus_num(bus); 1894 uint8_t numa_node = pci_bus_numa_node(bus); 1895 1896 /* look only for expander root buses */ 1897 if (!pci_bus_is_root(bus)) { 1898 continue; 1899 } 1900 1901 if (bus_num < root_bus_limit) { 1902 root_bus_limit = bus_num - 1; 1903 } 1904 1905 scope = aml_scope("\\_SB"); 1906 dev = aml_device("PC%.02X", bus_num); 1907 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1908 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1909 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1910 if (pci_bus_is_express(bus)) { 1911 aml_append(dev, build_q35_osc_method()); 1912 } 1913 1914 if (numa_node != NUMA_NODE_UNASSIGNED) { 1915 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1916 } 1917 1918 aml_append(dev, build_prt(false)); 1919 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1920 aml_append(dev, aml_name_decl("_CRS", crs)); 1921 aml_append(scope, dev); 1922 aml_append(dsdt, scope); 1923 } 1924 } 1925 1926 /* 1927 * At this point crs_range_set has all the ranges used by pci 1928 * busses *other* than PCI0. These ranges will be excluded from 1929 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1930 * too. 1931 */ 1932 if (acpi_get_mcfg(&mcfg)) { 1933 crs_range_insert(crs_range_set.mem_ranges, 1934 mcfg.base, mcfg.base + mcfg.size - 1); 1935 } 1936 1937 scope = aml_scope("\\_SB.PCI0"); 1938 /* build PCI0._CRS */ 1939 crs = aml_resource_template(); 1940 aml_append(crs, 1941 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1942 0x0000, 0x0, root_bus_limit, 1943 0x0000, root_bus_limit + 1)); 1944 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1945 1946 aml_append(crs, 1947 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1948 AML_POS_DECODE, AML_ENTIRE_RANGE, 1949 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1950 1951 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1952 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1953 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1954 aml_append(crs, 1955 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1956 AML_POS_DECODE, AML_ENTIRE_RANGE, 1957 0x0000, entry->base, entry->limit, 1958 0x0000, entry->limit - entry->base + 1)); 1959 } 1960 1961 aml_append(crs, 1962 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1963 AML_CACHEABLE, AML_READ_WRITE, 1964 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1965 1966 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1967 range_lob(pci_hole), 1968 range_upb(pci_hole)); 1969 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1970 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1971 aml_append(crs, 1972 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1973 AML_NON_CACHEABLE, AML_READ_WRITE, 1974 0, entry->base, entry->limit, 1975 0, entry->limit - entry->base + 1)); 1976 } 1977 1978 if (!range_is_empty(pci_hole64)) { 1979 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1980 range_lob(pci_hole64), 1981 range_upb(pci_hole64)); 1982 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1983 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1984 aml_append(crs, 1985 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1986 AML_MAX_FIXED, 1987 AML_CACHEABLE, AML_READ_WRITE, 1988 0, entry->base, entry->limit, 1989 0, entry->limit - entry->base + 1)); 1990 } 1991 } 1992 1993 if (TPM_IS_TIS(tpm_find())) { 1994 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1995 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1996 } 1997 aml_append(scope, aml_name_decl("_CRS", crs)); 1998 1999 /* reserve GPE0 block resources */ 2000 dev = aml_device("GPE0"); 2001 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2002 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 2003 /* device present, functioning, decoding, not shown in UI */ 2004 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2005 crs = aml_resource_template(); 2006 aml_append(crs, 2007 aml_io( 2008 AML_DECODE16, 2009 pm->fadt.gpe0_blk.address, 2010 pm->fadt.gpe0_blk.address, 2011 1, 2012 pm->fadt.gpe0_blk.bit_width / 8) 2013 ); 2014 aml_append(dev, aml_name_decl("_CRS", crs)); 2015 aml_append(scope, dev); 2016 2017 crs_range_set_free(&crs_range_set); 2018 2019 /* reserve PCIHP resources */ 2020 if (pm->pcihp_io_len) { 2021 dev = aml_device("PHPR"); 2022 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2023 aml_append(dev, 2024 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2025 /* device present, functioning, decoding, not shown in UI */ 2026 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2027 crs = aml_resource_template(); 2028 aml_append(crs, 2029 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2030 pm->pcihp_io_len) 2031 ); 2032 aml_append(dev, aml_name_decl("_CRS", crs)); 2033 aml_append(scope, dev); 2034 } 2035 aml_append(dsdt, scope); 2036 2037 /* create S3_ / S4_ / S5_ packages if necessary */ 2038 scope = aml_scope("\\"); 2039 if (!pm->s3_disabled) { 2040 pkg = aml_package(4); 2041 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2042 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2043 aml_append(pkg, aml_int(0)); /* reserved */ 2044 aml_append(pkg, aml_int(0)); /* reserved */ 2045 aml_append(scope, aml_name_decl("_S3", pkg)); 2046 } 2047 2048 if (!pm->s4_disabled) { 2049 pkg = aml_package(4); 2050 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2051 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2052 aml_append(pkg, aml_int(pm->s4_val)); 2053 aml_append(pkg, aml_int(0)); /* reserved */ 2054 aml_append(pkg, aml_int(0)); /* reserved */ 2055 aml_append(scope, aml_name_decl("_S4", pkg)); 2056 } 2057 2058 pkg = aml_package(4); 2059 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2060 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2061 aml_append(pkg, aml_int(0)); /* reserved */ 2062 aml_append(pkg, aml_int(0)); /* reserved */ 2063 aml_append(scope, aml_name_decl("_S5", pkg)); 2064 aml_append(dsdt, scope); 2065 2066 /* create fw_cfg node, unconditionally */ 2067 { 2068 /* when using port i/o, the 8-bit data register *always* overlaps 2069 * with half of the 16-bit control register. Hence, the total size 2070 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2071 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2072 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), 2073 "dma_enabled", NULL) ? 2074 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2075 FW_CFG_CTL_SIZE; 2076 2077 scope = aml_scope("\\_SB.PCI0"); 2078 dev = aml_device("FWCF"); 2079 2080 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2081 2082 /* device present, functioning, decoding, not shown in UI */ 2083 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2084 2085 crs = aml_resource_template(); 2086 aml_append(crs, 2087 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2088 ); 2089 aml_append(dev, aml_name_decl("_CRS", crs)); 2090 2091 aml_append(scope, dev); 2092 aml_append(dsdt, scope); 2093 } 2094 2095 if (misc->applesmc_io_base) { 2096 scope = aml_scope("\\_SB.PCI0.ISA"); 2097 dev = aml_device("SMC"); 2098 2099 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2100 /* device present, functioning, decoding, not shown in UI */ 2101 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2102 2103 crs = aml_resource_template(); 2104 aml_append(crs, 2105 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2106 0x01, APPLESMC_MAX_DATA_LENGTH) 2107 ); 2108 aml_append(crs, aml_irq_no_flags(6)); 2109 aml_append(dev, aml_name_decl("_CRS", crs)); 2110 2111 aml_append(scope, dev); 2112 aml_append(dsdt, scope); 2113 } 2114 2115 if (misc->pvpanic_port) { 2116 scope = aml_scope("\\_SB.PCI0.ISA"); 2117 2118 dev = aml_device("PEVT"); 2119 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2120 2121 crs = aml_resource_template(); 2122 aml_append(crs, 2123 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2124 ); 2125 aml_append(dev, aml_name_decl("_CRS", crs)); 2126 2127 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2128 aml_int(misc->pvpanic_port), 1)); 2129 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2130 aml_append(field, aml_named_field("PEPT", 8)); 2131 aml_append(dev, field); 2132 2133 /* device present, functioning, decoding, shown in UI */ 2134 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2135 2136 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2137 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2138 aml_append(method, aml_return(aml_local(0))); 2139 aml_append(dev, method); 2140 2141 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2142 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2143 aml_append(dev, method); 2144 2145 aml_append(scope, dev); 2146 aml_append(dsdt, scope); 2147 } 2148 2149 sb_scope = aml_scope("\\_SB"); 2150 { 2151 Object *pci_host; 2152 PCIBus *bus = NULL; 2153 2154 pci_host = acpi_get_i386_pci_host(); 2155 if (pci_host) { 2156 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2157 } 2158 2159 if (bus) { 2160 Aml *scope = aml_scope("PCI0"); 2161 /* Scan all PCI buses. Generate tables to support hotplug. */ 2162 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2163 2164 if (TPM_IS_TIS(tpm)) { 2165 if (misc->tpm_version == TPM_VERSION_2_0) { 2166 dev = aml_device("TPM"); 2167 aml_append(dev, aml_name_decl("_HID", 2168 aml_string("MSFT0101"))); 2169 } else { 2170 dev = aml_device("ISA.TPM"); 2171 aml_append(dev, aml_name_decl("_HID", 2172 aml_eisaid("PNP0C31"))); 2173 } 2174 2175 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2176 crs = aml_resource_template(); 2177 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2178 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2179 /* 2180 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 2181 Rewrite to take IRQ from TPM device model and 2182 fix default IRQ value there to use some unused IRQ 2183 */ 2184 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 2185 aml_append(dev, aml_name_decl("_CRS", crs)); 2186 2187 tpm_build_ppi_acpi(tpm, dev); 2188 2189 aml_append(scope, dev); 2190 } 2191 2192 aml_append(sb_scope, scope); 2193 } 2194 } 2195 2196 if (TPM_IS_CRB(tpm)) { 2197 dev = aml_device("TPM"); 2198 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 2199 crs = aml_resource_template(); 2200 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 2201 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 2202 aml_append(dev, aml_name_decl("_CRS", crs)); 2203 2204 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 2205 aml_append(method, aml_return(aml_int(0x0f))); 2206 aml_append(dev, method); 2207 2208 tpm_build_ppi_acpi(tpm, dev); 2209 2210 aml_append(sb_scope, dev); 2211 } 2212 2213 aml_append(dsdt, sb_scope); 2214 2215 /* copy AML table into ACPI tables blob and patch header there */ 2216 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2217 build_header(linker, table_data, 2218 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2219 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2220 free_aml_allocator(); 2221 } 2222 2223 static void 2224 build_hpet(GArray *table_data, BIOSLinker *linker) 2225 { 2226 Acpi20Hpet *hpet; 2227 2228 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2229 /* Note timer_block_id value must be kept in sync with value advertised by 2230 * emulated hpet 2231 */ 2232 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2233 hpet->addr.address = cpu_to_le64(HPET_BASE); 2234 build_header(linker, table_data, 2235 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2236 } 2237 2238 static void 2239 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2240 { 2241 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2242 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 2243 unsigned log_addr_offset = 2244 (char *)&tcpa->log_area_start_address - table_data->data; 2245 2246 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2247 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2248 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 2249 2250 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 2251 false /* high memory */); 2252 2253 /* log area start address to be filled by Guest linker */ 2254 bios_linker_loader_add_pointer(linker, 2255 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 2256 ACPI_BUILD_TPMLOG_FILE, 0); 2257 2258 build_header(linker, table_data, 2259 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2260 } 2261 2262 static void 2263 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2264 { 2265 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2266 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address); 2267 unsigned log_addr_offset = 2268 (char *)&tpm2_ptr->log_area_start_address - table_data->data; 2269 2270 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2271 if (TPM_IS_TIS(tpm_find())) { 2272 tpm2_ptr->control_area_address = cpu_to_le64(0); 2273 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2274 } else if (TPM_IS_CRB(tpm_find())) { 2275 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL); 2276 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB); 2277 } else { 2278 g_warn_if_reached(); 2279 } 2280 2281 tpm2_ptr->log_area_minimum_length = 2282 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2283 2284 /* log area start address to be filled by Guest linker */ 2285 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2286 log_addr_offset, log_addr_size, 2287 ACPI_BUILD_TPMLOG_FILE, 0); 2288 build_header(linker, table_data, 2289 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2290 } 2291 2292 #define HOLE_640K_START (640 * KiB) 2293 #define HOLE_640K_END (1 * MiB) 2294 2295 static void 2296 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2297 { 2298 AcpiSystemResourceAffinityTable *srat; 2299 AcpiSratMemoryAffinity *numamem; 2300 2301 int i; 2302 int srat_start, numa_start, slots; 2303 uint64_t mem_len, mem_base, next_base; 2304 MachineClass *mc = MACHINE_GET_CLASS(machine); 2305 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2306 PCMachineState *pcms = PC_MACHINE(machine); 2307 ram_addr_t hotplugabble_address_space_size = 2308 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 2309 NULL); 2310 2311 srat_start = table_data->len; 2312 2313 srat = acpi_data_push(table_data, sizeof *srat); 2314 srat->reserved1 = cpu_to_le32(1); 2315 2316 for (i = 0; i < apic_ids->len; i++) { 2317 int node_id = apic_ids->cpus[i].props.node_id; 2318 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2319 2320 if (apic_id < 255) { 2321 AcpiSratProcessorAffinity *core; 2322 2323 core = acpi_data_push(table_data, sizeof *core); 2324 core->type = ACPI_SRAT_PROCESSOR_APIC; 2325 core->length = sizeof(*core); 2326 core->local_apic_id = apic_id; 2327 core->proximity_lo = node_id; 2328 memset(core->proximity_hi, 0, 3); 2329 core->local_sapic_eid = 0; 2330 core->flags = cpu_to_le32(1); 2331 } else { 2332 AcpiSratProcessorX2ApicAffinity *core; 2333 2334 core = acpi_data_push(table_data, sizeof *core); 2335 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2336 core->length = sizeof(*core); 2337 core->x2apic_id = cpu_to_le32(apic_id); 2338 core->proximity_domain = cpu_to_le32(node_id); 2339 core->flags = cpu_to_le32(1); 2340 } 2341 } 2342 2343 2344 /* the memory map is a bit tricky, it contains at least one hole 2345 * from 640k-1M and possibly another one from 3.5G-4G. 2346 */ 2347 next_base = 0; 2348 numa_start = table_data->len; 2349 2350 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2351 mem_base = next_base; 2352 mem_len = pcms->node_mem[i - 1]; 2353 next_base = mem_base + mem_len; 2354 2355 /* Cut out the 640K hole */ 2356 if (mem_base <= HOLE_640K_START && 2357 next_base > HOLE_640K_START) { 2358 mem_len -= next_base - HOLE_640K_START; 2359 if (mem_len > 0) { 2360 numamem = acpi_data_push(table_data, sizeof *numamem); 2361 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2362 MEM_AFFINITY_ENABLED); 2363 } 2364 2365 /* Check for the rare case: 640K < RAM < 1M */ 2366 if (next_base <= HOLE_640K_END) { 2367 next_base = HOLE_640K_END; 2368 continue; 2369 } 2370 mem_base = HOLE_640K_END; 2371 mem_len = next_base - HOLE_640K_END; 2372 } 2373 2374 /* Cut out the ACPI_PCI hole */ 2375 if (mem_base <= pcms->below_4g_mem_size && 2376 next_base > pcms->below_4g_mem_size) { 2377 mem_len -= next_base - pcms->below_4g_mem_size; 2378 if (mem_len > 0) { 2379 numamem = acpi_data_push(table_data, sizeof *numamem); 2380 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2381 MEM_AFFINITY_ENABLED); 2382 } 2383 mem_base = 1ULL << 32; 2384 mem_len = next_base - pcms->below_4g_mem_size; 2385 next_base = mem_base + mem_len; 2386 } 2387 2388 if (mem_len > 0) { 2389 numamem = acpi_data_push(table_data, sizeof *numamem); 2390 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2391 MEM_AFFINITY_ENABLED); 2392 } 2393 } 2394 slots = (table_data->len - numa_start) / sizeof *numamem; 2395 for (; slots < pcms->numa_nodes + 2; slots++) { 2396 numamem = acpi_data_push(table_data, sizeof *numamem); 2397 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2398 } 2399 2400 /* 2401 * Entry is required for Windows to enable memory hotplug in OS 2402 * and for Linux to enable SWIOTLB when booted with less than 2403 * 4G of RAM. Windows works better if the entry sets proximity 2404 * to the highest NUMA node in the machine. 2405 * Memory devices may override proximity set by this entry, 2406 * providing _PXM method if necessary. 2407 */ 2408 if (hotplugabble_address_space_size) { 2409 numamem = acpi_data_push(table_data, sizeof *numamem); 2410 build_srat_memory(numamem, machine->device_memory->base, 2411 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2412 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2413 } 2414 2415 build_header(linker, table_data, 2416 (void *)(table_data->data + srat_start), 2417 "SRAT", 2418 table_data->len - srat_start, 1, NULL, NULL); 2419 } 2420 2421 /* 2422 * VT-d spec 8.1 DMA Remapping Reporting Structure 2423 * (version Oct. 2014 or later) 2424 */ 2425 static void 2426 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2427 { 2428 int dmar_start = table_data->len; 2429 2430 AcpiTableDmar *dmar; 2431 AcpiDmarHardwareUnit *drhd; 2432 AcpiDmarRootPortATS *atsr; 2433 uint8_t dmar_flags = 0; 2434 X86IOMMUState *iommu = x86_iommu_get_default(); 2435 AcpiDmarDeviceScope *scope = NULL; 2436 /* Root complex IOAPIC use one path[0] only */ 2437 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2438 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2439 2440 assert(iommu); 2441 if (x86_iommu_ir_supported(iommu)) { 2442 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2443 } 2444 2445 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2446 dmar->host_address_width = intel_iommu->aw_bits - 1; 2447 dmar->flags = dmar_flags; 2448 2449 /* DMAR Remapping Hardware Unit Definition structure */ 2450 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2451 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2452 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2453 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2454 drhd->pci_segment = cpu_to_le16(0); 2455 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2456 2457 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2458 * 8.3.1 (version Oct. 2014 or later). */ 2459 scope = &drhd->scope[0]; 2460 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2461 scope->length = ioapic_scope_size; 2462 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2463 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2464 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2465 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2466 2467 if (iommu->dt_supported) { 2468 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2469 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2470 atsr->length = cpu_to_le16(sizeof(*atsr)); 2471 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2472 atsr->pci_segment = cpu_to_le16(0); 2473 } 2474 2475 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2476 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2477 } 2478 /* 2479 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2480 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2481 */ 2482 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2483 2484 static void 2485 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2486 { 2487 int ivhd_table_len = 28; 2488 int iommu_start = table_data->len; 2489 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2490 2491 /* IVRS header */ 2492 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2493 /* IVinfo - IO virtualization information common to all 2494 * IOMMU units in a system 2495 */ 2496 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2497 /* reserved */ 2498 build_append_int_noprefix(table_data, 0, 8); 2499 2500 /* IVHD definition - type 10h */ 2501 build_append_int_noprefix(table_data, 0x10, 1); 2502 /* virtualization flags */ 2503 build_append_int_noprefix(table_data, 2504 (1UL << 0) | /* HtTunEn */ 2505 (1UL << 4) | /* iotblSup */ 2506 (1UL << 6) | /* PrefSup */ 2507 (1UL << 7), /* PPRSup */ 2508 1); 2509 2510 /* 2511 * When interrupt remapping is supported, we add a special IVHD device 2512 * for type IO-APIC. 2513 */ 2514 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2515 ivhd_table_len += 8; 2516 } 2517 /* IVHD length */ 2518 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2519 /* DeviceID */ 2520 build_append_int_noprefix(table_data, s->devid, 2); 2521 /* Capability offset */ 2522 build_append_int_noprefix(table_data, s->capab_offset, 2); 2523 /* IOMMU base address */ 2524 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2525 /* PCI Segment Group */ 2526 build_append_int_noprefix(table_data, 0, 2); 2527 /* IOMMU info */ 2528 build_append_int_noprefix(table_data, 0, 2); 2529 /* IOMMU Feature Reporting */ 2530 build_append_int_noprefix(table_data, 2531 (48UL << 30) | /* HATS */ 2532 (48UL << 28) | /* GATS */ 2533 (1UL << 2) | /* GTSup */ 2534 (1UL << 6), /* GASup */ 2535 4); 2536 /* 2537 * Type 1 device entry reporting all devices 2538 * These are 4-byte device entries currently reporting the range of 2539 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2540 */ 2541 build_append_int_noprefix(table_data, 0x0000001, 4); 2542 2543 /* 2544 * Add a special IVHD device type. 2545 * Refer to spec - Table 95: IVHD device entry type codes 2546 * 2547 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2548 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2549 */ 2550 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2551 build_append_int_noprefix(table_data, 2552 (0x1ull << 56) | /* type IOAPIC */ 2553 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2554 0x48, /* special device */ 2555 8); 2556 } 2557 2558 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2559 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2560 } 2561 2562 typedef 2563 struct AcpiBuildState { 2564 /* Copy of table in RAM (for patching). */ 2565 MemoryRegion *table_mr; 2566 /* Is table patched? */ 2567 uint8_t patched; 2568 void *rsdp; 2569 MemoryRegion *rsdp_mr; 2570 MemoryRegion *linker_mr; 2571 } AcpiBuildState; 2572 2573 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2574 { 2575 Object *pci_host; 2576 QObject *o; 2577 2578 pci_host = acpi_get_i386_pci_host(); 2579 g_assert(pci_host); 2580 2581 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2582 if (!o) { 2583 return false; 2584 } 2585 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2586 qobject_unref(o); 2587 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2588 return false; 2589 } 2590 2591 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2592 assert(o); 2593 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2594 qobject_unref(o); 2595 return true; 2596 } 2597 2598 static 2599 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2600 { 2601 PCMachineState *pcms = PC_MACHINE(machine); 2602 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2603 GArray *table_offsets; 2604 unsigned facs, dsdt, rsdt, fadt; 2605 AcpiPmInfo pm; 2606 AcpiMiscInfo misc; 2607 AcpiMcfgInfo mcfg; 2608 Range pci_hole, pci_hole64; 2609 uint8_t *u; 2610 size_t aml_len = 0; 2611 GArray *tables_blob = tables->table_data; 2612 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2613 Object *vmgenid_dev; 2614 2615 acpi_get_pm_info(&pm); 2616 acpi_get_misc_info(&misc); 2617 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2618 acpi_get_slic_oem(&slic_oem); 2619 2620 table_offsets = g_array_new(false, true /* clear */, 2621 sizeof(uint32_t)); 2622 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2623 2624 bios_linker_loader_alloc(tables->linker, 2625 ACPI_BUILD_TABLE_FILE, tables_blob, 2626 64 /* Ensure FACS is aligned */, 2627 false /* high memory */); 2628 2629 /* 2630 * FACS is pointed to by FADT. 2631 * We place it first since it's the only table that has alignment 2632 * requirements. 2633 */ 2634 facs = tables_blob->len; 2635 build_facs(tables_blob); 2636 2637 /* DSDT is pointed to by FADT */ 2638 dsdt = tables_blob->len; 2639 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2640 &pci_hole, &pci_hole64, machine); 2641 2642 /* Count the size of the DSDT and SSDT, we will need it for legacy 2643 * sizing of ACPI tables. 2644 */ 2645 aml_len += tables_blob->len - dsdt; 2646 2647 /* ACPI tables pointed to by RSDT */ 2648 fadt = tables_blob->len; 2649 acpi_add_table(table_offsets, tables_blob); 2650 pm.fadt.facs_tbl_offset = &facs; 2651 pm.fadt.dsdt_tbl_offset = &dsdt; 2652 pm.fadt.xdsdt_tbl_offset = &dsdt; 2653 build_fadt(tables_blob, tables->linker, &pm.fadt, 2654 slic_oem.id, slic_oem.table_id); 2655 aml_len += tables_blob->len - fadt; 2656 2657 acpi_add_table(table_offsets, tables_blob); 2658 build_madt(tables_blob, tables->linker, pcms); 2659 2660 vmgenid_dev = find_vmgenid_dev(); 2661 if (vmgenid_dev) { 2662 acpi_add_table(table_offsets, tables_blob); 2663 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2664 tables->vmgenid, tables->linker); 2665 } 2666 2667 if (misc.has_hpet) { 2668 acpi_add_table(table_offsets, tables_blob); 2669 build_hpet(tables_blob, tables->linker); 2670 } 2671 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2672 acpi_add_table(table_offsets, tables_blob); 2673 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2674 2675 if (misc.tpm_version == TPM_VERSION_2_0) { 2676 acpi_add_table(table_offsets, tables_blob); 2677 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2678 } 2679 } 2680 if (pcms->numa_nodes) { 2681 acpi_add_table(table_offsets, tables_blob); 2682 build_srat(tables_blob, tables->linker, machine); 2683 if (have_numa_distance) { 2684 acpi_add_table(table_offsets, tables_blob); 2685 build_slit(tables_blob, tables->linker); 2686 } 2687 } 2688 if (acpi_get_mcfg(&mcfg)) { 2689 acpi_add_table(table_offsets, tables_blob); 2690 build_mcfg(tables_blob, tables->linker, &mcfg); 2691 } 2692 if (x86_iommu_get_default()) { 2693 IommuType IOMMUType = x86_iommu_get_type(); 2694 if (IOMMUType == TYPE_AMD) { 2695 acpi_add_table(table_offsets, tables_blob); 2696 build_amd_iommu(tables_blob, tables->linker); 2697 } else if (IOMMUType == TYPE_INTEL) { 2698 acpi_add_table(table_offsets, tables_blob); 2699 build_dmar_q35(tables_blob, tables->linker); 2700 } 2701 } 2702 if (machine->nvdimms_state->is_enabled) { 2703 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2704 machine->nvdimms_state, machine->ram_slots); 2705 } 2706 2707 /* Add tables supplied by user (if any) */ 2708 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2709 unsigned len = acpi_table_len(u); 2710 2711 acpi_add_table(table_offsets, tables_blob); 2712 g_array_append_vals(tables_blob, u, len); 2713 } 2714 2715 /* RSDT is pointed to by RSDP */ 2716 rsdt = tables_blob->len; 2717 build_rsdt(tables_blob, tables->linker, table_offsets, 2718 slic_oem.id, slic_oem.table_id); 2719 2720 /* RSDP is in FSEG memory, so allocate it separately */ 2721 { 2722 AcpiRsdpData rsdp_data = { 2723 .revision = 0, 2724 .oem_id = ACPI_BUILD_APPNAME6, 2725 .xsdt_tbl_offset = NULL, 2726 .rsdt_tbl_offset = &rsdt, 2727 }; 2728 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2729 if (!pcmc->rsdp_in_ram) { 2730 /* We used to allocate some extra space for RSDP revision 2 but 2731 * only used the RSDP revision 0 space. The extra bytes were 2732 * zeroed out and not used. 2733 * Here we continue wasting those extra 16 bytes to make sure we 2734 * don't break migration for machine types 2.2 and older due to 2735 * RSDP blob size mismatch. 2736 */ 2737 build_append_int_noprefix(tables->rsdp, 0, 16); 2738 } 2739 } 2740 2741 /* We'll expose it all to Guest so we want to reduce 2742 * chance of size changes. 2743 * 2744 * We used to align the tables to 4k, but of course this would 2745 * too simple to be enough. 4k turned out to be too small an 2746 * alignment very soon, and in fact it is almost impossible to 2747 * keep the table size stable for all (max_cpus, max_memory_slots) 2748 * combinations. So the table size is always 64k for pc-i440fx-2.1 2749 * and we give an error if the table grows beyond that limit. 2750 * 2751 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2752 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2753 * than 2.0 and we can always pad the smaller tables with zeros. We can 2754 * then use the exact size of the 2.0 tables. 2755 * 2756 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2757 */ 2758 if (pcmc->legacy_acpi_table_size) { 2759 /* Subtracting aml_len gives the size of fixed tables. Then add the 2760 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2761 */ 2762 int legacy_aml_len = 2763 pcmc->legacy_acpi_table_size + 2764 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit; 2765 int legacy_table_size = 2766 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2767 ACPI_BUILD_ALIGN_SIZE); 2768 if (tables_blob->len > legacy_table_size) { 2769 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2770 warn_report("ACPI table size %u exceeds %d bytes," 2771 " migration may not work", 2772 tables_blob->len, legacy_table_size); 2773 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2774 " or PCI bridges."); 2775 } 2776 g_array_set_size(tables_blob, legacy_table_size); 2777 } else { 2778 /* Make sure we have a buffer in case we need to resize the tables. */ 2779 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2780 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2781 warn_report("ACPI table size %u exceeds %d bytes," 2782 " migration may not work", 2783 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2784 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2785 " or PCI bridges."); 2786 } 2787 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2788 } 2789 2790 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2791 2792 /* Cleanup memory that's no longer used. */ 2793 g_array_free(table_offsets, true); 2794 } 2795 2796 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2797 { 2798 uint32_t size = acpi_data_len(data); 2799 2800 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2801 memory_region_ram_resize(mr, size, &error_abort); 2802 2803 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2804 memory_region_set_dirty(mr, 0, size); 2805 } 2806 2807 static void acpi_build_update(void *build_opaque) 2808 { 2809 AcpiBuildState *build_state = build_opaque; 2810 AcpiBuildTables tables; 2811 2812 /* No state to update or already patched? Nothing to do. */ 2813 if (!build_state || build_state->patched) { 2814 return; 2815 } 2816 build_state->patched = 1; 2817 2818 acpi_build_tables_init(&tables); 2819 2820 acpi_build(&tables, MACHINE(qdev_get_machine())); 2821 2822 acpi_ram_update(build_state->table_mr, tables.table_data); 2823 2824 if (build_state->rsdp) { 2825 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2826 } else { 2827 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2828 } 2829 2830 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2831 acpi_build_tables_cleanup(&tables, true); 2832 } 2833 2834 static void acpi_build_reset(void *build_opaque) 2835 { 2836 AcpiBuildState *build_state = build_opaque; 2837 build_state->patched = 0; 2838 } 2839 2840 static const VMStateDescription vmstate_acpi_build = { 2841 .name = "acpi_build", 2842 .version_id = 1, 2843 .minimum_version_id = 1, 2844 .fields = (VMStateField[]) { 2845 VMSTATE_UINT8(patched, AcpiBuildState), 2846 VMSTATE_END_OF_LIST() 2847 }, 2848 }; 2849 2850 void acpi_setup(void) 2851 { 2852 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2853 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2854 AcpiBuildTables tables; 2855 AcpiBuildState *build_state; 2856 Object *vmgenid_dev; 2857 TPMIf *tpm; 2858 static FwCfgTPMConfig tpm_config; 2859 2860 if (!pcms->fw_cfg) { 2861 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2862 return; 2863 } 2864 2865 if (!pcms->acpi_build_enabled) { 2866 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2867 return; 2868 } 2869 2870 if (!acpi_enabled) { 2871 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2872 return; 2873 } 2874 2875 build_state = g_malloc0(sizeof *build_state); 2876 2877 acpi_build_tables_init(&tables); 2878 acpi_build(&tables, MACHINE(pcms)); 2879 2880 /* Now expose it all to Guest */ 2881 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2882 build_state, tables.table_data, 2883 ACPI_BUILD_TABLE_FILE, 2884 ACPI_BUILD_TABLE_MAX_SIZE); 2885 assert(build_state->table_mr != NULL); 2886 2887 build_state->linker_mr = 2888 acpi_add_rom_blob(acpi_build_update, build_state, 2889 tables.linker->cmd_blob, "etc/table-loader", 0); 2890 2891 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2892 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2893 2894 tpm = tpm_find(); 2895 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2896 tpm_config = (FwCfgTPMConfig) { 2897 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2898 .tpm_version = tpm_get_version(tpm), 2899 .tpmppi_version = TPM_PPI_VERSION_1_30 2900 }; 2901 fw_cfg_add_file(pcms->fw_cfg, "etc/tpm/config", 2902 &tpm_config, sizeof tpm_config); 2903 } 2904 2905 vmgenid_dev = find_vmgenid_dev(); 2906 if (vmgenid_dev) { 2907 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg, 2908 tables.vmgenid); 2909 } 2910 2911 if (!pcmc->rsdp_in_ram) { 2912 /* 2913 * Keep for compatibility with old machine types. 2914 * Though RSDP is small, its contents isn't immutable, so 2915 * we'll update it along with the rest of tables on guest access. 2916 */ 2917 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2918 2919 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2920 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2921 acpi_build_update, NULL, build_state, 2922 build_state->rsdp, rsdp_size, true); 2923 build_state->rsdp_mr = NULL; 2924 } else { 2925 build_state->rsdp = NULL; 2926 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2927 build_state, tables.rsdp, 2928 ACPI_BUILD_RSDP_FILE, 0); 2929 } 2930 2931 qemu_register_reset(acpi_build_reset, build_state); 2932 acpi_build_reset(build_state); 2933 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2934 2935 /* Cleanup tables but don't free the memory: we track it 2936 * in build_state. 2937 */ 2938 acpi_build_tables_cleanup(&tables, false); 2939 } 2940