1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/core/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/boards.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/rtc/mc146818rtc_regs.h" 49 #include "migration/vmstate.h" 50 #include "hw/mem/memory-device.h" 51 #include "hw/mem/nvdimm.h" 52 #include "sysemu/numa.h" 53 #include "sysemu/reset.h" 54 #include "hw/hyperv/vmbus-bridge.h" 55 56 /* Supported chipsets: */ 57 #include "hw/southbridge/piix.h" 58 #include "hw/acpi/pcihp.h" 59 #include "hw/i386/fw_cfg.h" 60 #include "hw/i386/ich9.h" 61 #include "hw/pci/pci_bus.h" 62 #include "hw/pci-host/q35.h" 63 #include "hw/i386/x86-iommu.h" 64 65 #include "hw/acpi/aml-build.h" 66 #include "hw/acpi/utils.h" 67 #include "hw/acpi/pci.h" 68 69 #include "qom/qom-qobject.h" 70 #include "hw/i386/amd_iommu.h" 71 #include "hw/i386/intel_iommu.h" 72 73 #include "hw/acpi/ipmi.h" 74 #include "hw/acpi/hmat.h" 75 76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 78 * a little bit, there should be plenty of free space since the DSDT 79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 80 */ 81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 82 #define ACPI_BUILD_ALIGN_SIZE 0x1000 83 84 #define ACPI_BUILD_TABLE_SIZE 0x20000 85 86 /* #define DEBUG_ACPI_BUILD */ 87 #ifdef DEBUG_ACPI_BUILD 88 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 90 #else 91 #define ACPI_BUILD_DPRINTF(fmt, ...) 92 #endif 93 94 typedef struct AcpiPmInfo { 95 bool s3_disabled; 96 bool s4_disabled; 97 bool pcihp_bridge_en; 98 bool smi_on_cpuhp; 99 uint8_t s4_val; 100 AcpiFadtData fadt; 101 uint16_t cpu_hp_io_base; 102 uint16_t pcihp_io_base; 103 uint16_t pcihp_io_len; 104 } AcpiPmInfo; 105 106 typedef struct AcpiMiscInfo { 107 bool is_piix4; 108 bool has_hpet; 109 TPMVersion tpm_version; 110 const unsigned char *dsdt_code; 111 unsigned dsdt_size; 112 uint16_t pvpanic_port; 113 uint16_t applesmc_io_base; 114 } AcpiMiscInfo; 115 116 typedef struct AcpiBuildPciBusHotplugState { 117 GArray *device_table; 118 GArray *notify_table; 119 struct AcpiBuildPciBusHotplugState *parent; 120 bool pcihp_bridge_en; 121 } AcpiBuildPciBusHotplugState; 122 123 typedef struct FwCfgTPMConfig { 124 uint32_t tpmppi_address; 125 uint8_t tpm_version; 126 uint8_t tpmppi_version; 127 } QEMU_PACKED FwCfgTPMConfig; 128 129 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 130 131 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 132 .space_id = AML_AS_SYSTEM_IO, 133 .address = NVDIMM_ACPI_IO_BASE, 134 .bit_width = NVDIMM_ACPI_IO_LEN << 3 135 }; 136 137 static void init_common_fadt_data(MachineState *ms, Object *o, 138 AcpiFadtData *data) 139 { 140 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 141 AmlAddressSpace as = AML_AS_SYSTEM_IO; 142 AcpiFadtData fadt = { 143 .rev = 3, 144 .flags = 145 (1 << ACPI_FADT_F_WBINVD) | 146 (1 << ACPI_FADT_F_PROC_C1) | 147 (1 << ACPI_FADT_F_SLP_BUTTON) | 148 (1 << ACPI_FADT_F_RTC_S4) | 149 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 150 /* APIC destination mode ("Flat Logical") has an upper limit of 8 151 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 152 * used 153 */ 154 ((ms->smp.max_cpus > 8) ? 155 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 156 .int_model = 1 /* Multiple APIC */, 157 .rtc_century = RTC_CENTURY, 158 .plvl2_lat = 0xfff /* C2 state not supported */, 159 .plvl3_lat = 0xfff /* C3 state not supported */, 160 .smi_cmd = ACPI_PORT_SMI_CMD, 161 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 162 .acpi_enable_cmd = 163 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 164 .acpi_disable_cmd = 165 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 166 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 167 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 168 .address = io + 0x04 }, 169 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 170 .gpe0_blk = { .space_id = as, .bit_width = 171 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 172 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 173 }, 174 }; 175 *data = fadt; 176 } 177 178 static Object *object_resolve_type_unambiguous(const char *typename) 179 { 180 bool ambig; 181 Object *o = object_resolve_path_type("", typename, &ambig); 182 183 if (ambig || !o) { 184 return NULL; 185 } 186 return o; 187 } 188 189 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 190 { 191 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 192 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 193 Object *obj = piix ? piix : lpc; 194 QObject *o; 195 pm->cpu_hp_io_base = 0; 196 pm->pcihp_io_base = 0; 197 pm->pcihp_io_len = 0; 198 pm->smi_on_cpuhp = false; 199 200 assert(obj); 201 init_common_fadt_data(machine, obj, &pm->fadt); 202 if (piix) { 203 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 204 pm->fadt.rev = 1; 205 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 206 pm->pcihp_io_base = 207 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 208 pm->pcihp_io_len = 209 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 210 } 211 if (lpc) { 212 uint64_t smi_features = object_property_get_uint(lpc, 213 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 214 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 215 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 216 pm->fadt.reset_reg = r; 217 pm->fadt.reset_val = 0xf; 218 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 219 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 220 pm->smi_on_cpuhp = 221 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 222 } 223 224 /* The above need not be conditional on machine type because the reset port 225 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 226 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 227 228 /* Fill in optional s3/s4 related properties */ 229 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 230 if (o) { 231 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 232 } else { 233 pm->s3_disabled = false; 234 } 235 qobject_unref(o); 236 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 237 if (o) { 238 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 239 } else { 240 pm->s4_disabled = false; 241 } 242 qobject_unref(o); 243 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 244 if (o) { 245 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 246 } else { 247 pm->s4_val = false; 248 } 249 qobject_unref(o); 250 251 pm->pcihp_bridge_en = 252 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 253 NULL); 254 } 255 256 static void acpi_get_misc_info(AcpiMiscInfo *info) 257 { 258 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 259 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 260 assert(!!piix != !!lpc); 261 262 if (piix) { 263 info->is_piix4 = true; 264 } 265 if (lpc) { 266 info->is_piix4 = false; 267 } 268 269 info->has_hpet = hpet_find(); 270 info->tpm_version = tpm_get_version(tpm_find()); 271 info->pvpanic_port = pvpanic_port(); 272 info->applesmc_io_base = applesmc_port(); 273 } 274 275 /* 276 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 277 * On i386 arch we only have two pci hosts, so we can look only for them. 278 */ 279 static Object *acpi_get_i386_pci_host(void) 280 { 281 PCIHostState *host; 282 283 host = OBJECT_CHECK(PCIHostState, 284 object_resolve_path("/machine/i440fx", NULL), 285 TYPE_PCI_HOST_BRIDGE); 286 if (!host) { 287 host = OBJECT_CHECK(PCIHostState, 288 object_resolve_path("/machine/q35", NULL), 289 TYPE_PCI_HOST_BRIDGE); 290 } 291 292 return OBJECT(host); 293 } 294 295 static void acpi_get_pci_holes(Range *hole, Range *hole64) 296 { 297 Object *pci_host; 298 299 pci_host = acpi_get_i386_pci_host(); 300 g_assert(pci_host); 301 302 range_set_bounds1(hole, 303 object_property_get_uint(pci_host, 304 PCI_HOST_PROP_PCI_HOLE_START, 305 NULL), 306 object_property_get_uint(pci_host, 307 PCI_HOST_PROP_PCI_HOLE_END, 308 NULL)); 309 range_set_bounds1(hole64, 310 object_property_get_uint(pci_host, 311 PCI_HOST_PROP_PCI_HOLE64_START, 312 NULL), 313 object_property_get_uint(pci_host, 314 PCI_HOST_PROP_PCI_HOLE64_END, 315 NULL)); 316 } 317 318 static void acpi_align_size(GArray *blob, unsigned align) 319 { 320 /* Align size to multiple of given size. This reduces the chance 321 * we need to change size in the future (breaking cross version migration). 322 */ 323 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 324 } 325 326 /* FACS */ 327 static void 328 build_facs(GArray *table_data) 329 { 330 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 331 memcpy(&facs->signature, "FACS", 4); 332 facs->length = cpu_to_le32(sizeof(*facs)); 333 } 334 335 static void build_append_pcihp_notify_entry(Aml *method, int slot) 336 { 337 Aml *if_ctx; 338 int32_t devfn = PCI_DEVFN(slot, 0); 339 340 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 341 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 342 aml_append(method, if_ctx); 343 } 344 345 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 346 bool pcihp_bridge_en) 347 { 348 Aml *dev, *notify_method = NULL, *method; 349 QObject *bsel; 350 PCIBus *sec; 351 int i; 352 353 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 354 if (bsel) { 355 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 356 357 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 358 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 359 } 360 361 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 362 DeviceClass *dc; 363 PCIDeviceClass *pc; 364 PCIDevice *pdev = bus->devices[i]; 365 int slot = PCI_SLOT(i); 366 bool hotplug_enabled_dev; 367 bool bridge_in_acpi; 368 369 if (!pdev) { 370 if (bsel) { /* add hotplug slots for non present devices */ 371 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 372 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 373 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 374 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 375 aml_append(method, 376 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 377 ); 378 aml_append(dev, method); 379 aml_append(parent_scope, dev); 380 381 build_append_pcihp_notify_entry(notify_method, slot); 382 } 383 continue; 384 } 385 386 pc = PCI_DEVICE_GET_CLASS(pdev); 387 dc = DEVICE_GET_CLASS(pdev); 388 389 /* When hotplug for bridges is enabled, bridges are 390 * described in ACPI separately (see build_pci_bus_end). 391 * In this case they aren't themselves hot-pluggable. 392 * Hotplugged bridges *are* hot-pluggable. 393 */ 394 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 395 !DEVICE(pdev)->hotplugged; 396 397 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 398 399 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 400 continue; 401 } 402 403 /* start to compose PCI slot descriptor */ 404 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 405 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 406 407 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 408 /* add VGA specific AML methods */ 409 int s3d; 410 411 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 412 s3d = 3; 413 } else { 414 s3d = 0; 415 } 416 417 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 418 aml_append(method, aml_return(aml_int(0))); 419 aml_append(dev, method); 420 421 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 422 aml_append(method, aml_return(aml_int(0))); 423 aml_append(dev, method); 424 425 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 426 aml_append(method, aml_return(aml_int(s3d))); 427 aml_append(dev, method); 428 } else if (hotplug_enabled_dev) { 429 /* add _SUN/_EJ0 to make slot hotpluggable */ 430 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 431 432 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 433 aml_append(method, 434 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 435 ); 436 aml_append(dev, method); 437 438 if (bsel) { 439 build_append_pcihp_notify_entry(notify_method, slot); 440 } 441 } else if (bridge_in_acpi) { 442 /* 443 * device is coldplugged bridge, 444 * add child device descriptions into its scope 445 */ 446 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 447 448 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 449 } 450 /* slot descriptor has been composed, add it into parent context */ 451 aml_append(parent_scope, dev); 452 } 453 454 if (bsel) { 455 aml_append(parent_scope, notify_method); 456 } 457 458 /* Append PCNT method to notify about events on local and child buses. 459 * Add unconditionally for root since DSDT expects it. 460 */ 461 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 462 463 /* If bus supports hotplug select it and notify about local events */ 464 if (bsel) { 465 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 466 467 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 468 aml_append(method, 469 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 470 ); 471 aml_append(method, 472 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 473 ); 474 } 475 476 /* Notify about child bus events in any case */ 477 if (pcihp_bridge_en) { 478 QLIST_FOREACH(sec, &bus->child, sibling) { 479 int32_t devfn = sec->parent_dev->devfn; 480 481 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 482 continue; 483 } 484 485 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 486 } 487 } 488 aml_append(parent_scope, method); 489 qobject_unref(bsel); 490 } 491 492 /** 493 * build_prt_entry: 494 * @link_name: link name for PCI route entry 495 * 496 * build AML package containing a PCI route entry for @link_name 497 */ 498 static Aml *build_prt_entry(const char *link_name) 499 { 500 Aml *a_zero = aml_int(0); 501 Aml *pkg = aml_package(4); 502 aml_append(pkg, a_zero); 503 aml_append(pkg, a_zero); 504 aml_append(pkg, aml_name("%s", link_name)); 505 aml_append(pkg, a_zero); 506 return pkg; 507 } 508 509 /* 510 * initialize_route - Initialize the interrupt routing rule 511 * through a specific LINK: 512 * if (lnk_idx == idx) 513 * route using link 'link_name' 514 */ 515 static Aml *initialize_route(Aml *route, const char *link_name, 516 Aml *lnk_idx, int idx) 517 { 518 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 519 Aml *pkg = build_prt_entry(link_name); 520 521 aml_append(if_ctx, aml_store(pkg, route)); 522 523 return if_ctx; 524 } 525 526 /* 527 * build_prt - Define interrupt rounting rules 528 * 529 * Returns an array of 128 routes, one for each device, 530 * based on device location. 531 * The main goal is to equaly distribute the interrupts 532 * over the 4 existing ACPI links (works only for i440fx). 533 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 534 * 535 */ 536 static Aml *build_prt(bool is_pci0_prt) 537 { 538 Aml *method, *while_ctx, *pin, *res; 539 540 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 541 res = aml_local(0); 542 pin = aml_local(1); 543 aml_append(method, aml_store(aml_package(128), res)); 544 aml_append(method, aml_store(aml_int(0), pin)); 545 546 /* while (pin < 128) */ 547 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 548 { 549 Aml *slot = aml_local(2); 550 Aml *lnk_idx = aml_local(3); 551 Aml *route = aml_local(4); 552 553 /* slot = pin >> 2 */ 554 aml_append(while_ctx, 555 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 556 /* lnk_idx = (slot + pin) & 3 */ 557 aml_append(while_ctx, 558 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 559 lnk_idx)); 560 561 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 562 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 563 if (is_pci0_prt) { 564 Aml *if_device_1, *if_pin_4, *else_pin_4; 565 566 /* device 1 is the power-management device, needs SCI */ 567 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 568 { 569 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 570 { 571 aml_append(if_pin_4, 572 aml_store(build_prt_entry("LNKS"), route)); 573 } 574 aml_append(if_device_1, if_pin_4); 575 else_pin_4 = aml_else(); 576 { 577 aml_append(else_pin_4, 578 aml_store(build_prt_entry("LNKA"), route)); 579 } 580 aml_append(if_device_1, else_pin_4); 581 } 582 aml_append(while_ctx, if_device_1); 583 } else { 584 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 585 } 586 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 587 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 588 589 /* route[0] = 0x[slot]FFFF */ 590 aml_append(while_ctx, 591 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 592 NULL), 593 aml_index(route, aml_int(0)))); 594 /* route[1] = pin & 3 */ 595 aml_append(while_ctx, 596 aml_store(aml_and(pin, aml_int(3), NULL), 597 aml_index(route, aml_int(1)))); 598 /* res[pin] = route */ 599 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 600 /* pin++ */ 601 aml_append(while_ctx, aml_increment(pin)); 602 } 603 aml_append(method, while_ctx); 604 /* return res*/ 605 aml_append(method, aml_return(res)); 606 607 return method; 608 } 609 610 typedef struct CrsRangeEntry { 611 uint64_t base; 612 uint64_t limit; 613 } CrsRangeEntry; 614 615 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 616 { 617 CrsRangeEntry *entry; 618 619 entry = g_malloc(sizeof(*entry)); 620 entry->base = base; 621 entry->limit = limit; 622 623 g_ptr_array_add(ranges, entry); 624 } 625 626 static void crs_range_free(gpointer data) 627 { 628 CrsRangeEntry *entry = (CrsRangeEntry *)data; 629 g_free(entry); 630 } 631 632 typedef struct CrsRangeSet { 633 GPtrArray *io_ranges; 634 GPtrArray *mem_ranges; 635 GPtrArray *mem_64bit_ranges; 636 } CrsRangeSet; 637 638 static void crs_range_set_init(CrsRangeSet *range_set) 639 { 640 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 641 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 642 range_set->mem_64bit_ranges = 643 g_ptr_array_new_with_free_func(crs_range_free); 644 } 645 646 static void crs_range_set_free(CrsRangeSet *range_set) 647 { 648 g_ptr_array_free(range_set->io_ranges, true); 649 g_ptr_array_free(range_set->mem_ranges, true); 650 g_ptr_array_free(range_set->mem_64bit_ranges, true); 651 } 652 653 static gint crs_range_compare(gconstpointer a, gconstpointer b) 654 { 655 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 656 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 657 658 if (entry_a->base < entry_b->base) { 659 return -1; 660 } else if (entry_a->base > entry_b->base) { 661 return 1; 662 } else { 663 return 0; 664 } 665 } 666 667 /* 668 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 669 * interval, computes the 'free' ranges from the same interval. 670 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 671 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 672 */ 673 static void crs_replace_with_free_ranges(GPtrArray *ranges, 674 uint64_t start, uint64_t end) 675 { 676 GPtrArray *free_ranges = g_ptr_array_new(); 677 uint64_t free_base = start; 678 int i; 679 680 g_ptr_array_sort(ranges, crs_range_compare); 681 for (i = 0; i < ranges->len; i++) { 682 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 683 684 if (free_base < used->base) { 685 crs_range_insert(free_ranges, free_base, used->base - 1); 686 } 687 688 free_base = used->limit + 1; 689 } 690 691 if (free_base < end) { 692 crs_range_insert(free_ranges, free_base, end); 693 } 694 695 g_ptr_array_set_size(ranges, 0); 696 for (i = 0; i < free_ranges->len; i++) { 697 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 698 } 699 700 g_ptr_array_free(free_ranges, true); 701 } 702 703 /* 704 * crs_range_merge - merges adjacent ranges in the given array. 705 * Array elements are deleted and replaced with the merged ranges. 706 */ 707 static void crs_range_merge(GPtrArray *range) 708 { 709 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 710 CrsRangeEntry *entry; 711 uint64_t range_base, range_limit; 712 int i; 713 714 if (!range->len) { 715 return; 716 } 717 718 g_ptr_array_sort(range, crs_range_compare); 719 720 entry = g_ptr_array_index(range, 0); 721 range_base = entry->base; 722 range_limit = entry->limit; 723 for (i = 1; i < range->len; i++) { 724 entry = g_ptr_array_index(range, i); 725 if (entry->base - 1 == range_limit) { 726 range_limit = entry->limit; 727 } else { 728 crs_range_insert(tmp, range_base, range_limit); 729 range_base = entry->base; 730 range_limit = entry->limit; 731 } 732 } 733 crs_range_insert(tmp, range_base, range_limit); 734 735 g_ptr_array_set_size(range, 0); 736 for (i = 0; i < tmp->len; i++) { 737 entry = g_ptr_array_index(tmp, i); 738 crs_range_insert(range, entry->base, entry->limit); 739 } 740 g_ptr_array_free(tmp, true); 741 } 742 743 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 744 { 745 Aml *crs = aml_resource_template(); 746 CrsRangeSet temp_range_set; 747 CrsRangeEntry *entry; 748 uint8_t max_bus = pci_bus_num(host->bus); 749 uint8_t type; 750 int devfn; 751 int i; 752 753 crs_range_set_init(&temp_range_set); 754 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 755 uint64_t range_base, range_limit; 756 PCIDevice *dev = host->bus->devices[devfn]; 757 758 if (!dev) { 759 continue; 760 } 761 762 for (i = 0; i < PCI_NUM_REGIONS; i++) { 763 PCIIORegion *r = &dev->io_regions[i]; 764 765 range_base = r->addr; 766 range_limit = r->addr + r->size - 1; 767 768 /* 769 * Work-around for old bioses 770 * that do not support multiple root buses 771 */ 772 if (!range_base || range_base > range_limit) { 773 continue; 774 } 775 776 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 777 crs_range_insert(temp_range_set.io_ranges, 778 range_base, range_limit); 779 } else { /* "memory" */ 780 crs_range_insert(temp_range_set.mem_ranges, 781 range_base, range_limit); 782 } 783 } 784 785 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 786 if (type == PCI_HEADER_TYPE_BRIDGE) { 787 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 788 if (subordinate > max_bus) { 789 max_bus = subordinate; 790 } 791 792 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 793 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 794 795 /* 796 * Work-around for old bioses 797 * that do not support multiple root buses 798 */ 799 if (range_base && range_base <= range_limit) { 800 crs_range_insert(temp_range_set.io_ranges, 801 range_base, range_limit); 802 } 803 804 range_base = 805 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 806 range_limit = 807 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 808 809 /* 810 * Work-around for old bioses 811 * that do not support multiple root buses 812 */ 813 if (range_base && range_base <= range_limit) { 814 uint64_t length = range_limit - range_base + 1; 815 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 816 crs_range_insert(temp_range_set.mem_ranges, 817 range_base, range_limit); 818 } else { 819 crs_range_insert(temp_range_set.mem_64bit_ranges, 820 range_base, range_limit); 821 } 822 } 823 824 range_base = 825 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 826 range_limit = 827 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 828 829 /* 830 * Work-around for old bioses 831 * that do not support multiple root buses 832 */ 833 if (range_base && range_base <= range_limit) { 834 uint64_t length = range_limit - range_base + 1; 835 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 836 crs_range_insert(temp_range_set.mem_ranges, 837 range_base, range_limit); 838 } else { 839 crs_range_insert(temp_range_set.mem_64bit_ranges, 840 range_base, range_limit); 841 } 842 } 843 } 844 } 845 846 crs_range_merge(temp_range_set.io_ranges); 847 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 848 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 849 aml_append(crs, 850 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 851 AML_POS_DECODE, AML_ENTIRE_RANGE, 852 0, entry->base, entry->limit, 0, 853 entry->limit - entry->base + 1)); 854 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 855 } 856 857 crs_range_merge(temp_range_set.mem_ranges); 858 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 859 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 860 aml_append(crs, 861 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 862 AML_MAX_FIXED, AML_NON_CACHEABLE, 863 AML_READ_WRITE, 864 0, entry->base, entry->limit, 0, 865 entry->limit - entry->base + 1)); 866 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 867 } 868 869 crs_range_merge(temp_range_set.mem_64bit_ranges); 870 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 871 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 872 aml_append(crs, 873 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 874 AML_MAX_FIXED, AML_NON_CACHEABLE, 875 AML_READ_WRITE, 876 0, entry->base, entry->limit, 0, 877 entry->limit - entry->base + 1)); 878 crs_range_insert(range_set->mem_64bit_ranges, 879 entry->base, entry->limit); 880 } 881 882 crs_range_set_free(&temp_range_set); 883 884 aml_append(crs, 885 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 886 0, 887 pci_bus_num(host->bus), 888 max_bus, 889 0, 890 max_bus - pci_bus_num(host->bus) + 1)); 891 892 return crs; 893 } 894 895 static void build_hpet_aml(Aml *table) 896 { 897 Aml *crs; 898 Aml *field; 899 Aml *method; 900 Aml *if_ctx; 901 Aml *scope = aml_scope("_SB"); 902 Aml *dev = aml_device("HPET"); 903 Aml *zero = aml_int(0); 904 Aml *id = aml_local(0); 905 Aml *period = aml_local(1); 906 907 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 908 aml_append(dev, aml_name_decl("_UID", zero)); 909 910 aml_append(dev, 911 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 912 HPET_LEN)); 913 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 914 aml_append(field, aml_named_field("VEND", 32)); 915 aml_append(field, aml_named_field("PRD", 32)); 916 aml_append(dev, field); 917 918 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 919 aml_append(method, aml_store(aml_name("VEND"), id)); 920 aml_append(method, aml_store(aml_name("PRD"), period)); 921 aml_append(method, aml_shiftright(id, aml_int(16), id)); 922 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 923 aml_equal(id, aml_int(0xffff)))); 924 { 925 aml_append(if_ctx, aml_return(zero)); 926 } 927 aml_append(method, if_ctx); 928 929 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 930 aml_lgreater(period, aml_int(100000000)))); 931 { 932 aml_append(if_ctx, aml_return(zero)); 933 } 934 aml_append(method, if_ctx); 935 936 aml_append(method, aml_return(aml_int(0x0F))); 937 aml_append(dev, method); 938 939 crs = aml_resource_template(); 940 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 941 aml_append(dev, aml_name_decl("_CRS", crs)); 942 943 aml_append(scope, dev); 944 aml_append(table, scope); 945 } 946 947 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 948 { 949 Aml *dev; 950 Aml *method; 951 Aml *crs; 952 953 dev = aml_device("VMBS"); 954 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 955 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 956 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 957 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 958 959 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 960 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 961 aml_name("STA"))); 962 aml_append(dev, method); 963 964 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 965 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 966 aml_name("STA"))); 967 aml_append(dev, method); 968 969 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 970 aml_append(method, aml_return(aml_name("STA"))); 971 aml_append(dev, method); 972 973 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 974 975 crs = aml_resource_template(); 976 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 977 aml_append(dev, aml_name_decl("_CRS", crs)); 978 979 return dev; 980 } 981 982 static void build_isa_devices_aml(Aml *table) 983 { 984 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 985 bool ambiguous; 986 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 987 Aml *scope; 988 989 assert(obj && !ambiguous); 990 991 scope = aml_scope("_SB.PCI0.ISA"); 992 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 993 isa_build_aml(ISA_BUS(obj), scope); 994 995 if (vmbus_bridge) { 996 aml_append(scope, build_vmbus_device_aml(vmbus_bridge)); 997 } 998 999 aml_append(table, scope); 1000 } 1001 1002 static void build_dbg_aml(Aml *table) 1003 { 1004 Aml *field; 1005 Aml *method; 1006 Aml *while_ctx; 1007 Aml *scope = aml_scope("\\"); 1008 Aml *buf = aml_local(0); 1009 Aml *len = aml_local(1); 1010 Aml *idx = aml_local(2); 1011 1012 aml_append(scope, 1013 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1014 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1015 aml_append(field, aml_named_field("DBGB", 8)); 1016 aml_append(scope, field); 1017 1018 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1019 1020 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1021 aml_append(method, aml_to_buffer(buf, buf)); 1022 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1023 aml_append(method, aml_store(aml_int(0), idx)); 1024 1025 while_ctx = aml_while(aml_lless(idx, len)); 1026 aml_append(while_ctx, 1027 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1028 aml_append(while_ctx, aml_increment(idx)); 1029 aml_append(method, while_ctx); 1030 1031 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1032 aml_append(scope, method); 1033 1034 aml_append(table, scope); 1035 } 1036 1037 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1038 { 1039 Aml *dev; 1040 Aml *crs; 1041 Aml *method; 1042 uint32_t irqs[] = {5, 10, 11}; 1043 1044 dev = aml_device("%s", name); 1045 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1046 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1047 1048 crs = aml_resource_template(); 1049 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1050 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1051 aml_append(dev, aml_name_decl("_PRS", crs)); 1052 1053 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1054 aml_append(method, aml_return(aml_call1("IQST", reg))); 1055 aml_append(dev, method); 1056 1057 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1058 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1059 aml_append(dev, method); 1060 1061 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1062 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1063 aml_append(dev, method); 1064 1065 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1066 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1067 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1068 aml_append(dev, method); 1069 1070 return dev; 1071 } 1072 1073 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1074 { 1075 Aml *dev; 1076 Aml *crs; 1077 Aml *method; 1078 uint32_t irqs; 1079 1080 dev = aml_device("%s", name); 1081 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1082 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1083 1084 crs = aml_resource_template(); 1085 irqs = gsi; 1086 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1087 AML_SHARED, &irqs, 1)); 1088 aml_append(dev, aml_name_decl("_PRS", crs)); 1089 1090 aml_append(dev, aml_name_decl("_CRS", crs)); 1091 1092 /* 1093 * _DIS can be no-op because the interrupt cannot be disabled. 1094 */ 1095 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1096 aml_append(dev, method); 1097 1098 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1099 aml_append(dev, method); 1100 1101 return dev; 1102 } 1103 1104 /* _CRS method - get current settings */ 1105 static Aml *build_iqcr_method(bool is_piix4) 1106 { 1107 Aml *if_ctx; 1108 uint32_t irqs; 1109 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1110 Aml *crs = aml_resource_template(); 1111 1112 irqs = 0; 1113 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1114 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1115 aml_append(method, aml_name_decl("PRR0", crs)); 1116 1117 aml_append(method, 1118 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1119 1120 if (is_piix4) { 1121 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1122 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1123 aml_append(method, if_ctx); 1124 } else { 1125 aml_append(method, 1126 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1127 aml_name("PRRI"))); 1128 } 1129 1130 aml_append(method, aml_return(aml_name("PRR0"))); 1131 return method; 1132 } 1133 1134 /* _STA method - get status */ 1135 static Aml *build_irq_status_method(void) 1136 { 1137 Aml *if_ctx; 1138 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1139 1140 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1141 aml_append(if_ctx, aml_return(aml_int(0x09))); 1142 aml_append(method, if_ctx); 1143 aml_append(method, aml_return(aml_int(0x0B))); 1144 return method; 1145 } 1146 1147 static void build_piix4_pci0_int(Aml *table) 1148 { 1149 Aml *dev; 1150 Aml *crs; 1151 Aml *field; 1152 Aml *method; 1153 uint32_t irqs; 1154 Aml *sb_scope = aml_scope("_SB"); 1155 Aml *pci0_scope = aml_scope("PCI0"); 1156 1157 aml_append(pci0_scope, build_prt(true)); 1158 aml_append(sb_scope, pci0_scope); 1159 1160 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1161 aml_append(field, aml_named_field("PRQ0", 8)); 1162 aml_append(field, aml_named_field("PRQ1", 8)); 1163 aml_append(field, aml_named_field("PRQ2", 8)); 1164 aml_append(field, aml_named_field("PRQ3", 8)); 1165 aml_append(sb_scope, field); 1166 1167 aml_append(sb_scope, build_irq_status_method()); 1168 aml_append(sb_scope, build_iqcr_method(true)); 1169 1170 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1171 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1172 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1173 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1174 1175 dev = aml_device("LNKS"); 1176 { 1177 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1178 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1179 1180 crs = aml_resource_template(); 1181 irqs = 9; 1182 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1183 AML_ACTIVE_HIGH, AML_SHARED, 1184 &irqs, 1)); 1185 aml_append(dev, aml_name_decl("_PRS", crs)); 1186 1187 /* The SCI cannot be disabled and is always attached to GSI 9, 1188 * so these are no-ops. We only need this link to override the 1189 * polarity to active high and match the content of the MADT. 1190 */ 1191 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1192 aml_append(method, aml_return(aml_int(0x0b))); 1193 aml_append(dev, method); 1194 1195 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1196 aml_append(dev, method); 1197 1198 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1199 aml_append(method, aml_return(aml_name("_PRS"))); 1200 aml_append(dev, method); 1201 1202 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1203 aml_append(dev, method); 1204 } 1205 aml_append(sb_scope, dev); 1206 1207 aml_append(table, sb_scope); 1208 } 1209 1210 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1211 { 1212 int i; 1213 int head; 1214 Aml *pkg; 1215 char base = name[3] < 'E' ? 'A' : 'E'; 1216 char *s = g_strdup(name); 1217 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1218 1219 assert(strlen(s) == 4); 1220 1221 head = name[3] - base; 1222 for (i = 0; i < 4; i++) { 1223 if (head + i > 3) { 1224 head = i * -1; 1225 } 1226 s[3] = base + head + i; 1227 pkg = aml_package(4); 1228 aml_append(pkg, a_nr); 1229 aml_append(pkg, aml_int(i)); 1230 aml_append(pkg, aml_name("%s", s)); 1231 aml_append(pkg, aml_int(0)); 1232 aml_append(ctx, pkg); 1233 } 1234 g_free(s); 1235 } 1236 1237 static Aml *build_q35_routing_table(const char *str) 1238 { 1239 int i; 1240 Aml *pkg; 1241 char *name = g_strdup_printf("%s ", str); 1242 1243 pkg = aml_package(128); 1244 for (i = 0; i < 0x18; i++) { 1245 name[3] = 'E' + (i & 0x3); 1246 append_q35_prt_entry(pkg, i, name); 1247 } 1248 1249 name[3] = 'E'; 1250 append_q35_prt_entry(pkg, 0x18, name); 1251 1252 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1253 for (i = 0x0019; i < 0x1e; i++) { 1254 name[3] = 'A'; 1255 append_q35_prt_entry(pkg, i, name); 1256 } 1257 1258 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1259 name[3] = 'E'; 1260 append_q35_prt_entry(pkg, 0x1e, name); 1261 name[3] = 'A'; 1262 append_q35_prt_entry(pkg, 0x1f, name); 1263 1264 g_free(name); 1265 return pkg; 1266 } 1267 1268 static void build_q35_pci0_int(Aml *table) 1269 { 1270 Aml *field; 1271 Aml *method; 1272 Aml *sb_scope = aml_scope("_SB"); 1273 Aml *pci0_scope = aml_scope("PCI0"); 1274 1275 /* Zero => PIC mode, One => APIC Mode */ 1276 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1277 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1278 { 1279 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1280 } 1281 aml_append(table, method); 1282 1283 aml_append(pci0_scope, 1284 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1285 aml_append(pci0_scope, 1286 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1287 1288 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1289 { 1290 Aml *if_ctx; 1291 Aml *else_ctx; 1292 1293 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1294 section 6.2.8.1 */ 1295 /* Note: we provide the same info as the PCI routing 1296 table of the Bochs BIOS */ 1297 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1298 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1299 aml_append(method, if_ctx); 1300 else_ctx = aml_else(); 1301 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1302 aml_append(method, else_ctx); 1303 } 1304 aml_append(pci0_scope, method); 1305 aml_append(sb_scope, pci0_scope); 1306 1307 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1308 aml_append(field, aml_named_field("PRQA", 8)); 1309 aml_append(field, aml_named_field("PRQB", 8)); 1310 aml_append(field, aml_named_field("PRQC", 8)); 1311 aml_append(field, aml_named_field("PRQD", 8)); 1312 aml_append(field, aml_reserved_field(0x20)); 1313 aml_append(field, aml_named_field("PRQE", 8)); 1314 aml_append(field, aml_named_field("PRQF", 8)); 1315 aml_append(field, aml_named_field("PRQG", 8)); 1316 aml_append(field, aml_named_field("PRQH", 8)); 1317 aml_append(sb_scope, field); 1318 1319 aml_append(sb_scope, build_irq_status_method()); 1320 aml_append(sb_scope, build_iqcr_method(false)); 1321 1322 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1323 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1324 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1325 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1326 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1327 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1328 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1329 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1330 1331 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1332 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1333 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1334 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1335 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1336 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1337 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1338 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1339 1340 aml_append(table, sb_scope); 1341 } 1342 1343 static void build_q35_isa_bridge(Aml *table) 1344 { 1345 Aml *dev; 1346 Aml *scope; 1347 1348 scope = aml_scope("_SB.PCI0"); 1349 dev = aml_device("ISA"); 1350 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1351 1352 /* ICH9 PCI to ISA irq remapping */ 1353 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1354 aml_int(0x60), 0x0C)); 1355 1356 aml_append(scope, dev); 1357 aml_append(table, scope); 1358 } 1359 1360 static void build_piix4_isa_bridge(Aml *table) 1361 { 1362 Aml *dev; 1363 Aml *scope; 1364 1365 scope = aml_scope("_SB.PCI0"); 1366 dev = aml_device("ISA"); 1367 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1368 1369 /* PIIX PCI to ISA irq remapping */ 1370 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1371 aml_int(0x60), 0x04)); 1372 1373 aml_append(scope, dev); 1374 aml_append(table, scope); 1375 } 1376 1377 static void build_piix4_pci_hotplug(Aml *table) 1378 { 1379 Aml *scope; 1380 Aml *field; 1381 Aml *method; 1382 1383 scope = aml_scope("_SB.PCI0"); 1384 1385 aml_append(scope, 1386 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1387 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1388 aml_append(field, aml_named_field("PCIU", 32)); 1389 aml_append(field, aml_named_field("PCID", 32)); 1390 aml_append(scope, field); 1391 1392 aml_append(scope, 1393 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1394 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1395 aml_append(field, aml_named_field("B0EJ", 32)); 1396 aml_append(scope, field); 1397 1398 aml_append(scope, 1399 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1400 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1401 aml_append(field, aml_named_field("BNUM", 32)); 1402 aml_append(scope, field); 1403 1404 aml_append(scope, aml_mutex("BLCK", 0)); 1405 1406 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1407 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1408 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1409 aml_append(method, 1410 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1411 aml_append(method, aml_release(aml_name("BLCK"))); 1412 aml_append(method, aml_return(aml_int(0))); 1413 aml_append(scope, method); 1414 1415 aml_append(table, scope); 1416 } 1417 1418 static Aml *build_q35_osc_method(void) 1419 { 1420 Aml *if_ctx; 1421 Aml *if_ctx2; 1422 Aml *else_ctx; 1423 Aml *method; 1424 Aml *a_cwd1 = aml_name("CDW1"); 1425 Aml *a_ctrl = aml_local(0); 1426 1427 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1428 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1429 1430 if_ctx = aml_if(aml_equal( 1431 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1432 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1433 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1434 1435 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1436 1437 /* 1438 * Always allow native PME, AER (no dependencies) 1439 * Allow SHPC (PCI bridges can have SHPC controller) 1440 */ 1441 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1442 1443 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1444 /* Unknown revision */ 1445 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1446 aml_append(if_ctx, if_ctx2); 1447 1448 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1449 /* Capabilities bits were masked */ 1450 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1451 aml_append(if_ctx, if_ctx2); 1452 1453 /* Update DWORD3 in the buffer */ 1454 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1455 aml_append(method, if_ctx); 1456 1457 else_ctx = aml_else(); 1458 /* Unrecognized UUID */ 1459 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1460 aml_append(method, else_ctx); 1461 1462 aml_append(method, aml_return(aml_arg(3))); 1463 return method; 1464 } 1465 1466 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1467 { 1468 Aml *scope = aml_scope("_SB.PCI0"); 1469 Aml *dev = aml_device("SMB0"); 1470 1471 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1472 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1473 aml_append(scope, dev); 1474 aml_append(table, scope); 1475 } 1476 1477 static void 1478 build_dsdt(GArray *table_data, BIOSLinker *linker, 1479 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1480 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1481 { 1482 CrsRangeEntry *entry; 1483 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1484 CrsRangeSet crs_range_set; 1485 PCMachineState *pcms = PC_MACHINE(machine); 1486 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1487 X86MachineState *x86ms = X86_MACHINE(machine); 1488 AcpiMcfgInfo mcfg; 1489 uint32_t nr_mem = machine->ram_slots; 1490 int root_bus_limit = 0xFF; 1491 PCIBus *bus = NULL; 1492 TPMIf *tpm = tpm_find(); 1493 int i; 1494 1495 dsdt = init_aml_allocator(); 1496 1497 /* Reserve space for header */ 1498 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1499 1500 build_dbg_aml(dsdt); 1501 if (misc->is_piix4) { 1502 sb_scope = aml_scope("_SB"); 1503 dev = aml_device("PCI0"); 1504 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1505 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1506 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1507 aml_append(sb_scope, dev); 1508 aml_append(dsdt, sb_scope); 1509 1510 build_hpet_aml(dsdt); 1511 build_piix4_isa_bridge(dsdt); 1512 build_isa_devices_aml(dsdt); 1513 build_piix4_pci_hotplug(dsdt); 1514 build_piix4_pci0_int(dsdt); 1515 } else { 1516 sb_scope = aml_scope("_SB"); 1517 dev = aml_device("PCI0"); 1518 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1519 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1520 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1521 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1522 aml_append(dev, build_q35_osc_method()); 1523 aml_append(sb_scope, dev); 1524 1525 if (pm->smi_on_cpuhp) { 1526 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1527 dev = aml_device("PCI0.SMI0"); 1528 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1529 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1530 crs = aml_resource_template(); 1531 aml_append(crs, 1532 aml_io( 1533 AML_DECODE16, 1534 ACPI_PORT_SMI_CMD, 1535 ACPI_PORT_SMI_CMD, 1536 1, 1537 2) 1538 ); 1539 aml_append(dev, aml_name_decl("_CRS", crs)); 1540 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1541 aml_int(ACPI_PORT_SMI_CMD), 2)); 1542 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1543 AML_WRITE_AS_ZEROS); 1544 aml_append(field, aml_named_field("SMIC", 8)); 1545 aml_append(field, aml_reserved_field(8)); 1546 aml_append(dev, field); 1547 aml_append(sb_scope, dev); 1548 } 1549 1550 aml_append(dsdt, sb_scope); 1551 1552 build_hpet_aml(dsdt); 1553 build_q35_isa_bridge(dsdt); 1554 build_isa_devices_aml(dsdt); 1555 build_q35_pci0_int(dsdt); 1556 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1557 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1558 } 1559 } 1560 1561 if (pcmc->legacy_cpu_hotplug) { 1562 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1563 } else { 1564 CPUHotplugFeatures opts = { 1565 .acpi_1_compatible = true, .has_legacy_cphp = true, 1566 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1567 }; 1568 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1569 "\\_SB.PCI0", "\\_GPE._E02"); 1570 } 1571 1572 if (pcms->memhp_io_base && nr_mem) { 1573 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1574 "\\_GPE._E03", AML_SYSTEM_IO, 1575 pcms->memhp_io_base); 1576 } 1577 1578 scope = aml_scope("_GPE"); 1579 { 1580 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1581 1582 if (misc->is_piix4) { 1583 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1584 aml_append(method, 1585 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1586 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1587 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1588 aml_append(scope, method); 1589 } 1590 1591 if (machine->nvdimms_state->is_enabled) { 1592 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1593 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1594 aml_int(0x80))); 1595 aml_append(scope, method); 1596 } 1597 } 1598 aml_append(dsdt, scope); 1599 1600 crs_range_set_init(&crs_range_set); 1601 bus = PC_MACHINE(machine)->bus; 1602 if (bus) { 1603 QLIST_FOREACH(bus, &bus->child, sibling) { 1604 uint8_t bus_num = pci_bus_num(bus); 1605 uint8_t numa_node = pci_bus_numa_node(bus); 1606 1607 /* look only for expander root buses */ 1608 if (!pci_bus_is_root(bus)) { 1609 continue; 1610 } 1611 1612 if (bus_num < root_bus_limit) { 1613 root_bus_limit = bus_num - 1; 1614 } 1615 1616 scope = aml_scope("\\_SB"); 1617 dev = aml_device("PC%.02X", bus_num); 1618 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1619 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1620 if (pci_bus_is_express(bus)) { 1621 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1622 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1623 aml_append(dev, build_q35_osc_method()); 1624 } else { 1625 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1626 } 1627 1628 if (numa_node != NUMA_NODE_UNASSIGNED) { 1629 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1630 } 1631 1632 aml_append(dev, build_prt(false)); 1633 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1634 aml_append(dev, aml_name_decl("_CRS", crs)); 1635 aml_append(scope, dev); 1636 aml_append(dsdt, scope); 1637 } 1638 } 1639 1640 /* 1641 * At this point crs_range_set has all the ranges used by pci 1642 * busses *other* than PCI0. These ranges will be excluded from 1643 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1644 * too. 1645 */ 1646 if (acpi_get_mcfg(&mcfg)) { 1647 crs_range_insert(crs_range_set.mem_ranges, 1648 mcfg.base, mcfg.base + mcfg.size - 1); 1649 } 1650 1651 scope = aml_scope("\\_SB.PCI0"); 1652 /* build PCI0._CRS */ 1653 crs = aml_resource_template(); 1654 aml_append(crs, 1655 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1656 0x0000, 0x0, root_bus_limit, 1657 0x0000, root_bus_limit + 1)); 1658 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1659 1660 aml_append(crs, 1661 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1662 AML_POS_DECODE, AML_ENTIRE_RANGE, 1663 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1664 1665 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1666 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1667 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1668 aml_append(crs, 1669 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1670 AML_POS_DECODE, AML_ENTIRE_RANGE, 1671 0x0000, entry->base, entry->limit, 1672 0x0000, entry->limit - entry->base + 1)); 1673 } 1674 1675 aml_append(crs, 1676 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1677 AML_CACHEABLE, AML_READ_WRITE, 1678 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1679 1680 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1681 range_lob(pci_hole), 1682 range_upb(pci_hole)); 1683 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1684 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1685 aml_append(crs, 1686 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1687 AML_NON_CACHEABLE, AML_READ_WRITE, 1688 0, entry->base, entry->limit, 1689 0, entry->limit - entry->base + 1)); 1690 } 1691 1692 if (!range_is_empty(pci_hole64)) { 1693 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1694 range_lob(pci_hole64), 1695 range_upb(pci_hole64)); 1696 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1697 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1698 aml_append(crs, 1699 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1700 AML_MAX_FIXED, 1701 AML_CACHEABLE, AML_READ_WRITE, 1702 0, entry->base, entry->limit, 1703 0, entry->limit - entry->base + 1)); 1704 } 1705 } 1706 1707 if (TPM_IS_TIS_ISA(tpm_find())) { 1708 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1709 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1710 } 1711 aml_append(scope, aml_name_decl("_CRS", crs)); 1712 1713 /* reserve GPE0 block resources */ 1714 dev = aml_device("GPE0"); 1715 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1716 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1717 /* device present, functioning, decoding, not shown in UI */ 1718 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1719 crs = aml_resource_template(); 1720 aml_append(crs, 1721 aml_io( 1722 AML_DECODE16, 1723 pm->fadt.gpe0_blk.address, 1724 pm->fadt.gpe0_blk.address, 1725 1, 1726 pm->fadt.gpe0_blk.bit_width / 8) 1727 ); 1728 aml_append(dev, aml_name_decl("_CRS", crs)); 1729 aml_append(scope, dev); 1730 1731 crs_range_set_free(&crs_range_set); 1732 1733 /* reserve PCIHP resources */ 1734 if (pm->pcihp_io_len) { 1735 dev = aml_device("PHPR"); 1736 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1737 aml_append(dev, 1738 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1739 /* device present, functioning, decoding, not shown in UI */ 1740 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1741 crs = aml_resource_template(); 1742 aml_append(crs, 1743 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1744 pm->pcihp_io_len) 1745 ); 1746 aml_append(dev, aml_name_decl("_CRS", crs)); 1747 aml_append(scope, dev); 1748 } 1749 aml_append(dsdt, scope); 1750 1751 /* create S3_ / S4_ / S5_ packages if necessary */ 1752 scope = aml_scope("\\"); 1753 if (!pm->s3_disabled) { 1754 pkg = aml_package(4); 1755 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1756 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1757 aml_append(pkg, aml_int(0)); /* reserved */ 1758 aml_append(pkg, aml_int(0)); /* reserved */ 1759 aml_append(scope, aml_name_decl("_S3", pkg)); 1760 } 1761 1762 if (!pm->s4_disabled) { 1763 pkg = aml_package(4); 1764 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1765 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1766 aml_append(pkg, aml_int(pm->s4_val)); 1767 aml_append(pkg, aml_int(0)); /* reserved */ 1768 aml_append(pkg, aml_int(0)); /* reserved */ 1769 aml_append(scope, aml_name_decl("_S4", pkg)); 1770 } 1771 1772 pkg = aml_package(4); 1773 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1774 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1775 aml_append(pkg, aml_int(0)); /* reserved */ 1776 aml_append(pkg, aml_int(0)); /* reserved */ 1777 aml_append(scope, aml_name_decl("_S5", pkg)); 1778 aml_append(dsdt, scope); 1779 1780 /* create fw_cfg node, unconditionally */ 1781 { 1782 scope = aml_scope("\\_SB.PCI0"); 1783 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1784 aml_append(dsdt, scope); 1785 } 1786 1787 if (misc->applesmc_io_base) { 1788 scope = aml_scope("\\_SB.PCI0.ISA"); 1789 dev = aml_device("SMC"); 1790 1791 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1792 /* device present, functioning, decoding, not shown in UI */ 1793 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1794 1795 crs = aml_resource_template(); 1796 aml_append(crs, 1797 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1798 0x01, APPLESMC_MAX_DATA_LENGTH) 1799 ); 1800 aml_append(crs, aml_irq_no_flags(6)); 1801 aml_append(dev, aml_name_decl("_CRS", crs)); 1802 1803 aml_append(scope, dev); 1804 aml_append(dsdt, scope); 1805 } 1806 1807 if (misc->pvpanic_port) { 1808 scope = aml_scope("\\_SB.PCI0.ISA"); 1809 1810 dev = aml_device("PEVT"); 1811 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1812 1813 crs = aml_resource_template(); 1814 aml_append(crs, 1815 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1816 ); 1817 aml_append(dev, aml_name_decl("_CRS", crs)); 1818 1819 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1820 aml_int(misc->pvpanic_port), 1)); 1821 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1822 aml_append(field, aml_named_field("PEPT", 8)); 1823 aml_append(dev, field); 1824 1825 /* device present, functioning, decoding, shown in UI */ 1826 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1827 1828 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1829 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1830 aml_append(method, aml_return(aml_local(0))); 1831 aml_append(dev, method); 1832 1833 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1834 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1835 aml_append(dev, method); 1836 1837 aml_append(scope, dev); 1838 aml_append(dsdt, scope); 1839 } 1840 1841 sb_scope = aml_scope("\\_SB"); 1842 { 1843 Object *pci_host; 1844 PCIBus *bus = NULL; 1845 1846 pci_host = acpi_get_i386_pci_host(); 1847 if (pci_host) { 1848 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1849 } 1850 1851 if (bus) { 1852 Aml *scope = aml_scope("PCI0"); 1853 /* Scan all PCI buses. Generate tables to support hotplug. */ 1854 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1855 1856 if (TPM_IS_TIS_ISA(tpm)) { 1857 if (misc->tpm_version == TPM_VERSION_2_0) { 1858 dev = aml_device("TPM"); 1859 aml_append(dev, aml_name_decl("_HID", 1860 aml_string("MSFT0101"))); 1861 } else { 1862 dev = aml_device("ISA.TPM"); 1863 aml_append(dev, aml_name_decl("_HID", 1864 aml_eisaid("PNP0C31"))); 1865 } 1866 1867 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1868 crs = aml_resource_template(); 1869 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1870 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1871 /* 1872 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1873 Rewrite to take IRQ from TPM device model and 1874 fix default IRQ value there to use some unused IRQ 1875 */ 1876 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1877 aml_append(dev, aml_name_decl("_CRS", crs)); 1878 1879 tpm_build_ppi_acpi(tpm, dev); 1880 1881 aml_append(scope, dev); 1882 } 1883 1884 aml_append(sb_scope, scope); 1885 } 1886 } 1887 1888 if (TPM_IS_CRB(tpm)) { 1889 dev = aml_device("TPM"); 1890 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1891 crs = aml_resource_template(); 1892 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1893 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1894 aml_append(dev, aml_name_decl("_CRS", crs)); 1895 1896 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1897 1898 tpm_build_ppi_acpi(tpm, dev); 1899 1900 aml_append(sb_scope, dev); 1901 } 1902 1903 aml_append(dsdt, sb_scope); 1904 1905 /* copy AML table into ACPI tables blob and patch header there */ 1906 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1907 build_header(linker, table_data, 1908 (void *)(table_data->data + table_data->len - dsdt->buf->len), 1909 "DSDT", dsdt->buf->len, 1, NULL, NULL); 1910 free_aml_allocator(); 1911 } 1912 1913 static void 1914 build_hpet(GArray *table_data, BIOSLinker *linker) 1915 { 1916 Acpi20Hpet *hpet; 1917 1918 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1919 /* Note timer_block_id value must be kept in sync with value advertised by 1920 * emulated hpet 1921 */ 1922 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1923 hpet->addr.address = cpu_to_le64(HPET_BASE); 1924 build_header(linker, table_data, 1925 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 1926 } 1927 1928 static void 1929 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 1930 { 1931 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1932 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 1933 unsigned log_addr_offset = 1934 (char *)&tcpa->log_area_start_address - table_data->data; 1935 1936 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1937 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1938 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 1939 1940 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1941 false /* high memory */); 1942 1943 /* log area start address to be filled by Guest linker */ 1944 bios_linker_loader_add_pointer(linker, 1945 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 1946 ACPI_BUILD_TPMLOG_FILE, 0); 1947 1948 build_header(linker, table_data, 1949 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 1950 } 1951 1952 #define HOLE_640K_START (640 * KiB) 1953 #define HOLE_640K_END (1 * MiB) 1954 1955 static void 1956 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1957 { 1958 AcpiSystemResourceAffinityTable *srat; 1959 AcpiSratMemoryAffinity *numamem; 1960 1961 int i; 1962 int srat_start, numa_start, slots; 1963 uint64_t mem_len, mem_base, next_base; 1964 MachineClass *mc = MACHINE_GET_CLASS(machine); 1965 X86MachineState *x86ms = X86_MACHINE(machine); 1966 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1967 PCMachineState *pcms = PC_MACHINE(machine); 1968 ram_addr_t hotplugabble_address_space_size = 1969 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1970 NULL); 1971 1972 srat_start = table_data->len; 1973 1974 srat = acpi_data_push(table_data, sizeof *srat); 1975 srat->reserved1 = cpu_to_le32(1); 1976 1977 for (i = 0; i < apic_ids->len; i++) { 1978 int node_id = apic_ids->cpus[i].props.node_id; 1979 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1980 1981 if (apic_id < 255) { 1982 AcpiSratProcessorAffinity *core; 1983 1984 core = acpi_data_push(table_data, sizeof *core); 1985 core->type = ACPI_SRAT_PROCESSOR_APIC; 1986 core->length = sizeof(*core); 1987 core->local_apic_id = apic_id; 1988 core->proximity_lo = node_id; 1989 memset(core->proximity_hi, 0, 3); 1990 core->local_sapic_eid = 0; 1991 core->flags = cpu_to_le32(1); 1992 } else { 1993 AcpiSratProcessorX2ApicAffinity *core; 1994 1995 core = acpi_data_push(table_data, sizeof *core); 1996 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 1997 core->length = sizeof(*core); 1998 core->x2apic_id = cpu_to_le32(apic_id); 1999 core->proximity_domain = cpu_to_le32(node_id); 2000 core->flags = cpu_to_le32(1); 2001 } 2002 } 2003 2004 2005 /* the memory map is a bit tricky, it contains at least one hole 2006 * from 640k-1M and possibly another one from 3.5G-4G. 2007 */ 2008 next_base = 0; 2009 numa_start = table_data->len; 2010 2011 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2012 mem_base = next_base; 2013 mem_len = pcms->node_mem[i - 1]; 2014 next_base = mem_base + mem_len; 2015 2016 /* Cut out the 640K hole */ 2017 if (mem_base <= HOLE_640K_START && 2018 next_base > HOLE_640K_START) { 2019 mem_len -= next_base - HOLE_640K_START; 2020 if (mem_len > 0) { 2021 numamem = acpi_data_push(table_data, sizeof *numamem); 2022 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2023 MEM_AFFINITY_ENABLED); 2024 } 2025 2026 /* Check for the rare case: 640K < RAM < 1M */ 2027 if (next_base <= HOLE_640K_END) { 2028 next_base = HOLE_640K_END; 2029 continue; 2030 } 2031 mem_base = HOLE_640K_END; 2032 mem_len = next_base - HOLE_640K_END; 2033 } 2034 2035 /* Cut out the ACPI_PCI hole */ 2036 if (mem_base <= x86ms->below_4g_mem_size && 2037 next_base > x86ms->below_4g_mem_size) { 2038 mem_len -= next_base - x86ms->below_4g_mem_size; 2039 if (mem_len > 0) { 2040 numamem = acpi_data_push(table_data, sizeof *numamem); 2041 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2042 MEM_AFFINITY_ENABLED); 2043 } 2044 mem_base = 1ULL << 32; 2045 mem_len = next_base - x86ms->below_4g_mem_size; 2046 next_base = mem_base + mem_len; 2047 } 2048 2049 if (mem_len > 0) { 2050 numamem = acpi_data_push(table_data, sizeof *numamem); 2051 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2052 MEM_AFFINITY_ENABLED); 2053 } 2054 } 2055 2056 if (machine->nvdimms_state->is_enabled) { 2057 nvdimm_build_srat(table_data); 2058 } 2059 2060 slots = (table_data->len - numa_start) / sizeof *numamem; 2061 for (; slots < pcms->numa_nodes + 2; slots++) { 2062 numamem = acpi_data_push(table_data, sizeof *numamem); 2063 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2064 } 2065 2066 /* 2067 * Entry is required for Windows to enable memory hotplug in OS 2068 * and for Linux to enable SWIOTLB when booted with less than 2069 * 4G of RAM. Windows works better if the entry sets proximity 2070 * to the highest NUMA node in the machine. 2071 * Memory devices may override proximity set by this entry, 2072 * providing _PXM method if necessary. 2073 */ 2074 if (hotplugabble_address_space_size) { 2075 numamem = acpi_data_push(table_data, sizeof *numamem); 2076 build_srat_memory(numamem, machine->device_memory->base, 2077 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2078 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2079 } 2080 2081 build_header(linker, table_data, 2082 (void *)(table_data->data + srat_start), 2083 "SRAT", 2084 table_data->len - srat_start, 1, NULL, NULL); 2085 } 2086 2087 /* 2088 * VT-d spec 8.1 DMA Remapping Reporting Structure 2089 * (version Oct. 2014 or later) 2090 */ 2091 static void 2092 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2093 { 2094 int dmar_start = table_data->len; 2095 2096 AcpiTableDmar *dmar; 2097 AcpiDmarHardwareUnit *drhd; 2098 AcpiDmarRootPortATS *atsr; 2099 uint8_t dmar_flags = 0; 2100 X86IOMMUState *iommu = x86_iommu_get_default(); 2101 AcpiDmarDeviceScope *scope = NULL; 2102 /* Root complex IOAPIC use one path[0] only */ 2103 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2104 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2105 2106 assert(iommu); 2107 if (x86_iommu_ir_supported(iommu)) { 2108 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2109 } 2110 2111 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2112 dmar->host_address_width = intel_iommu->aw_bits - 1; 2113 dmar->flags = dmar_flags; 2114 2115 /* DMAR Remapping Hardware Unit Definition structure */ 2116 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2117 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2118 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2119 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2120 drhd->pci_segment = cpu_to_le16(0); 2121 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2122 2123 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2124 * 8.3.1 (version Oct. 2014 or later). */ 2125 scope = &drhd->scope[0]; 2126 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2127 scope->length = ioapic_scope_size; 2128 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2129 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2130 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2131 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2132 2133 if (iommu->dt_supported) { 2134 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2135 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2136 atsr->length = cpu_to_le16(sizeof(*atsr)); 2137 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2138 atsr->pci_segment = cpu_to_le16(0); 2139 } 2140 2141 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2142 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2143 } 2144 2145 /* 2146 * Windows ACPI Emulated Devices Table 2147 * (Version 1.0 - April 6, 2009) 2148 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2149 * 2150 * Helpful to speedup Windows guests and ignored by others. 2151 */ 2152 static void 2153 build_waet(GArray *table_data, BIOSLinker *linker) 2154 { 2155 int waet_start = table_data->len; 2156 2157 /* WAET header */ 2158 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2159 /* 2160 * Set "ACPI PM timer good" flag. 2161 * 2162 * Tells Windows guests that our ACPI PM timer is reliable in the 2163 * sense that guest can read it only once to obtain a reliable value. 2164 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2165 */ 2166 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2167 2168 build_header(linker, table_data, (void *)(table_data->data + waet_start), 2169 "WAET", table_data->len - waet_start, 1, NULL, NULL); 2170 } 2171 2172 /* 2173 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2174 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2175 */ 2176 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2177 2178 /* 2179 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2180 * necessary for the PCI topology. 2181 */ 2182 static void 2183 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2184 { 2185 GArray *table_data = opaque; 2186 uint32_t entry; 2187 2188 /* "Select" IVHD entry, type 0x2 */ 2189 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2190 build_append_int_noprefix(table_data, entry, 4); 2191 2192 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2193 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2194 uint8_t sec = pci_bus_num(sec_bus); 2195 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2196 2197 if (pci_bus_is_express(sec_bus)) { 2198 /* 2199 * Walk the bus if there are subordinates, otherwise use a range 2200 * to cover an entire leaf bus. We could potentially also use a 2201 * range for traversed buses, but we'd need to take care not to 2202 * create both Select and Range entries covering the same device. 2203 * This is easier and potentially more compact. 2204 * 2205 * An example bare metal system seems to use Select entries for 2206 * root ports without a slot (ie. built-ins) and Range entries 2207 * when there is a slot. The same system also only hard-codes 2208 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2209 * making no effort to support nested bridges. We attempt to 2210 * be more thorough here. 2211 */ 2212 if (sec == sub) { /* leaf bus */ 2213 /* "Start of Range" IVHD entry, type 0x3 */ 2214 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2215 build_append_int_noprefix(table_data, entry, 4); 2216 /* "End of Range" IVHD entry, type 0x4 */ 2217 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2218 build_append_int_noprefix(table_data, entry, 4); 2219 } else { 2220 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2221 } 2222 } else { 2223 /* 2224 * If the secondary bus is conventional, then we need to create an 2225 * Alias range for everything downstream. The range covers the 2226 * first devfn on the secondary bus to the last devfn on the 2227 * subordinate bus. The alias target depends on legacy versus 2228 * express bridges, just as in pci_device_iommu_address_space(). 2229 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2230 */ 2231 uint16_t dev_id_a, dev_id_b; 2232 2233 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2234 2235 if (pci_is_express(dev) && 2236 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2237 dev_id_b = dev_id_a; 2238 } else { 2239 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2240 } 2241 2242 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2243 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2244 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2245 2246 /* "End of Range" IVHD entry, type 0x4 */ 2247 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2248 build_append_int_noprefix(table_data, entry, 4); 2249 } 2250 } 2251 } 2252 2253 /* For all PCI host bridges, walk and insert IVHD entries */ 2254 static int 2255 ivrs_host_bridges(Object *obj, void *opaque) 2256 { 2257 GArray *ivhd_blob = opaque; 2258 2259 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2260 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2261 2262 if (bus) { 2263 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); 2264 } 2265 } 2266 2267 return 0; 2268 } 2269 2270 static void 2271 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2272 { 2273 int ivhd_table_len = 24; 2274 int iommu_start = table_data->len; 2275 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2276 GArray *ivhd_blob = g_array_new(false, true, 1); 2277 2278 /* IVRS header */ 2279 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2280 /* IVinfo - IO virtualization information common to all 2281 * IOMMU units in a system 2282 */ 2283 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2284 /* reserved */ 2285 build_append_int_noprefix(table_data, 0, 8); 2286 2287 /* IVHD definition - type 10h */ 2288 build_append_int_noprefix(table_data, 0x10, 1); 2289 /* virtualization flags */ 2290 build_append_int_noprefix(table_data, 2291 (1UL << 0) | /* HtTunEn */ 2292 (1UL << 4) | /* iotblSup */ 2293 (1UL << 6) | /* PrefSup */ 2294 (1UL << 7), /* PPRSup */ 2295 1); 2296 2297 /* 2298 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2299 * complete set of IVHD entries. Do this into a separate blob so that we 2300 * can calculate the total IVRS table length here and then append the new 2301 * blob further below. Fall back to an entry covering all devices, which 2302 * is sufficient when no aliases are present. 2303 */ 2304 object_child_foreach_recursive(object_get_root(), 2305 ivrs_host_bridges, ivhd_blob); 2306 2307 if (!ivhd_blob->len) { 2308 /* 2309 * Type 1 device entry reporting all devices 2310 * These are 4-byte device entries currently reporting the range of 2311 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2312 */ 2313 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2314 } 2315 2316 ivhd_table_len += ivhd_blob->len; 2317 2318 /* 2319 * When interrupt remapping is supported, we add a special IVHD device 2320 * for type IO-APIC. 2321 */ 2322 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2323 ivhd_table_len += 8; 2324 } 2325 2326 /* IVHD length */ 2327 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2328 /* DeviceID */ 2329 build_append_int_noprefix(table_data, s->devid, 2); 2330 /* Capability offset */ 2331 build_append_int_noprefix(table_data, s->capab_offset, 2); 2332 /* IOMMU base address */ 2333 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2334 /* PCI Segment Group */ 2335 build_append_int_noprefix(table_data, 0, 2); 2336 /* IOMMU info */ 2337 build_append_int_noprefix(table_data, 0, 2); 2338 /* IOMMU Feature Reporting */ 2339 build_append_int_noprefix(table_data, 2340 (48UL << 30) | /* HATS */ 2341 (48UL << 28) | /* GATS */ 2342 (1UL << 2) | /* GTSup */ 2343 (1UL << 6), /* GASup */ 2344 4); 2345 2346 /* IVHD entries as found above */ 2347 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2348 g_array_free(ivhd_blob, TRUE); 2349 2350 /* 2351 * Add a special IVHD device type. 2352 * Refer to spec - Table 95: IVHD device entry type codes 2353 * 2354 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2355 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2356 */ 2357 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2358 build_append_int_noprefix(table_data, 2359 (0x1ull << 56) | /* type IOAPIC */ 2360 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2361 0x48, /* special device */ 2362 8); 2363 } 2364 2365 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2366 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2367 } 2368 2369 typedef 2370 struct AcpiBuildState { 2371 /* Copy of table in RAM (for patching). */ 2372 MemoryRegion *table_mr; 2373 /* Is table patched? */ 2374 uint8_t patched; 2375 void *rsdp; 2376 MemoryRegion *rsdp_mr; 2377 MemoryRegion *linker_mr; 2378 } AcpiBuildState; 2379 2380 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2381 { 2382 Object *pci_host; 2383 QObject *o; 2384 2385 pci_host = acpi_get_i386_pci_host(); 2386 g_assert(pci_host); 2387 2388 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2389 if (!o) { 2390 return false; 2391 } 2392 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2393 qobject_unref(o); 2394 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2395 return false; 2396 } 2397 2398 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2399 assert(o); 2400 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2401 qobject_unref(o); 2402 return true; 2403 } 2404 2405 static 2406 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2407 { 2408 PCMachineState *pcms = PC_MACHINE(machine); 2409 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2410 X86MachineState *x86ms = X86_MACHINE(machine); 2411 GArray *table_offsets; 2412 unsigned facs, dsdt, rsdt, fadt; 2413 AcpiPmInfo pm; 2414 AcpiMiscInfo misc; 2415 AcpiMcfgInfo mcfg; 2416 Range pci_hole, pci_hole64; 2417 uint8_t *u; 2418 size_t aml_len = 0; 2419 GArray *tables_blob = tables->table_data; 2420 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2421 Object *vmgenid_dev; 2422 2423 acpi_get_pm_info(machine, &pm); 2424 acpi_get_misc_info(&misc); 2425 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2426 acpi_get_slic_oem(&slic_oem); 2427 2428 table_offsets = g_array_new(false, true /* clear */, 2429 sizeof(uint32_t)); 2430 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2431 2432 bios_linker_loader_alloc(tables->linker, 2433 ACPI_BUILD_TABLE_FILE, tables_blob, 2434 64 /* Ensure FACS is aligned */, 2435 false /* high memory */); 2436 2437 /* 2438 * FACS is pointed to by FADT. 2439 * We place it first since it's the only table that has alignment 2440 * requirements. 2441 */ 2442 facs = tables_blob->len; 2443 build_facs(tables_blob); 2444 2445 /* DSDT is pointed to by FADT */ 2446 dsdt = tables_blob->len; 2447 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2448 &pci_hole, &pci_hole64, machine); 2449 2450 /* Count the size of the DSDT and SSDT, we will need it for legacy 2451 * sizing of ACPI tables. 2452 */ 2453 aml_len += tables_blob->len - dsdt; 2454 2455 /* ACPI tables pointed to by RSDT */ 2456 fadt = tables_blob->len; 2457 acpi_add_table(table_offsets, tables_blob); 2458 pm.fadt.facs_tbl_offset = &facs; 2459 pm.fadt.dsdt_tbl_offset = &dsdt; 2460 pm.fadt.xdsdt_tbl_offset = &dsdt; 2461 build_fadt(tables_blob, tables->linker, &pm.fadt, 2462 slic_oem.id, slic_oem.table_id); 2463 aml_len += tables_blob->len - fadt; 2464 2465 acpi_add_table(table_offsets, tables_blob); 2466 acpi_build_madt(tables_blob, tables->linker, x86ms, 2467 ACPI_DEVICE_IF(x86ms->acpi_dev), true); 2468 2469 vmgenid_dev = find_vmgenid_dev(); 2470 if (vmgenid_dev) { 2471 acpi_add_table(table_offsets, tables_blob); 2472 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2473 tables->vmgenid, tables->linker); 2474 } 2475 2476 if (misc.has_hpet) { 2477 acpi_add_table(table_offsets, tables_blob); 2478 build_hpet(tables_blob, tables->linker); 2479 } 2480 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2481 if (misc.tpm_version == TPM_VERSION_1_2) { 2482 acpi_add_table(table_offsets, tables_blob); 2483 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2484 } else { /* TPM_VERSION_2_0 */ 2485 acpi_add_table(table_offsets, tables_blob); 2486 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2487 } 2488 } 2489 if (pcms->numa_nodes) { 2490 acpi_add_table(table_offsets, tables_blob); 2491 build_srat(tables_blob, tables->linker, machine); 2492 if (machine->numa_state->have_numa_distance) { 2493 acpi_add_table(table_offsets, tables_blob); 2494 build_slit(tables_blob, tables->linker, machine); 2495 } 2496 if (machine->numa_state->hmat_enabled) { 2497 acpi_add_table(table_offsets, tables_blob); 2498 build_hmat(tables_blob, tables->linker, machine->numa_state); 2499 } 2500 } 2501 if (acpi_get_mcfg(&mcfg)) { 2502 acpi_add_table(table_offsets, tables_blob); 2503 build_mcfg(tables_blob, tables->linker, &mcfg); 2504 } 2505 if (x86_iommu_get_default()) { 2506 IommuType IOMMUType = x86_iommu_get_type(); 2507 if (IOMMUType == TYPE_AMD) { 2508 acpi_add_table(table_offsets, tables_blob); 2509 build_amd_iommu(tables_blob, tables->linker); 2510 } else if (IOMMUType == TYPE_INTEL) { 2511 acpi_add_table(table_offsets, tables_blob); 2512 build_dmar_q35(tables_blob, tables->linker); 2513 } 2514 } 2515 if (machine->nvdimms_state->is_enabled) { 2516 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2517 machine->nvdimms_state, machine->ram_slots); 2518 } 2519 2520 acpi_add_table(table_offsets, tables_blob); 2521 build_waet(tables_blob, tables->linker); 2522 2523 /* Add tables supplied by user (if any) */ 2524 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2525 unsigned len = acpi_table_len(u); 2526 2527 acpi_add_table(table_offsets, tables_blob); 2528 g_array_append_vals(tables_blob, u, len); 2529 } 2530 2531 /* RSDT is pointed to by RSDP */ 2532 rsdt = tables_blob->len; 2533 build_rsdt(tables_blob, tables->linker, table_offsets, 2534 slic_oem.id, slic_oem.table_id); 2535 2536 /* RSDP is in FSEG memory, so allocate it separately */ 2537 { 2538 AcpiRsdpData rsdp_data = { 2539 .revision = 0, 2540 .oem_id = ACPI_BUILD_APPNAME6, 2541 .xsdt_tbl_offset = NULL, 2542 .rsdt_tbl_offset = &rsdt, 2543 }; 2544 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2545 if (!pcmc->rsdp_in_ram) { 2546 /* We used to allocate some extra space for RSDP revision 2 but 2547 * only used the RSDP revision 0 space. The extra bytes were 2548 * zeroed out and not used. 2549 * Here we continue wasting those extra 16 bytes to make sure we 2550 * don't break migration for machine types 2.2 and older due to 2551 * RSDP blob size mismatch. 2552 */ 2553 build_append_int_noprefix(tables->rsdp, 0, 16); 2554 } 2555 } 2556 2557 /* We'll expose it all to Guest so we want to reduce 2558 * chance of size changes. 2559 * 2560 * We used to align the tables to 4k, but of course this would 2561 * too simple to be enough. 4k turned out to be too small an 2562 * alignment very soon, and in fact it is almost impossible to 2563 * keep the table size stable for all (max_cpus, max_memory_slots) 2564 * combinations. So the table size is always 64k for pc-i440fx-2.1 2565 * and we give an error if the table grows beyond that limit. 2566 * 2567 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2568 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2569 * than 2.0 and we can always pad the smaller tables with zeros. We can 2570 * then use the exact size of the 2.0 tables. 2571 * 2572 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2573 */ 2574 if (pcmc->legacy_acpi_table_size) { 2575 /* Subtracting aml_len gives the size of fixed tables. Then add the 2576 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2577 */ 2578 int legacy_aml_len = 2579 pcmc->legacy_acpi_table_size + 2580 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2581 int legacy_table_size = 2582 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2583 ACPI_BUILD_ALIGN_SIZE); 2584 if (tables_blob->len > legacy_table_size) { 2585 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2586 warn_report("ACPI table size %u exceeds %d bytes," 2587 " migration may not work", 2588 tables_blob->len, legacy_table_size); 2589 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2590 " or PCI bridges."); 2591 } 2592 g_array_set_size(tables_blob, legacy_table_size); 2593 } else { 2594 /* Make sure we have a buffer in case we need to resize the tables. */ 2595 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2596 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2597 warn_report("ACPI table size %u exceeds %d bytes," 2598 " migration may not work", 2599 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2600 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2601 " or PCI bridges."); 2602 } 2603 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2604 } 2605 2606 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2607 2608 /* Cleanup memory that's no longer used. */ 2609 g_array_free(table_offsets, true); 2610 } 2611 2612 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2613 { 2614 uint32_t size = acpi_data_len(data); 2615 2616 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2617 memory_region_ram_resize(mr, size, &error_abort); 2618 2619 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2620 memory_region_set_dirty(mr, 0, size); 2621 } 2622 2623 static void acpi_build_update(void *build_opaque) 2624 { 2625 AcpiBuildState *build_state = build_opaque; 2626 AcpiBuildTables tables; 2627 2628 /* No state to update or already patched? Nothing to do. */ 2629 if (!build_state || build_state->patched) { 2630 return; 2631 } 2632 build_state->patched = 1; 2633 2634 acpi_build_tables_init(&tables); 2635 2636 acpi_build(&tables, MACHINE(qdev_get_machine())); 2637 2638 acpi_ram_update(build_state->table_mr, tables.table_data); 2639 2640 if (build_state->rsdp) { 2641 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2642 } else { 2643 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2644 } 2645 2646 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2647 acpi_build_tables_cleanup(&tables, true); 2648 } 2649 2650 static void acpi_build_reset(void *build_opaque) 2651 { 2652 AcpiBuildState *build_state = build_opaque; 2653 build_state->patched = 0; 2654 } 2655 2656 static const VMStateDescription vmstate_acpi_build = { 2657 .name = "acpi_build", 2658 .version_id = 1, 2659 .minimum_version_id = 1, 2660 .fields = (VMStateField[]) { 2661 VMSTATE_UINT8(patched, AcpiBuildState), 2662 VMSTATE_END_OF_LIST() 2663 }, 2664 }; 2665 2666 void acpi_setup(void) 2667 { 2668 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2669 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2670 X86MachineState *x86ms = X86_MACHINE(pcms); 2671 AcpiBuildTables tables; 2672 AcpiBuildState *build_state; 2673 Object *vmgenid_dev; 2674 TPMIf *tpm; 2675 static FwCfgTPMConfig tpm_config; 2676 2677 if (!x86ms->fw_cfg) { 2678 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2679 return; 2680 } 2681 2682 if (!pcms->acpi_build_enabled) { 2683 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2684 return; 2685 } 2686 2687 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2688 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2689 return; 2690 } 2691 2692 build_state = g_malloc0(sizeof *build_state); 2693 2694 acpi_build_tables_init(&tables); 2695 acpi_build(&tables, MACHINE(pcms)); 2696 2697 /* Now expose it all to Guest */ 2698 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2699 build_state, tables.table_data, 2700 ACPI_BUILD_TABLE_FILE, 2701 ACPI_BUILD_TABLE_MAX_SIZE); 2702 assert(build_state->table_mr != NULL); 2703 2704 build_state->linker_mr = 2705 acpi_add_rom_blob(acpi_build_update, build_state, 2706 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 2707 2708 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2709 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2710 2711 tpm = tpm_find(); 2712 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2713 tpm_config = (FwCfgTPMConfig) { 2714 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2715 .tpm_version = tpm_get_version(tpm), 2716 .tpmppi_version = TPM_PPI_VERSION_1_30 2717 }; 2718 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2719 &tpm_config, sizeof tpm_config); 2720 } 2721 2722 vmgenid_dev = find_vmgenid_dev(); 2723 if (vmgenid_dev) { 2724 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2725 tables.vmgenid); 2726 } 2727 2728 if (!pcmc->rsdp_in_ram) { 2729 /* 2730 * Keep for compatibility with old machine types. 2731 * Though RSDP is small, its contents isn't immutable, so 2732 * we'll update it along with the rest of tables on guest access. 2733 */ 2734 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2735 2736 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2737 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2738 acpi_build_update, NULL, build_state, 2739 build_state->rsdp, rsdp_size, true); 2740 build_state->rsdp_mr = NULL; 2741 } else { 2742 build_state->rsdp = NULL; 2743 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2744 build_state, tables.rsdp, 2745 ACPI_BUILD_RSDP_FILE, 0); 2746 } 2747 2748 qemu_register_reset(acpi_build_reset, build_state); 2749 acpi_build_reset(build_state); 2750 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2751 2752 /* Cleanup tables but don't free the memory: we track it 2753 * in build_state. 2754 */ 2755 acpi_build_tables_cleanup(&tables, false); 2756 } 2757