1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "acpi-build.h" 24 #include <stddef.h> 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/osdep.h" 29 #include "qemu/range.h" 30 #include "qemu/error-report.h" 31 #include "hw/pci/pci.h" 32 #include "qom/cpu.h" 33 #include "hw/i386/pc.h" 34 #include "target-i386/cpu.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/acpi/acpi-defs.h" 37 #include "hw/acpi/acpi.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/loader.h" 41 #include "hw/isa/isa.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 46 /* Supported chipsets: */ 47 #include "hw/acpi/piix4.h" 48 #include "hw/acpi/pcihp.h" 49 #include "hw/i386/ich9.h" 50 #include "hw/pci/pci_bus.h" 51 #include "hw/pci-host/q35.h" 52 #include "hw/i386/intel_iommu.h" 53 54 #include "hw/i386/q35-acpi-dsdt.hex" 55 #include "hw/i386/acpi-dsdt.hex" 56 57 #include "hw/acpi/aml-build.h" 58 59 #include "qapi/qmp/qint.h" 60 #include "qom/qom-qobject.h" 61 #include "exec/ram_addr.h" 62 63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 65 * a little bit, there should be plenty of free space since the DSDT 66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 67 */ 68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 69 #define ACPI_BUILD_ALIGN_SIZE 0x1000 70 71 #define ACPI_BUILD_TABLE_SIZE 0x20000 72 73 /* #define DEBUG_ACPI_BUILD */ 74 #ifdef DEBUG_ACPI_BUILD 75 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 76 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 77 #else 78 #define ACPI_BUILD_DPRINTF(fmt, ...) 79 #endif 80 81 typedef struct AcpiCpuInfo { 82 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT); 83 } AcpiCpuInfo; 84 85 typedef struct AcpiMcfgInfo { 86 uint64_t mcfg_base; 87 uint32_t mcfg_size; 88 } AcpiMcfgInfo; 89 90 typedef struct AcpiPmInfo { 91 bool s3_disabled; 92 bool s4_disabled; 93 bool pcihp_bridge_en; 94 uint8_t s4_val; 95 uint16_t sci_int; 96 uint8_t acpi_enable_cmd; 97 uint8_t acpi_disable_cmd; 98 uint32_t gpe0_blk; 99 uint32_t gpe0_blk_len; 100 uint32_t io_base; 101 uint16_t cpu_hp_io_base; 102 uint16_t cpu_hp_io_len; 103 uint16_t mem_hp_io_base; 104 uint16_t mem_hp_io_len; 105 uint16_t pcihp_io_base; 106 uint16_t pcihp_io_len; 107 } AcpiPmInfo; 108 109 typedef struct AcpiMiscInfo { 110 bool has_hpet; 111 bool has_tpm; 112 const unsigned char *dsdt_code; 113 unsigned dsdt_size; 114 uint16_t pvpanic_port; 115 uint16_t applesmc_io_base; 116 } AcpiMiscInfo; 117 118 typedef struct AcpiBuildPciBusHotplugState { 119 GArray *device_table; 120 GArray *notify_table; 121 struct AcpiBuildPciBusHotplugState *parent; 122 bool pcihp_bridge_en; 123 } AcpiBuildPciBusHotplugState; 124 125 static void acpi_get_dsdt(AcpiMiscInfo *info) 126 { 127 Object *piix = piix4_pm_find(); 128 Object *lpc = ich9_lpc_find(); 129 assert(!!piix != !!lpc); 130 131 if (piix) { 132 info->dsdt_code = AcpiDsdtAmlCode; 133 info->dsdt_size = sizeof AcpiDsdtAmlCode; 134 } 135 if (lpc) { 136 info->dsdt_code = Q35AcpiDsdtAmlCode; 137 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; 138 } 139 } 140 141 static 142 int acpi_add_cpu_info(Object *o, void *opaque) 143 { 144 AcpiCpuInfo *cpu = opaque; 145 uint64_t apic_id; 146 147 if (object_dynamic_cast(o, TYPE_CPU)) { 148 apic_id = object_property_get_int(o, "apic-id", NULL); 149 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 150 151 set_bit(apic_id, cpu->found_cpus); 152 } 153 154 object_child_foreach(o, acpi_add_cpu_info, opaque); 155 return 0; 156 } 157 158 static void acpi_get_cpu_info(AcpiCpuInfo *cpu) 159 { 160 Object *root = object_get_root(); 161 162 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus); 163 object_child_foreach(root, acpi_add_cpu_info, cpu); 164 } 165 166 static void acpi_get_pm_info(AcpiPmInfo *pm) 167 { 168 Object *piix = piix4_pm_find(); 169 Object *lpc = ich9_lpc_find(); 170 Object *obj = NULL; 171 QObject *o; 172 173 pm->pcihp_io_base = 0; 174 pm->pcihp_io_len = 0; 175 if (piix) { 176 obj = piix; 177 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 178 pm->pcihp_io_base = 179 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 180 pm->pcihp_io_len = 181 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 182 } 183 if (lpc) { 184 obj = lpc; 185 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 186 } 187 assert(obj); 188 189 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 190 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 191 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 192 193 /* Fill in optional s3/s4 related properties */ 194 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 195 if (o) { 196 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 197 } else { 198 pm->s3_disabled = false; 199 } 200 qobject_decref(o); 201 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 202 if (o) { 203 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 204 } else { 205 pm->s4_disabled = false; 206 } 207 qobject_decref(o); 208 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 209 if (o) { 210 pm->s4_val = qint_get_int(qobject_to_qint(o)); 211 } else { 212 pm->s4_val = false; 213 } 214 qobject_decref(o); 215 216 /* Fill in mandatory properties */ 217 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 218 219 pm->acpi_enable_cmd = object_property_get_int(obj, 220 ACPI_PM_PROP_ACPI_ENABLE_CMD, 221 NULL); 222 pm->acpi_disable_cmd = object_property_get_int(obj, 223 ACPI_PM_PROP_ACPI_DISABLE_CMD, 224 NULL); 225 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 226 NULL); 227 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 228 NULL); 229 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 230 NULL); 231 pm->pcihp_bridge_en = 232 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 233 NULL); 234 } 235 236 static void acpi_get_misc_info(AcpiMiscInfo *info) 237 { 238 info->has_hpet = hpet_find(); 239 info->has_tpm = tpm_find(); 240 info->pvpanic_port = pvpanic_port(); 241 info->applesmc_io_base = applesmc_port(); 242 } 243 244 static void acpi_get_pci_info(PcPciInfo *info) 245 { 246 Object *pci_host; 247 bool ambiguous; 248 249 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 250 g_assert(!ambiguous); 251 g_assert(pci_host); 252 253 info->w32.begin = object_property_get_int(pci_host, 254 PCI_HOST_PROP_PCI_HOLE_START, 255 NULL); 256 info->w32.end = object_property_get_int(pci_host, 257 PCI_HOST_PROP_PCI_HOLE_END, 258 NULL); 259 info->w64.begin = object_property_get_int(pci_host, 260 PCI_HOST_PROP_PCI_HOLE64_START, 261 NULL); 262 info->w64.end = object_property_get_int(pci_host, 263 PCI_HOST_PROP_PCI_HOLE64_END, 264 NULL); 265 } 266 267 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 268 269 static void acpi_align_size(GArray *blob, unsigned align) 270 { 271 /* Align size to multiple of given size. This reduces the chance 272 * we need to change size in the future (breaking cross version migration). 273 */ 274 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 275 } 276 277 /* FACS */ 278 static void 279 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 280 { 281 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 282 memcpy(&facs->signature, "FACS", 4); 283 facs->length = cpu_to_le32(sizeof(*facs)); 284 } 285 286 /* Load chipset information in FADT */ 287 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 288 { 289 fadt->model = 1; 290 fadt->reserved1 = 0; 291 fadt->sci_int = cpu_to_le16(pm->sci_int); 292 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 293 fadt->acpi_enable = pm->acpi_enable_cmd; 294 fadt->acpi_disable = pm->acpi_disable_cmd; 295 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 296 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 297 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 298 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 299 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 300 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 301 fadt->pm1_evt_len = 4; 302 fadt->pm1_cnt_len = 2; 303 fadt->pm_tmr_len = 4; 304 fadt->gpe0_blk_len = pm->gpe0_blk_len; 305 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 306 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 307 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 308 (1 << ACPI_FADT_F_PROC_C1) | 309 (1 << ACPI_FADT_F_SLP_BUTTON) | 310 (1 << ACPI_FADT_F_RTC_S4)); 311 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 312 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 313 * For more than 8 CPUs, "Clustered Logical" mode has to be used 314 */ 315 if (max_cpus > 8) { 316 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 317 } 318 } 319 320 321 /* FADT */ 322 static void 323 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 324 unsigned facs, unsigned dsdt) 325 { 326 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 327 328 fadt->firmware_ctrl = cpu_to_le32(facs); 329 /* FACS address to be filled by Guest linker */ 330 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 331 ACPI_BUILD_TABLE_FILE, 332 table_data, &fadt->firmware_ctrl, 333 sizeof fadt->firmware_ctrl); 334 335 fadt->dsdt = cpu_to_le32(dsdt); 336 /* DSDT address to be filled by Guest linker */ 337 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 338 ACPI_BUILD_TABLE_FILE, 339 table_data, &fadt->dsdt, 340 sizeof fadt->dsdt); 341 342 fadt_setup(fadt, pm); 343 344 build_header(linker, table_data, 345 (void *)fadt, "FACP", sizeof(*fadt), 1); 346 } 347 348 static void 349 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, 350 PcGuestInfo *guest_info) 351 { 352 int madt_start = table_data->len; 353 354 AcpiMultipleApicTable *madt; 355 AcpiMadtIoApic *io_apic; 356 AcpiMadtIntsrcovr *intsrcovr; 357 AcpiMadtLocalNmi *local_nmi; 358 int i; 359 360 madt = acpi_data_push(table_data, sizeof *madt); 361 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 362 madt->flags = cpu_to_le32(1); 363 364 for (i = 0; i < guest_info->apic_id_limit; i++) { 365 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 366 apic->type = ACPI_APIC_PROCESSOR; 367 apic->length = sizeof(*apic); 368 apic->processor_id = i; 369 apic->local_apic_id = i; 370 if (test_bit(i, cpu->found_cpus)) { 371 apic->flags = cpu_to_le32(1); 372 } else { 373 apic->flags = cpu_to_le32(0); 374 } 375 } 376 io_apic = acpi_data_push(table_data, sizeof *io_apic); 377 io_apic->type = ACPI_APIC_IO; 378 io_apic->length = sizeof(*io_apic); 379 #define ACPI_BUILD_IOAPIC_ID 0x0 380 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 381 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 382 io_apic->interrupt = cpu_to_le32(0); 383 384 if (guest_info->apic_xrupt_override) { 385 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 386 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 387 intsrcovr->length = sizeof(*intsrcovr); 388 intsrcovr->source = 0; 389 intsrcovr->gsi = cpu_to_le32(2); 390 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 391 } 392 for (i = 1; i < 16; i++) { 393 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 394 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 395 /* No need for a INT source override structure. */ 396 continue; 397 } 398 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 399 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 400 intsrcovr->length = sizeof(*intsrcovr); 401 intsrcovr->source = i; 402 intsrcovr->gsi = cpu_to_le32(i); 403 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 404 } 405 406 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 407 local_nmi->type = ACPI_APIC_LOCAL_NMI; 408 local_nmi->length = sizeof(*local_nmi); 409 local_nmi->processor_id = 0xff; /* all processors */ 410 local_nmi->flags = cpu_to_le16(0); 411 local_nmi->lint = 1; /* ACPI_LINT1 */ 412 413 build_header(linker, table_data, 414 (void *)(table_data->data + madt_start), "APIC", 415 table_data->len - madt_start, 1); 416 } 417 418 #include "hw/i386/ssdt-tpm.hex" 419 420 /* Assign BSEL property to all buses. In the future, this can be changed 421 * to only assign to buses that support hotplug. 422 */ 423 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 424 { 425 unsigned *bsel_alloc = opaque; 426 unsigned *bus_bsel; 427 428 if (qbus_is_hotpluggable(BUS(bus))) { 429 bus_bsel = g_malloc(sizeof *bus_bsel); 430 431 *bus_bsel = (*bsel_alloc)++; 432 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 433 bus_bsel, NULL); 434 } 435 436 return bsel_alloc; 437 } 438 439 static void acpi_set_pci_info(void) 440 { 441 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 442 unsigned bsel_alloc = 0; 443 444 if (bus) { 445 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 446 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 447 } 448 } 449 450 static void build_append_pcihp_notify_entry(Aml *method, int slot) 451 { 452 Aml *if_ctx; 453 int32_t devfn = PCI_DEVFN(slot, 0); 454 455 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot))); 456 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 457 aml_append(method, if_ctx); 458 } 459 460 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 461 bool pcihp_bridge_en) 462 { 463 Aml *dev, *notify_method, *method; 464 QObject *bsel; 465 PCIBus *sec; 466 int i; 467 468 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 469 if (bsel) { 470 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 471 472 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 473 notify_method = aml_method("DVNT", 2); 474 } 475 476 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 477 DeviceClass *dc; 478 PCIDeviceClass *pc; 479 PCIDevice *pdev = bus->devices[i]; 480 int slot = PCI_SLOT(i); 481 bool hotplug_enabled_dev; 482 bool bridge_in_acpi; 483 484 if (!pdev) { 485 if (bsel) { /* add hotplug slots for non present devices */ 486 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 487 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 488 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 489 method = aml_method("_EJ0", 1); 490 aml_append(method, 491 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 492 ); 493 aml_append(dev, method); 494 aml_append(parent_scope, dev); 495 496 build_append_pcihp_notify_entry(notify_method, slot); 497 } 498 continue; 499 } 500 501 pc = PCI_DEVICE_GET_CLASS(pdev); 502 dc = DEVICE_GET_CLASS(pdev); 503 504 /* When hotplug for bridges is enabled, bridges are 505 * described in ACPI separately (see build_pci_bus_end). 506 * In this case they aren't themselves hot-pluggable. 507 * Hotplugged bridges *are* hot-pluggable. 508 */ 509 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 510 !DEVICE(pdev)->hotplugged; 511 512 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 513 514 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 515 continue; 516 } 517 518 /* start to compose PCI slot descriptor */ 519 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 520 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 521 522 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 523 /* add VGA specific AML methods */ 524 int s3d; 525 526 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 527 s3d = 3; 528 } else { 529 s3d = 0; 530 } 531 532 method = aml_method("_S1D", 0); 533 aml_append(method, aml_return(aml_int(0))); 534 aml_append(dev, method); 535 536 method = aml_method("_S2D", 0); 537 aml_append(method, aml_return(aml_int(0))); 538 aml_append(dev, method); 539 540 method = aml_method("_S3D", 0); 541 aml_append(method, aml_return(aml_int(s3d))); 542 aml_append(dev, method); 543 } else if (hotplug_enabled_dev) { 544 /* add _SUN/_EJ0 to make slot hotpluggable */ 545 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 546 547 method = aml_method("_EJ0", 1); 548 aml_append(method, 549 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 550 ); 551 aml_append(dev, method); 552 553 if (bsel) { 554 build_append_pcihp_notify_entry(notify_method, slot); 555 } 556 } else if (bridge_in_acpi) { 557 /* 558 * device is coldplugged bridge, 559 * add child device descriptions into its scope 560 */ 561 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 562 563 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 564 } 565 /* slot descriptor has been composed, add it into parent context */ 566 aml_append(parent_scope, dev); 567 } 568 569 if (bsel) { 570 aml_append(parent_scope, notify_method); 571 } 572 573 /* Append PCNT method to notify about events on local and child buses. 574 * Add unconditionally for root since DSDT expects it. 575 */ 576 method = aml_method("PCNT", 0); 577 578 /* If bus supports hotplug select it and notify about local events */ 579 if (bsel) { 580 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 581 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 582 aml_append(method, 583 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 584 ); 585 aml_append(method, 586 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 587 ); 588 } 589 590 /* Notify about child bus events in any case */ 591 if (pcihp_bridge_en) { 592 QLIST_FOREACH(sec, &bus->child, sibling) { 593 int32_t devfn = sec->parent_dev->devfn; 594 595 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 596 } 597 } 598 aml_append(parent_scope, method); 599 } 600 601 static void 602 build_ssdt(GArray *table_data, GArray *linker, 603 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, 604 PcPciInfo *pci, PcGuestInfo *guest_info) 605 { 606 MachineState *machine = MACHINE(qdev_get_machine()); 607 uint32_t nr_mem = machine->ram_slots; 608 unsigned acpi_cpus = guest_info->apic_id_limit; 609 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; 610 int i; 611 612 ssdt = init_aml_allocator(); 613 /* The current AML generator can cover the APIC ID range [0..255], 614 * inclusive, for VCPU hotplug. */ 615 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 616 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); 617 618 /* Reserve space for header */ 619 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); 620 621 scope = aml_scope("\\_SB.PCI0"); 622 /* build PCI0._CRS */ 623 crs = aml_resource_template(); 624 aml_append(crs, 625 aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode, 626 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); 627 aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 628 629 aml_append(crs, 630 aml_word_io(aml_min_fixed, aml_max_fixed, 631 aml_pos_decode, aml_entire_range, 632 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 633 aml_append(crs, 634 aml_word_io(aml_min_fixed, aml_max_fixed, 635 aml_pos_decode, aml_entire_range, 636 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); 637 aml_append(crs, 638 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 639 aml_cacheable, aml_ReadWrite, 640 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 641 aml_append(crs, 642 aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 643 aml_non_cacheable, aml_ReadWrite, 644 0, pci->w32.begin, pci->w32.end - 1, 0, 645 pci->w32.end - pci->w32.begin)); 646 if (pci->w64.begin) { 647 aml_append(crs, 648 aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, 649 aml_cacheable, aml_ReadWrite, 650 0, pci->w64.begin, pci->w64.end - 1, 0, 651 pci->w64.end - pci->w64.begin)); 652 } 653 aml_append(scope, aml_name_decl("_CRS", crs)); 654 655 /* reserve GPE0 block resources */ 656 dev = aml_device("GPE0"); 657 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 658 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 659 /* device present, functioning, decoding, not shown in UI */ 660 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 661 crs = aml_resource_template(); 662 aml_append(crs, 663 aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 664 ); 665 aml_append(dev, aml_name_decl("_CRS", crs)); 666 aml_append(scope, dev); 667 668 /* reserve PCIHP resources */ 669 if (pm->pcihp_io_len) { 670 dev = aml_device("PHPR"); 671 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 672 aml_append(dev, 673 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 674 /* device present, functioning, decoding, not shown in UI */ 675 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 676 crs = aml_resource_template(); 677 aml_append(crs, 678 aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 679 pm->pcihp_io_len) 680 ); 681 aml_append(dev, aml_name_decl("_CRS", crs)); 682 aml_append(scope, dev); 683 } 684 aml_append(ssdt, scope); 685 686 /* create S3_ / S4_ / S5_ packages if necessary */ 687 scope = aml_scope("\\"); 688 if (!pm->s3_disabled) { 689 pkg = aml_package(4); 690 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 691 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 692 aml_append(pkg, aml_int(0)); /* reserved */ 693 aml_append(pkg, aml_int(0)); /* reserved */ 694 aml_append(scope, aml_name_decl("_S3", pkg)); 695 } 696 697 if (!pm->s4_disabled) { 698 pkg = aml_package(4); 699 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 700 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 701 aml_append(pkg, aml_int(pm->s4_val)); 702 aml_append(pkg, aml_int(0)); /* reserved */ 703 aml_append(pkg, aml_int(0)); /* reserved */ 704 aml_append(scope, aml_name_decl("_S4", pkg)); 705 } 706 707 pkg = aml_package(4); 708 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 709 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 710 aml_append(pkg, aml_int(0)); /* reserved */ 711 aml_append(pkg, aml_int(0)); /* reserved */ 712 aml_append(scope, aml_name_decl("_S5", pkg)); 713 aml_append(ssdt, scope); 714 715 if (misc->applesmc_io_base) { 716 scope = aml_scope("\\_SB.PCI0.ISA"); 717 dev = aml_device("SMC"); 718 719 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 720 /* device present, functioning, decoding, not shown in UI */ 721 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 722 723 crs = aml_resource_template(); 724 aml_append(crs, 725 aml_io(aml_decode16, misc->applesmc_io_base, misc->applesmc_io_base, 726 0x01, APPLESMC_MAX_DATA_LENGTH) 727 ); 728 aml_append(crs, aml_irq_no_flags(6)); 729 aml_append(dev, aml_name_decl("_CRS", crs)); 730 731 aml_append(scope, dev); 732 aml_append(ssdt, scope); 733 } 734 735 if (misc->pvpanic_port) { 736 scope = aml_scope("\\_SB.PCI0.ISA"); 737 738 dev = aml_device("PEVR"); 739 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 740 741 crs = aml_resource_template(); 742 aml_append(crs, 743 aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 744 ); 745 aml_append(dev, aml_name_decl("_CRS", crs)); 746 747 aml_append(dev, aml_operation_region("PEOR", aml_system_io, 748 misc->pvpanic_port, 1)); 749 field = aml_field("PEOR", aml_byte_acc); 750 aml_append(field, aml_named_field("PEPT", 8)); 751 aml_append(dev, field); 752 753 method = aml_method("RDPT", 0); 754 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 755 aml_append(method, aml_return(aml_local(0))); 756 aml_append(dev, method); 757 758 method = aml_method("WRPT", 1); 759 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 760 aml_append(dev, method); 761 762 aml_append(scope, dev); 763 aml_append(ssdt, scope); 764 } 765 766 sb_scope = aml_scope("_SB"); 767 { 768 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 769 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 770 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 771 aml_append(dev, 772 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 773 ); 774 /* device present, functioning, decoding, not shown in UI */ 775 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 776 crs = aml_resource_template(); 777 aml_append(crs, 778 aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 779 pm->cpu_hp_io_len) 780 ); 781 aml_append(dev, aml_name_decl("_CRS", crs)); 782 aml_append(sb_scope, dev); 783 /* declare CPU hotplug MMIO region and PRS field to access it */ 784 aml_append(sb_scope, aml_operation_region( 785 "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); 786 field = aml_field("PRST", aml_byte_acc); 787 aml_append(field, aml_named_field("PRS", 256)); 788 aml_append(sb_scope, field); 789 790 /* build Processor object for each processor */ 791 for (i = 0; i < acpi_cpus; i++) { 792 dev = aml_processor(i, 0, 0, "CP%.02X", i); 793 794 method = aml_method("_MAT", 0); 795 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); 796 aml_append(dev, method); 797 798 method = aml_method("_STA", 0); 799 aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); 800 aml_append(dev, method); 801 802 method = aml_method("_EJ0", 1); 803 aml_append(method, 804 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) 805 ); 806 aml_append(dev, method); 807 808 aml_append(sb_scope, dev); 809 } 810 811 /* build this code: 812 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 813 */ 814 /* Arg0 = Processor ID = APIC ID */ 815 method = aml_method("NTFY", 2); 816 for (i = 0; i < acpi_cpus; i++) { 817 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 818 aml_append(ifctx, 819 aml_notify(aml_name("CP%.02X", i), aml_arg(1)) 820 ); 821 aml_append(method, ifctx); 822 } 823 aml_append(sb_scope, method); 824 825 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 826 * 827 * Note: The ability to create variable-sized packages was first 828 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 829 * ith up to 255 elements. Windows guests up to win2k8 fail when 830 * VarPackageOp is used. 831 */ 832 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : 833 aml_varpackage(acpi_cpus); 834 835 for (i = 0; i < acpi_cpus; i++) { 836 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; 837 aml_append(pkg, aml_int(b)); 838 } 839 aml_append(sb_scope, aml_name_decl("CPON", pkg)); 840 841 /* build memory devices */ 842 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 843 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); 844 aml_append(scope, 845 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) 846 ); 847 848 crs = aml_resource_template(); 849 aml_append(crs, 850 aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, 851 pm->mem_hp_io_len) 852 ); 853 aml_append(scope, aml_name_decl("_CRS", crs)); 854 855 aml_append(scope, aml_operation_region( 856 stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io, 857 pm->mem_hp_io_base, pm->mem_hp_io_len) 858 ); 859 860 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc); 861 aml_append(field, /* read only */ 862 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); 863 aml_append(field, /* read only */ 864 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); 865 aml_append(field, /* read only */ 866 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); 867 aml_append(field, /* read only */ 868 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); 869 aml_append(field, /* read only */ 870 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); 871 aml_append(scope, field); 872 873 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc); 874 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 875 aml_append(field, /* 1 if enabled, read only */ 876 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); 877 aml_append(field, 878 /*(read) 1 if has a insert event. (write) 1 to clear event */ 879 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); 880 aml_append(scope, field); 881 882 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc); 883 aml_append(field, /* DIMM selector, write only */ 884 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); 885 aml_append(field, /* _OST event code, write only */ 886 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); 887 aml_append(field, /* _OST status code, write only */ 888 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); 889 aml_append(scope, field); 890 891 aml_append(sb_scope, scope); 892 893 for (i = 0; i < nr_mem; i++) { 894 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." 895 const char *s; 896 897 dev = aml_device("MP%02X", i); 898 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 899 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 900 901 method = aml_method("_CRS", 0); 902 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); 903 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 904 aml_append(dev, method); 905 906 method = aml_method("_STA", 0); 907 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); 908 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 909 aml_append(dev, method); 910 911 method = aml_method("_PXM", 0); 912 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); 913 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 914 aml_append(dev, method); 915 916 method = aml_method("_OST", 3); 917 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); 918 aml_append(method, aml_return(aml_call4( 919 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 920 ))); 921 aml_append(dev, method); 922 923 aml_append(sb_scope, dev); 924 } 925 926 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 927 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } 928 */ 929 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2); 930 for (i = 0; i < nr_mem; i++) { 931 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 932 aml_append(ifctx, 933 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 934 ); 935 aml_append(method, ifctx); 936 } 937 aml_append(sb_scope, method); 938 939 { 940 Object *pci_host; 941 PCIBus *bus = NULL; 942 bool ambiguous; 943 944 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 945 if (!ambiguous && pci_host) { 946 bus = PCI_HOST_BRIDGE(pci_host)->bus; 947 } 948 949 if (bus) { 950 Aml *scope = aml_scope("PCI0"); 951 /* Scan all PCI buses. Generate tables to support hotplug. */ 952 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 953 aml_append(sb_scope, scope); 954 } 955 } 956 aml_append(ssdt, sb_scope); 957 } 958 959 /* copy AML table into ACPI tables blob and patch header there */ 960 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); 961 build_header(linker, table_data, 962 (void *)(table_data->data + table_data->len - ssdt->buf->len), 963 "SSDT", ssdt->buf->len, 1); 964 free_aml_allocator(); 965 } 966 967 static void 968 build_hpet(GArray *table_data, GArray *linker) 969 { 970 Acpi20Hpet *hpet; 971 972 hpet = acpi_data_push(table_data, sizeof(*hpet)); 973 /* Note timer_block_id value must be kept in sync with value advertised by 974 * emulated hpet 975 */ 976 hpet->timer_block_id = cpu_to_le32(0x8086a201); 977 hpet->addr.address = cpu_to_le64(HPET_BASE); 978 build_header(linker, table_data, 979 (void *)hpet, "HPET", sizeof(*hpet), 1); 980 } 981 982 static void 983 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 984 { 985 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 986 uint64_t log_area_start_address = acpi_data_len(tcpalog); 987 988 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 989 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 990 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 991 992 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 993 false /* high memory */); 994 995 /* log area start address to be filled by Guest linker */ 996 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 997 ACPI_BUILD_TPMLOG_FILE, 998 table_data, &tcpa->log_area_start_address, 999 sizeof(tcpa->log_area_start_address)); 1000 1001 build_header(linker, table_data, 1002 (void *)tcpa, "TCPA", sizeof(*tcpa), 2); 1003 1004 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1005 } 1006 1007 static void 1008 build_tpm_ssdt(GArray *table_data, GArray *linker) 1009 { 1010 void *tpm_ptr; 1011 1012 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml)); 1013 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml)); 1014 } 1015 1016 typedef enum { 1017 MEM_AFFINITY_NOFLAGS = 0, 1018 MEM_AFFINITY_ENABLED = (1 << 0), 1019 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 1020 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 1021 } MemoryAffinityFlags; 1022 1023 static void 1024 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 1025 uint64_t len, int node, MemoryAffinityFlags flags) 1026 { 1027 numamem->type = ACPI_SRAT_MEMORY; 1028 numamem->length = sizeof(*numamem); 1029 memset(numamem->proximity, 0, 4); 1030 numamem->proximity[0] = node; 1031 numamem->flags = cpu_to_le32(flags); 1032 numamem->base_addr = cpu_to_le64(base); 1033 numamem->range_length = cpu_to_le64(len); 1034 } 1035 1036 static void 1037 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info) 1038 { 1039 AcpiSystemResourceAffinityTable *srat; 1040 AcpiSratProcessorAffinity *core; 1041 AcpiSratMemoryAffinity *numamem; 1042 1043 int i; 1044 uint64_t curnode; 1045 int srat_start, numa_start, slots; 1046 uint64_t mem_len, mem_base, next_base; 1047 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1048 ram_addr_t hotplugabble_address_space_size = 1049 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 1050 NULL); 1051 1052 srat_start = table_data->len; 1053 1054 srat = acpi_data_push(table_data, sizeof *srat); 1055 srat->reserved1 = cpu_to_le32(1); 1056 core = (void *)(srat + 1); 1057 1058 for (i = 0; i < guest_info->apic_id_limit; ++i) { 1059 core = acpi_data_push(table_data, sizeof *core); 1060 core->type = ACPI_SRAT_PROCESSOR; 1061 core->length = sizeof(*core); 1062 core->local_apic_id = i; 1063 curnode = guest_info->node_cpu[i]; 1064 core->proximity_lo = curnode; 1065 memset(core->proximity_hi, 0, 3); 1066 core->local_sapic_eid = 0; 1067 core->flags = cpu_to_le32(1); 1068 } 1069 1070 1071 /* the memory map is a bit tricky, it contains at least one hole 1072 * from 640k-1M and possibly another one from 3.5G-4G. 1073 */ 1074 next_base = 0; 1075 numa_start = table_data->len; 1076 1077 numamem = acpi_data_push(table_data, sizeof *numamem); 1078 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 1079 next_base = 1024 * 1024; 1080 for (i = 1; i < guest_info->numa_nodes + 1; ++i) { 1081 mem_base = next_base; 1082 mem_len = guest_info->node_mem[i - 1]; 1083 if (i == 1) { 1084 mem_len -= 1024 * 1024; 1085 } 1086 next_base = mem_base + mem_len; 1087 1088 /* Cut out the ACPI_PCI hole */ 1089 if (mem_base <= guest_info->ram_size_below_4g && 1090 next_base > guest_info->ram_size_below_4g) { 1091 mem_len -= next_base - guest_info->ram_size_below_4g; 1092 if (mem_len > 0) { 1093 numamem = acpi_data_push(table_data, sizeof *numamem); 1094 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1095 MEM_AFFINITY_ENABLED); 1096 } 1097 mem_base = 1ULL << 32; 1098 mem_len = next_base - guest_info->ram_size_below_4g; 1099 next_base += (1ULL << 32) - guest_info->ram_size_below_4g; 1100 } 1101 numamem = acpi_data_push(table_data, sizeof *numamem); 1102 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1103 MEM_AFFINITY_ENABLED); 1104 } 1105 slots = (table_data->len - numa_start) / sizeof *numamem; 1106 for (; slots < guest_info->numa_nodes + 2; slots++) { 1107 numamem = acpi_data_push(table_data, sizeof *numamem); 1108 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1109 } 1110 1111 /* 1112 * Entry is required for Windows to enable memory hotplug in OS. 1113 * Memory devices may override proximity set by this entry, 1114 * providing _PXM method if necessary. 1115 */ 1116 if (hotplugabble_address_space_size) { 1117 numamem = acpi_data_push(table_data, sizeof *numamem); 1118 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base, 1119 hotplugabble_address_space_size, 0, 1120 MEM_AFFINITY_HOTPLUGGABLE | 1121 MEM_AFFINITY_ENABLED); 1122 } 1123 1124 build_header(linker, table_data, 1125 (void *)(table_data->data + srat_start), 1126 "SRAT", 1127 table_data->len - srat_start, 1); 1128 } 1129 1130 static void 1131 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 1132 { 1133 AcpiTableMcfg *mcfg; 1134 const char *sig; 1135 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 1136 1137 mcfg = acpi_data_push(table_data, len); 1138 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 1139 /* Only a single allocation so no need to play with segments */ 1140 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 1141 mcfg->allocation[0].start_bus_number = 0; 1142 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 1143 1144 /* MCFG is used for ECAM which can be enabled or disabled by guest. 1145 * To avoid table size changes (which create migration issues), 1146 * always create the table even if there are no allocations, 1147 * but set the signature to a reserved value in this case. 1148 * ACPI spec requires OSPMs to ignore such tables. 1149 */ 1150 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 1151 /* Reserved signature: ignored by OSPM */ 1152 sig = "QEMU"; 1153 } else { 1154 sig = "MCFG"; 1155 } 1156 build_header(linker, table_data, (void *)mcfg, sig, len, 1); 1157 } 1158 1159 static void 1160 build_dmar_q35(GArray *table_data, GArray *linker) 1161 { 1162 int dmar_start = table_data->len; 1163 1164 AcpiTableDmar *dmar; 1165 AcpiDmarHardwareUnit *drhd; 1166 1167 dmar = acpi_data_push(table_data, sizeof(*dmar)); 1168 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 1169 dmar->flags = 0; /* No intr_remap for now */ 1170 1171 /* DMAR Remapping Hardware Unit Definition structure */ 1172 drhd = acpi_data_push(table_data, sizeof(*drhd)); 1173 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 1174 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 1175 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 1176 drhd->pci_segment = cpu_to_le16(0); 1177 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 1178 1179 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 1180 "DMAR", table_data->len - dmar_start, 1); 1181 } 1182 1183 static void 1184 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) 1185 { 1186 AcpiTableHeader *dsdt; 1187 1188 assert(misc->dsdt_code && misc->dsdt_size); 1189 1190 dsdt = acpi_data_push(table_data, misc->dsdt_size); 1191 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); 1192 1193 memset(dsdt, 0, sizeof *dsdt); 1194 build_header(linker, table_data, dsdt, "DSDT", 1195 misc->dsdt_size, 1); 1196 } 1197 1198 /* Build final rsdt table */ 1199 static void 1200 build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets) 1201 { 1202 AcpiRsdtDescriptorRev1 *rsdt; 1203 size_t rsdt_len; 1204 int i; 1205 1206 rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len; 1207 rsdt = acpi_data_push(table_data, rsdt_len); 1208 memcpy(rsdt->table_offset_entry, table_offsets->data, 1209 sizeof(uint32_t) * table_offsets->len); 1210 for (i = 0; i < table_offsets->len; ++i) { 1211 /* rsdt->table_offset_entry to be filled by Guest linker */ 1212 bios_linker_loader_add_pointer(linker, 1213 ACPI_BUILD_TABLE_FILE, 1214 ACPI_BUILD_TABLE_FILE, 1215 table_data, &rsdt->table_offset_entry[i], 1216 sizeof(uint32_t)); 1217 } 1218 build_header(linker, table_data, 1219 (void *)rsdt, "RSDT", rsdt_len, 1); 1220 } 1221 1222 static GArray * 1223 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 1224 { 1225 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 1226 1227 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 1228 true /* fseg memory */); 1229 1230 memcpy(&rsdp->signature, "RSD PTR ", 8); 1231 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 1232 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 1233 /* Address to be filled by Guest linker */ 1234 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 1235 ACPI_BUILD_TABLE_FILE, 1236 rsdp_table, &rsdp->rsdt_physical_address, 1237 sizeof rsdp->rsdt_physical_address); 1238 rsdp->checksum = 0; 1239 /* Checksum to be filled by Guest linker */ 1240 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 1241 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum); 1242 1243 return rsdp_table; 1244 } 1245 1246 typedef 1247 struct AcpiBuildState { 1248 /* Copy of table in RAM (for patching). */ 1249 ram_addr_t table_ram; 1250 /* Is table patched? */ 1251 uint8_t patched; 1252 PcGuestInfo *guest_info; 1253 void *rsdp; 1254 ram_addr_t rsdp_ram; 1255 ram_addr_t linker_ram; 1256 } AcpiBuildState; 1257 1258 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 1259 { 1260 Object *pci_host; 1261 QObject *o; 1262 bool ambiguous; 1263 1264 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous); 1265 g_assert(!ambiguous); 1266 g_assert(pci_host); 1267 1268 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 1269 if (!o) { 1270 return false; 1271 } 1272 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 1273 qobject_decref(o); 1274 1275 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 1276 assert(o); 1277 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 1278 qobject_decref(o); 1279 return true; 1280 } 1281 1282 static bool acpi_has_iommu(void) 1283 { 1284 bool ambiguous; 1285 Object *intel_iommu; 1286 1287 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 1288 &ambiguous); 1289 return intel_iommu && !ambiguous; 1290 } 1291 1292 static 1293 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) 1294 { 1295 GArray *table_offsets; 1296 unsigned facs, ssdt, dsdt, rsdt; 1297 AcpiCpuInfo cpu; 1298 AcpiPmInfo pm; 1299 AcpiMiscInfo misc; 1300 AcpiMcfgInfo mcfg; 1301 PcPciInfo pci; 1302 uint8_t *u; 1303 size_t aml_len = 0; 1304 GArray *tables_blob = tables->table_data; 1305 1306 acpi_get_cpu_info(&cpu); 1307 acpi_get_pm_info(&pm); 1308 acpi_get_dsdt(&misc); 1309 acpi_get_misc_info(&misc); 1310 acpi_get_pci_info(&pci); 1311 1312 table_offsets = g_array_new(false, true /* clear */, 1313 sizeof(uint32_t)); 1314 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 1315 1316 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 1317 64 /* Ensure FACS is aligned */, 1318 false /* high memory */); 1319 1320 /* 1321 * FACS is pointed to by FADT. 1322 * We place it first since it's the only table that has alignment 1323 * requirements. 1324 */ 1325 facs = tables_blob->len; 1326 build_facs(tables_blob, tables->linker, guest_info); 1327 1328 /* DSDT is pointed to by FADT */ 1329 dsdt = tables_blob->len; 1330 build_dsdt(tables_blob, tables->linker, &misc); 1331 1332 /* Count the size of the DSDT and SSDT, we will need it for legacy 1333 * sizing of ACPI tables. 1334 */ 1335 aml_len += tables_blob->len - dsdt; 1336 1337 /* ACPI tables pointed to by RSDT */ 1338 acpi_add_table(table_offsets, tables_blob); 1339 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt); 1340 1341 ssdt = tables_blob->len; 1342 acpi_add_table(table_offsets, tables_blob); 1343 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, 1344 guest_info); 1345 aml_len += tables_blob->len - ssdt; 1346 1347 acpi_add_table(table_offsets, tables_blob); 1348 build_madt(tables_blob, tables->linker, &cpu, guest_info); 1349 1350 if (misc.has_hpet) { 1351 acpi_add_table(table_offsets, tables_blob); 1352 build_hpet(tables_blob, tables->linker); 1353 } 1354 if (misc.has_tpm) { 1355 acpi_add_table(table_offsets, tables_blob); 1356 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 1357 1358 acpi_add_table(table_offsets, tables_blob); 1359 build_tpm_ssdt(tables_blob, tables->linker); 1360 } 1361 if (guest_info->numa_nodes) { 1362 acpi_add_table(table_offsets, tables_blob); 1363 build_srat(tables_blob, tables->linker, guest_info); 1364 } 1365 if (acpi_get_mcfg(&mcfg)) { 1366 acpi_add_table(table_offsets, tables_blob); 1367 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 1368 } 1369 if (acpi_has_iommu()) { 1370 acpi_add_table(table_offsets, tables_blob); 1371 build_dmar_q35(tables_blob, tables->linker); 1372 } 1373 1374 /* Add tables supplied by user (if any) */ 1375 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 1376 unsigned len = acpi_table_len(u); 1377 1378 acpi_add_table(table_offsets, tables_blob); 1379 g_array_append_vals(tables_blob, u, len); 1380 } 1381 1382 /* RSDT is pointed to by RSDP */ 1383 rsdt = tables_blob->len; 1384 build_rsdt(tables_blob, tables->linker, table_offsets); 1385 1386 /* RSDP is in FSEG memory, so allocate it separately */ 1387 build_rsdp(tables->rsdp, tables->linker, rsdt); 1388 1389 /* We'll expose it all to Guest so we want to reduce 1390 * chance of size changes. 1391 * 1392 * We used to align the tables to 4k, but of course this would 1393 * too simple to be enough. 4k turned out to be too small an 1394 * alignment very soon, and in fact it is almost impossible to 1395 * keep the table size stable for all (max_cpus, max_memory_slots) 1396 * combinations. So the table size is always 64k for pc-i440fx-2.1 1397 * and we give an error if the table grows beyond that limit. 1398 * 1399 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 1400 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 1401 * than 2.0 and we can always pad the smaller tables with zeros. We can 1402 * then use the exact size of the 2.0 tables. 1403 * 1404 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 1405 */ 1406 if (guest_info->legacy_acpi_table_size) { 1407 /* Subtracting aml_len gives the size of fixed tables. Then add the 1408 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 1409 */ 1410 int legacy_aml_len = 1411 guest_info->legacy_acpi_table_size + 1412 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 1413 int legacy_table_size = 1414 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 1415 ACPI_BUILD_ALIGN_SIZE); 1416 if (tables_blob->len > legacy_table_size) { 1417 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 1418 error_report("Warning: migration may not work."); 1419 } 1420 g_array_set_size(tables_blob, legacy_table_size); 1421 } else { 1422 /* Make sure we have a buffer in case we need to resize the tables. */ 1423 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 1424 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 1425 error_report("Warning: ACPI tables are larger than 64k."); 1426 error_report("Warning: migration may not work."); 1427 error_report("Warning: please remove CPUs, NUMA nodes, " 1428 "memory slots or PCI bridges."); 1429 } 1430 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 1431 } 1432 1433 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 1434 1435 /* Cleanup memory that's no longer used. */ 1436 g_array_free(table_offsets, true); 1437 } 1438 1439 static void acpi_ram_update(ram_addr_t ram, GArray *data) 1440 { 1441 uint32_t size = acpi_data_len(data); 1442 1443 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 1444 qemu_ram_resize(ram, size, &error_abort); 1445 1446 memcpy(qemu_get_ram_ptr(ram), data->data, size); 1447 cpu_physical_memory_set_dirty_range_nocode(ram, size); 1448 } 1449 1450 static void acpi_build_update(void *build_opaque, uint32_t offset) 1451 { 1452 AcpiBuildState *build_state = build_opaque; 1453 AcpiBuildTables tables; 1454 1455 /* No state to update or already patched? Nothing to do. */ 1456 if (!build_state || build_state->patched) { 1457 return; 1458 } 1459 build_state->patched = 1; 1460 1461 acpi_build_tables_init(&tables); 1462 1463 acpi_build(build_state->guest_info, &tables); 1464 1465 acpi_ram_update(build_state->table_ram, tables.table_data); 1466 1467 if (build_state->rsdp) { 1468 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 1469 } else { 1470 acpi_ram_update(build_state->rsdp_ram, tables.rsdp); 1471 } 1472 1473 acpi_ram_update(build_state->linker_ram, tables.linker); 1474 acpi_build_tables_cleanup(&tables, true); 1475 } 1476 1477 static void acpi_build_reset(void *build_opaque) 1478 { 1479 AcpiBuildState *build_state = build_opaque; 1480 build_state->patched = 0; 1481 } 1482 1483 static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob, 1484 const char *name, uint64_t max_size) 1485 { 1486 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 1487 name, acpi_build_update, build_state); 1488 } 1489 1490 static const VMStateDescription vmstate_acpi_build = { 1491 .name = "acpi_build", 1492 .version_id = 1, 1493 .minimum_version_id = 1, 1494 .fields = (VMStateField[]) { 1495 VMSTATE_UINT8(patched, AcpiBuildState), 1496 VMSTATE_END_OF_LIST() 1497 }, 1498 }; 1499 1500 void acpi_setup(PcGuestInfo *guest_info) 1501 { 1502 AcpiBuildTables tables; 1503 AcpiBuildState *build_state; 1504 1505 if (!guest_info->fw_cfg) { 1506 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 1507 return; 1508 } 1509 1510 if (!guest_info->has_acpi_build) { 1511 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 1512 return; 1513 } 1514 1515 if (!acpi_enabled) { 1516 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 1517 return; 1518 } 1519 1520 build_state = g_malloc0(sizeof *build_state); 1521 1522 build_state->guest_info = guest_info; 1523 1524 acpi_set_pci_info(); 1525 1526 acpi_build_tables_init(&tables); 1527 acpi_build(build_state->guest_info, &tables); 1528 1529 /* Now expose it all to Guest */ 1530 build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data, 1531 ACPI_BUILD_TABLE_FILE, 1532 ACPI_BUILD_TABLE_MAX_SIZE); 1533 assert(build_state->table_ram != RAM_ADDR_MAX); 1534 1535 build_state->linker_ram = 1536 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 1537 1538 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 1539 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 1540 1541 if (!guest_info->rsdp_in_ram) { 1542 /* 1543 * Keep for compatibility with old machine types. 1544 * Though RSDP is small, its contents isn't immutable, so 1545 * we'll update it along with the rest of tables on guest access. 1546 */ 1547 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 1548 1549 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 1550 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE, 1551 acpi_build_update, build_state, 1552 build_state->rsdp, rsdp_size); 1553 build_state->rsdp_ram = (ram_addr_t)-1; 1554 } else { 1555 build_state->rsdp = NULL; 1556 build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp, 1557 ACPI_BUILD_RSDP_FILE, 0); 1558 } 1559 1560 qemu_register_reset(acpi_build_reset, build_state); 1561 acpi_build_reset(build_state); 1562 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 1563 1564 /* Cleanup tables but don't free the memory: we track it 1565 * in build_state. 1566 */ 1567 acpi_build_tables_cleanup(&tables, false); 1568 } 1569