1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/misc/pvpanic.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/acpi/acpi-defs.h" 37 #include "hw/acpi/acpi.h" 38 #include "hw/acpi/cpu.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/acpi/bios-linker-loader.h" 41 #include "hw/isa/isa.h" 42 #include "hw/input/i8042.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "sysemu/tpm.h" 45 #include "hw/acpi/tpm.h" 46 #include "hw/acpi/vmgenid.h" 47 #include "hw/acpi/erst.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/piix.h" 59 #include "hw/acpi/pcihp.h" 60 #include "hw/i386/fw_cfg.h" 61 #include "hw/i386/ich9.h" 62 #include "hw/pci/pci_bus.h" 63 #include "hw/pci-host/q35.h" 64 #include "hw/i386/x86-iommu.h" 65 66 #include "hw/acpi/aml-build.h" 67 #include "hw/acpi/utils.h" 68 #include "hw/acpi/pci.h" 69 #include "hw/acpi/cxl.h" 70 71 #include "qom/qom-qobject.h" 72 #include "hw/i386/amd_iommu.h" 73 #include "hw/i386/intel_iommu.h" 74 #include "hw/virtio/virtio-iommu.h" 75 76 #include "hw/acpi/ipmi.h" 77 #include "hw/acpi/hmat.h" 78 #include "hw/acpi/viot.h" 79 #include "hw/acpi/cxl.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 89 #define ACPI_BUILD_ALIGN_SIZE 0x1000 90 91 #define ACPI_BUILD_TABLE_SIZE 0x20000 92 93 /* #define DEBUG_ACPI_BUILD */ 94 #ifdef DEBUG_ACPI_BUILD 95 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 97 #else 98 #define ACPI_BUILD_DPRINTF(fmt, ...) 99 #endif 100 101 typedef struct AcpiPmInfo { 102 bool s3_disabled; 103 bool s4_disabled; 104 bool pcihp_bridge_en; 105 bool smi_on_cpuhp; 106 bool smi_on_cpu_unplug; 107 bool pcihp_root_en; 108 uint8_t s4_val; 109 AcpiFadtData fadt; 110 uint16_t cpu_hp_io_base; 111 uint16_t pcihp_io_base; 112 uint16_t pcihp_io_len; 113 } AcpiPmInfo; 114 115 typedef struct AcpiMiscInfo { 116 bool is_piix4; 117 bool has_hpet; 118 #ifdef CONFIG_TPM 119 TPMVersion tpm_version; 120 #endif 121 const unsigned char *dsdt_code; 122 unsigned dsdt_size; 123 uint16_t pvpanic_port; 124 uint16_t applesmc_io_base; 125 } AcpiMiscInfo; 126 127 typedef struct AcpiBuildPciBusHotplugState { 128 GArray *device_table; 129 GArray *notify_table; 130 struct AcpiBuildPciBusHotplugState *parent; 131 bool pcihp_bridge_en; 132 } AcpiBuildPciBusHotplugState; 133 134 typedef struct FwCfgTPMConfig { 135 uint32_t tpmppi_address; 136 uint8_t tpm_version; 137 uint8_t tpmppi_version; 138 } QEMU_PACKED FwCfgTPMConfig; 139 140 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 141 142 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 143 .space_id = AML_AS_SYSTEM_IO, 144 .address = NVDIMM_ACPI_IO_BASE, 145 .bit_width = NVDIMM_ACPI_IO_LEN << 3 146 }; 147 148 static void init_common_fadt_data(MachineState *ms, Object *o, 149 AcpiFadtData *data) 150 { 151 X86MachineState *x86ms = X86_MACHINE(ms); 152 /* 153 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 154 * behavior for compatibility irrelevant to smm_enabled, which doesn't 155 * comforms to ACPI spec. 156 */ 157 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 158 true : x86_machine_is_smm_enabled(x86ms); 159 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 160 AmlAddressSpace as = AML_AS_SYSTEM_IO; 161 AcpiFadtData fadt = { 162 .rev = 3, 163 .flags = 164 (1 << ACPI_FADT_F_WBINVD) | 165 (1 << ACPI_FADT_F_PROC_C1) | 166 (1 << ACPI_FADT_F_SLP_BUTTON) | 167 (1 << ACPI_FADT_F_RTC_S4) | 168 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 169 /* APIC destination mode ("Flat Logical") has an upper limit of 8 170 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 171 * used 172 */ 173 ((ms->smp.max_cpus > 8) ? 174 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 175 .int_model = 1 /* Multiple APIC */, 176 .rtc_century = RTC_CENTURY, 177 .plvl2_lat = 0xfff /* C2 state not supported */, 178 .plvl3_lat = 0xfff /* C3 state not supported */, 179 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 180 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 181 .acpi_enable_cmd = 182 smm_enabled ? 183 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 184 0, 185 .acpi_disable_cmd = 186 smm_enabled ? 187 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 188 0, 189 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 190 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 191 .address = io + 0x04 }, 192 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 193 .gpe0_blk = { .space_id = as, .bit_width = 194 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 195 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 196 }, 197 }; 198 199 /* 200 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 201 * Flags, bit offset 1 - 8042. 202 */ 203 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 204 205 *data = fadt; 206 } 207 208 static Object *object_resolve_type_unambiguous(const char *typename) 209 { 210 bool ambig; 211 Object *o = object_resolve_path_type("", typename, &ambig); 212 213 if (ambig || !o) { 214 return NULL; 215 } 216 return o; 217 } 218 219 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 220 { 221 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 222 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 223 Object *obj = piix ? piix : lpc; 224 QObject *o; 225 pm->cpu_hp_io_base = 0; 226 pm->pcihp_io_base = 0; 227 pm->pcihp_io_len = 0; 228 pm->smi_on_cpuhp = false; 229 pm->smi_on_cpu_unplug = false; 230 231 assert(obj); 232 init_common_fadt_data(machine, obj, &pm->fadt); 233 if (piix) { 234 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 235 pm->fadt.rev = 1; 236 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 237 } 238 if (lpc) { 239 uint64_t smi_features = object_property_get_uint(lpc, 240 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 241 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 242 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 243 pm->fadt.reset_reg = r; 244 pm->fadt.reset_val = 0xf; 245 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 246 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 247 pm->smi_on_cpuhp = 248 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 249 pm->smi_on_cpu_unplug = 250 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 251 } 252 pm->pcihp_io_base = 253 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 254 pm->pcihp_io_len = 255 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 256 257 /* The above need not be conditional on machine type because the reset port 258 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 259 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 260 261 /* Fill in optional s3/s4 related properties */ 262 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 263 if (o) { 264 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 265 } else { 266 pm->s3_disabled = false; 267 } 268 qobject_unref(o); 269 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 270 if (o) { 271 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 272 } else { 273 pm->s4_disabled = false; 274 } 275 qobject_unref(o); 276 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 277 if (o) { 278 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 279 } else { 280 pm->s4_val = false; 281 } 282 qobject_unref(o); 283 284 pm->pcihp_bridge_en = 285 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 286 NULL); 287 pm->pcihp_root_en = 288 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 289 NULL); 290 } 291 292 static void acpi_get_misc_info(AcpiMiscInfo *info) 293 { 294 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 295 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 296 assert(!!piix != !!lpc); 297 298 if (piix) { 299 info->is_piix4 = true; 300 } 301 if (lpc) { 302 info->is_piix4 = false; 303 } 304 305 info->has_hpet = hpet_find(); 306 #ifdef CONFIG_TPM 307 info->tpm_version = tpm_get_version(tpm_find()); 308 #endif 309 info->pvpanic_port = pvpanic_port(); 310 info->applesmc_io_base = applesmc_port(); 311 } 312 313 /* 314 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 315 * On i386 arch we only have two pci hosts, so we can look only for them. 316 */ 317 Object *acpi_get_i386_pci_host(void) 318 { 319 PCIHostState *host; 320 321 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 322 if (!host) { 323 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 324 } 325 326 return OBJECT(host); 327 } 328 329 static void acpi_get_pci_holes(Range *hole, Range *hole64) 330 { 331 Object *pci_host; 332 333 pci_host = acpi_get_i386_pci_host(); 334 335 if (!pci_host) { 336 return; 337 } 338 339 range_set_bounds1(hole, 340 object_property_get_uint(pci_host, 341 PCI_HOST_PROP_PCI_HOLE_START, 342 NULL), 343 object_property_get_uint(pci_host, 344 PCI_HOST_PROP_PCI_HOLE_END, 345 NULL)); 346 range_set_bounds1(hole64, 347 object_property_get_uint(pci_host, 348 PCI_HOST_PROP_PCI_HOLE64_START, 349 NULL), 350 object_property_get_uint(pci_host, 351 PCI_HOST_PROP_PCI_HOLE64_END, 352 NULL)); 353 } 354 355 static void acpi_align_size(GArray *blob, unsigned align) 356 { 357 /* Align size to multiple of given size. This reduces the chance 358 * we need to change size in the future (breaking cross version migration). 359 */ 360 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 361 } 362 363 /* 364 * ACPI spec 1.0b, 365 * 5.2.6 Firmware ACPI Control Structure 366 */ 367 static void 368 build_facs(GArray *table_data) 369 { 370 const char *sig = "FACS"; 371 const uint8_t reserved[40] = {}; 372 373 g_array_append_vals(table_data, sig, 4); /* Signature */ 374 build_append_int_noprefix(table_data, 64, 4); /* Length */ 375 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 376 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 377 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 378 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 379 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 380 } 381 382 static void build_append_pcihp_notify_entry(Aml *method, int slot) 383 { 384 Aml *if_ctx; 385 int32_t devfn = PCI_DEVFN(slot, 0); 386 387 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 388 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 389 aml_append(method, if_ctx); 390 } 391 392 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 393 bool pcihp_bridge_en) 394 { 395 Aml *dev, *notify_method = NULL, *method; 396 QObject *bsel; 397 PCIBus *sec; 398 int devfn; 399 400 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 401 if (bsel) { 402 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 403 404 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 405 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 406 } 407 408 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 409 DeviceClass *dc; 410 PCIDeviceClass *pc; 411 PCIDevice *pdev = bus->devices[devfn]; 412 int slot = PCI_SLOT(devfn); 413 int func = PCI_FUNC(devfn); 414 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 415 int adr = slot << 16 | func; 416 bool hotplug_enabled_dev; 417 bool bridge_in_acpi; 418 bool cold_plugged_bridge; 419 420 if (!pdev) { 421 /* 422 * add hotplug slots for non present devices. 423 * hotplug is supported only for non-multifunction device 424 * so generate device description only for function 0 425 */ 426 if (bsel && !func) { 427 if (pci_bus_is_express(bus) && slot > 0) { 428 break; 429 } 430 dev = aml_device("S%.02X", devfn); 431 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 432 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 433 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 434 aml_append(method, 435 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 436 ); 437 aml_append(dev, method); 438 method = aml_method("_DSM", 4, AML_SERIALIZED); 439 aml_append(method, 440 aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1), 441 aml_arg(2), aml_arg(3), 442 aml_name("BSEL"), aml_name("_SUN"))) 443 ); 444 aml_append(dev, method); 445 aml_append(parent_scope, dev); 446 447 build_append_pcihp_notify_entry(notify_method, slot); 448 } 449 continue; 450 } 451 452 pc = PCI_DEVICE_GET_CLASS(pdev); 453 dc = DEVICE_GET_CLASS(pdev); 454 455 /* 456 * Cold plugged bridges aren't themselves hot-pluggable. 457 * Hotplugged bridges *are* hot-pluggable. 458 */ 459 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 460 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 461 462 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 463 464 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 465 continue; 466 } 467 468 /* 469 * allow describing coldplugged bridges in ACPI even if they are not 470 * on function 0, as they are not unpluggable, for all other devices 471 * generate description only for function 0 per slot 472 */ 473 if (func && !bridge_in_acpi) { 474 continue; 475 } 476 477 /* start to compose PCI device descriptor */ 478 dev = aml_device("S%.02X", devfn); 479 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 480 481 if (bsel) { 482 /* 483 * Can't declare _SUN here for every device as it changes 'slot' 484 * enumeration order in linux kernel, so use another variable for it 485 */ 486 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 487 method = aml_method("_DSM", 4, AML_SERIALIZED); 488 aml_append(method, aml_return( 489 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2), 490 aml_arg(3), aml_name("BSEL"), aml_name("ASUN")) 491 )); 492 aml_append(dev, method); 493 } 494 495 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 496 /* add VGA specific AML methods */ 497 int s3d; 498 499 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 500 s3d = 3; 501 } else { 502 s3d = 0; 503 } 504 505 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 506 aml_append(method, aml_return(aml_int(0))); 507 aml_append(dev, method); 508 509 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 510 aml_append(method, aml_return(aml_int(0))); 511 aml_append(dev, method); 512 513 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 514 aml_append(method, aml_return(aml_int(s3d))); 515 aml_append(dev, method); 516 } else if (hotplug_enabled_dev) { 517 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 518 /* add _EJ0 to make slot hotpluggable */ 519 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 520 aml_append(method, 521 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 522 ); 523 aml_append(dev, method); 524 525 if (bsel) { 526 build_append_pcihp_notify_entry(notify_method, slot); 527 } 528 } else if (bridge_in_acpi) { 529 /* 530 * device is coldplugged bridge, 531 * add child device descriptions into its scope 532 */ 533 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 534 535 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 536 } 537 /* device descriptor has been composed, add it into parent context */ 538 aml_append(parent_scope, dev); 539 } 540 541 if (bsel) { 542 aml_append(parent_scope, notify_method); 543 } 544 545 /* Append PCNT method to notify about events on local and child buses. 546 * Add this method for root bus only when hotplug is enabled since DSDT 547 * expects it. 548 */ 549 if (bsel || pcihp_bridge_en) { 550 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 551 552 /* If bus supports hotplug select it and notify about local events */ 553 if (bsel) { 554 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 555 556 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 557 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 558 aml_int(1))); /* Device Check */ 559 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 560 aml_int(3))); /* Eject Request */ 561 } 562 563 /* Notify about child bus events in any case */ 564 if (pcihp_bridge_en) { 565 QLIST_FOREACH(sec, &bus->child, sibling) { 566 if (pci_bus_is_root(sec)) { 567 continue; 568 } 569 570 aml_append(method, aml_name("^S%.02X.PCNT", 571 sec->parent_dev->devfn)); 572 } 573 } 574 575 aml_append(parent_scope, method); 576 } 577 qobject_unref(bsel); 578 } 579 580 Aml *aml_pci_device_dsm(void) 581 { 582 Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx; 583 Aml *acpi_index = aml_local(0); 584 Aml *zero = aml_int(0); 585 Aml *bnum = aml_arg(4); 586 Aml *func = aml_arg(2); 587 Aml *rev = aml_arg(1); 588 Aml *sunum = aml_arg(5); 589 590 method = aml_method("PDSM", 6, AML_SERIALIZED); 591 592 /* 593 * PCI Firmware Specification 3.1 594 * 4.6. _DSM Definitions for PCI 595 */ 596 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 597 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 598 { 599 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 600 ifctx1 = aml_if(aml_equal(func, zero)); 601 { 602 uint8_t byte_list[1]; 603 604 ifctx2 = aml_if(aml_equal(rev, aml_int(2))); 605 { 606 /* 607 * advertise function 7 if device has acpi-index 608 * acpi_index values: 609 * 0: not present (default value) 610 * FFFFFFFF: not supported (old QEMU without PIDX reg) 611 * other: device's acpi-index 612 */ 613 ifctx3 = aml_if(aml_lnot( 614 aml_or(aml_equal(acpi_index, zero), 615 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 616 )); 617 { 618 byte_list[0] = 619 1 /* have supported functions */ | 620 1 << 7 /* support for function 7 */ 621 ; 622 aml_append(ifctx3, aml_return(aml_buffer(1, byte_list))); 623 } 624 aml_append(ifctx2, ifctx3); 625 } 626 aml_append(ifctx1, ifctx2); 627 628 byte_list[0] = 0; /* nothing supported */ 629 aml_append(ifctx1, aml_return(aml_buffer(1, byte_list))); 630 } 631 aml_append(ifctx, ifctx1); 632 elsectx = aml_else(); 633 /* 634 * PCI Firmware Specification 3.1 635 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 636 * Operating Systems 637 */ 638 ifctx1 = aml_if(aml_equal(func, aml_int(7))); 639 { 640 Aml *pkg = aml_package(2); 641 Aml *ret = aml_local(1); 642 643 aml_append(pkg, zero); 644 /* 645 * optional, if not impl. should return null string 646 */ 647 aml_append(pkg, aml_string("%s", "")); 648 aml_append(ifctx1, aml_store(pkg, ret)); 649 /* 650 * update acpi-index to actual value 651 */ 652 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); 653 aml_append(ifctx1, aml_return(ret)); 654 } 655 aml_append(elsectx, ifctx1); 656 aml_append(ifctx, elsectx); 657 } 658 aml_append(method, ifctx); 659 return method; 660 } 661 662 /** 663 * build_prt_entry: 664 * @link_name: link name for PCI route entry 665 * 666 * build AML package containing a PCI route entry for @link_name 667 */ 668 static Aml *build_prt_entry(const char *link_name) 669 { 670 Aml *a_zero = aml_int(0); 671 Aml *pkg = aml_package(4); 672 aml_append(pkg, a_zero); 673 aml_append(pkg, a_zero); 674 aml_append(pkg, aml_name("%s", link_name)); 675 aml_append(pkg, a_zero); 676 return pkg; 677 } 678 679 /* 680 * initialize_route - Initialize the interrupt routing rule 681 * through a specific LINK: 682 * if (lnk_idx == idx) 683 * route using link 'link_name' 684 */ 685 static Aml *initialize_route(Aml *route, const char *link_name, 686 Aml *lnk_idx, int idx) 687 { 688 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 689 Aml *pkg = build_prt_entry(link_name); 690 691 aml_append(if_ctx, aml_store(pkg, route)); 692 693 return if_ctx; 694 } 695 696 /* 697 * build_prt - Define interrupt rounting rules 698 * 699 * Returns an array of 128 routes, one for each device, 700 * based on device location. 701 * The main goal is to equaly distribute the interrupts 702 * over the 4 existing ACPI links (works only for i440fx). 703 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 704 * 705 */ 706 static Aml *build_prt(bool is_pci0_prt) 707 { 708 Aml *method, *while_ctx, *pin, *res; 709 710 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 711 res = aml_local(0); 712 pin = aml_local(1); 713 aml_append(method, aml_store(aml_package(128), res)); 714 aml_append(method, aml_store(aml_int(0), pin)); 715 716 /* while (pin < 128) */ 717 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 718 { 719 Aml *slot = aml_local(2); 720 Aml *lnk_idx = aml_local(3); 721 Aml *route = aml_local(4); 722 723 /* slot = pin >> 2 */ 724 aml_append(while_ctx, 725 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 726 /* lnk_idx = (slot + pin) & 3 */ 727 aml_append(while_ctx, 728 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 729 lnk_idx)); 730 731 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 732 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 733 if (is_pci0_prt) { 734 Aml *if_device_1, *if_pin_4, *else_pin_4; 735 736 /* device 1 is the power-management device, needs SCI */ 737 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 738 { 739 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 740 { 741 aml_append(if_pin_4, 742 aml_store(build_prt_entry("LNKS"), route)); 743 } 744 aml_append(if_device_1, if_pin_4); 745 else_pin_4 = aml_else(); 746 { 747 aml_append(else_pin_4, 748 aml_store(build_prt_entry("LNKA"), route)); 749 } 750 aml_append(if_device_1, else_pin_4); 751 } 752 aml_append(while_ctx, if_device_1); 753 } else { 754 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 755 } 756 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 757 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 758 759 /* route[0] = 0x[slot]FFFF */ 760 aml_append(while_ctx, 761 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 762 NULL), 763 aml_index(route, aml_int(0)))); 764 /* route[1] = pin & 3 */ 765 aml_append(while_ctx, 766 aml_store(aml_and(pin, aml_int(3), NULL), 767 aml_index(route, aml_int(1)))); 768 /* res[pin] = route */ 769 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 770 /* pin++ */ 771 aml_append(while_ctx, aml_increment(pin)); 772 } 773 aml_append(method, while_ctx); 774 /* return res*/ 775 aml_append(method, aml_return(res)); 776 777 return method; 778 } 779 780 static void build_hpet_aml(Aml *table) 781 { 782 Aml *crs; 783 Aml *field; 784 Aml *method; 785 Aml *if_ctx; 786 Aml *scope = aml_scope("_SB"); 787 Aml *dev = aml_device("HPET"); 788 Aml *zero = aml_int(0); 789 Aml *id = aml_local(0); 790 Aml *period = aml_local(1); 791 792 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 793 aml_append(dev, aml_name_decl("_UID", zero)); 794 795 aml_append(dev, 796 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 797 HPET_LEN)); 798 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 799 aml_append(field, aml_named_field("VEND", 32)); 800 aml_append(field, aml_named_field("PRD", 32)); 801 aml_append(dev, field); 802 803 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 804 aml_append(method, aml_store(aml_name("VEND"), id)); 805 aml_append(method, aml_store(aml_name("PRD"), period)); 806 aml_append(method, aml_shiftright(id, aml_int(16), id)); 807 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 808 aml_equal(id, aml_int(0xffff)))); 809 { 810 aml_append(if_ctx, aml_return(zero)); 811 } 812 aml_append(method, if_ctx); 813 814 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 815 aml_lgreater(period, aml_int(100000000)))); 816 { 817 aml_append(if_ctx, aml_return(zero)); 818 } 819 aml_append(method, if_ctx); 820 821 aml_append(method, aml_return(aml_int(0x0F))); 822 aml_append(dev, method); 823 824 crs = aml_resource_template(); 825 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 826 aml_append(dev, aml_name_decl("_CRS", crs)); 827 828 aml_append(scope, dev); 829 aml_append(table, scope); 830 } 831 832 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 833 { 834 Aml *dev; 835 Aml *method; 836 Aml *crs; 837 838 dev = aml_device("VMBS"); 839 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 840 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 841 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 842 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 843 844 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 845 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 846 aml_name("STA"))); 847 aml_append(dev, method); 848 849 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 850 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 851 aml_name("STA"))); 852 aml_append(dev, method); 853 854 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 855 aml_append(method, aml_return(aml_name("STA"))); 856 aml_append(dev, method); 857 858 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 859 860 crs = aml_resource_template(); 861 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 862 aml_append(dev, aml_name_decl("_CRS", crs)); 863 864 return dev; 865 } 866 867 static void build_isa_devices_aml(Aml *table) 868 { 869 bool ambiguous; 870 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 871 Aml *scope; 872 873 assert(obj && !ambiguous); 874 875 scope = aml_scope("_SB.PCI0.ISA"); 876 build_acpi_ipmi_devices(scope, BUS(obj)); 877 isa_build_aml(ISA_BUS(obj), scope); 878 879 aml_append(table, scope); 880 } 881 882 static void build_dbg_aml(Aml *table) 883 { 884 Aml *field; 885 Aml *method; 886 Aml *while_ctx; 887 Aml *scope = aml_scope("\\"); 888 Aml *buf = aml_local(0); 889 Aml *len = aml_local(1); 890 Aml *idx = aml_local(2); 891 892 aml_append(scope, 893 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 894 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 895 aml_append(field, aml_named_field("DBGB", 8)); 896 aml_append(scope, field); 897 898 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 899 900 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 901 aml_append(method, aml_to_buffer(buf, buf)); 902 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 903 aml_append(method, aml_store(aml_int(0), idx)); 904 905 while_ctx = aml_while(aml_lless(idx, len)); 906 aml_append(while_ctx, 907 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 908 aml_append(while_ctx, aml_increment(idx)); 909 aml_append(method, while_ctx); 910 911 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 912 aml_append(scope, method); 913 914 aml_append(table, scope); 915 } 916 917 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 918 { 919 Aml *dev; 920 Aml *crs; 921 Aml *method; 922 uint32_t irqs[] = {5, 10, 11}; 923 924 dev = aml_device("%s", name); 925 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 926 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 927 928 crs = aml_resource_template(); 929 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 930 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 931 aml_append(dev, aml_name_decl("_PRS", crs)); 932 933 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 934 aml_append(method, aml_return(aml_call1("IQST", reg))); 935 aml_append(dev, method); 936 937 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 938 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 939 aml_append(dev, method); 940 941 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 942 aml_append(method, aml_return(aml_call1("IQCR", reg))); 943 aml_append(dev, method); 944 945 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 946 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 947 aml_append(method, aml_store(aml_name("PRRI"), reg)); 948 aml_append(dev, method); 949 950 return dev; 951 } 952 953 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 954 { 955 Aml *dev; 956 Aml *crs; 957 Aml *method; 958 uint32_t irqs; 959 960 dev = aml_device("%s", name); 961 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 962 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 963 964 crs = aml_resource_template(); 965 irqs = gsi; 966 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 967 AML_SHARED, &irqs, 1)); 968 aml_append(dev, aml_name_decl("_PRS", crs)); 969 970 aml_append(dev, aml_name_decl("_CRS", crs)); 971 972 /* 973 * _DIS can be no-op because the interrupt cannot be disabled. 974 */ 975 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 976 aml_append(dev, method); 977 978 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 979 aml_append(dev, method); 980 981 return dev; 982 } 983 984 /* _CRS method - get current settings */ 985 static Aml *build_iqcr_method(bool is_piix4) 986 { 987 Aml *if_ctx; 988 uint32_t irqs; 989 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 990 Aml *crs = aml_resource_template(); 991 992 irqs = 0; 993 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 994 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 995 aml_append(method, aml_name_decl("PRR0", crs)); 996 997 aml_append(method, 998 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 999 1000 if (is_piix4) { 1001 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1002 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1003 aml_append(method, if_ctx); 1004 } else { 1005 aml_append(method, 1006 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1007 aml_name("PRRI"))); 1008 } 1009 1010 aml_append(method, aml_return(aml_name("PRR0"))); 1011 return method; 1012 } 1013 1014 /* _STA method - get status */ 1015 static Aml *build_irq_status_method(void) 1016 { 1017 Aml *if_ctx; 1018 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1019 1020 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1021 aml_append(if_ctx, aml_return(aml_int(0x09))); 1022 aml_append(method, if_ctx); 1023 aml_append(method, aml_return(aml_int(0x0B))); 1024 return method; 1025 } 1026 1027 static void build_piix4_pci0_int(Aml *table) 1028 { 1029 Aml *dev; 1030 Aml *crs; 1031 Aml *field; 1032 Aml *method; 1033 uint32_t irqs; 1034 Aml *sb_scope = aml_scope("_SB"); 1035 Aml *pci0_scope = aml_scope("PCI0"); 1036 1037 aml_append(pci0_scope, build_prt(true)); 1038 aml_append(sb_scope, pci0_scope); 1039 1040 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1041 aml_append(field, aml_named_field("PRQ0", 8)); 1042 aml_append(field, aml_named_field("PRQ1", 8)); 1043 aml_append(field, aml_named_field("PRQ2", 8)); 1044 aml_append(field, aml_named_field("PRQ3", 8)); 1045 aml_append(sb_scope, field); 1046 1047 aml_append(sb_scope, build_irq_status_method()); 1048 aml_append(sb_scope, build_iqcr_method(true)); 1049 1050 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1051 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1052 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1053 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1054 1055 dev = aml_device("LNKS"); 1056 { 1057 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1058 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1059 1060 crs = aml_resource_template(); 1061 irqs = 9; 1062 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1063 AML_ACTIVE_HIGH, AML_SHARED, 1064 &irqs, 1)); 1065 aml_append(dev, aml_name_decl("_PRS", crs)); 1066 1067 /* The SCI cannot be disabled and is always attached to GSI 9, 1068 * so these are no-ops. We only need this link to override the 1069 * polarity to active high and match the content of the MADT. 1070 */ 1071 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1072 aml_append(method, aml_return(aml_int(0x0b))); 1073 aml_append(dev, method); 1074 1075 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1076 aml_append(dev, method); 1077 1078 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1079 aml_append(method, aml_return(aml_name("_PRS"))); 1080 aml_append(dev, method); 1081 1082 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1083 aml_append(dev, method); 1084 } 1085 aml_append(sb_scope, dev); 1086 1087 aml_append(table, sb_scope); 1088 } 1089 1090 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1091 { 1092 int i; 1093 int head; 1094 Aml *pkg; 1095 char base = name[3] < 'E' ? 'A' : 'E'; 1096 char *s = g_strdup(name); 1097 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1098 1099 assert(strlen(s) == 4); 1100 1101 head = name[3] - base; 1102 for (i = 0; i < 4; i++) { 1103 if (head + i > 3) { 1104 head = i * -1; 1105 } 1106 s[3] = base + head + i; 1107 pkg = aml_package(4); 1108 aml_append(pkg, a_nr); 1109 aml_append(pkg, aml_int(i)); 1110 aml_append(pkg, aml_name("%s", s)); 1111 aml_append(pkg, aml_int(0)); 1112 aml_append(ctx, pkg); 1113 } 1114 g_free(s); 1115 } 1116 1117 static Aml *build_q35_routing_table(const char *str) 1118 { 1119 int i; 1120 Aml *pkg; 1121 char *name = g_strdup_printf("%s ", str); 1122 1123 pkg = aml_package(128); 1124 for (i = 0; i < 0x18; i++) { 1125 name[3] = 'E' + (i & 0x3); 1126 append_q35_prt_entry(pkg, i, name); 1127 } 1128 1129 name[3] = 'E'; 1130 append_q35_prt_entry(pkg, 0x18, name); 1131 1132 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1133 for (i = 0x0019; i < 0x1e; i++) { 1134 name[3] = 'A'; 1135 append_q35_prt_entry(pkg, i, name); 1136 } 1137 1138 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1139 name[3] = 'E'; 1140 append_q35_prt_entry(pkg, 0x1e, name); 1141 name[3] = 'A'; 1142 append_q35_prt_entry(pkg, 0x1f, name); 1143 1144 g_free(name); 1145 return pkg; 1146 } 1147 1148 static void build_q35_pci0_int(Aml *table) 1149 { 1150 Aml *field; 1151 Aml *method; 1152 Aml *sb_scope = aml_scope("_SB"); 1153 Aml *pci0_scope = aml_scope("PCI0"); 1154 1155 /* Zero => PIC mode, One => APIC Mode */ 1156 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1157 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1158 { 1159 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1160 } 1161 aml_append(table, method); 1162 1163 aml_append(pci0_scope, 1164 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1165 aml_append(pci0_scope, 1166 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1167 1168 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1169 { 1170 Aml *if_ctx; 1171 Aml *else_ctx; 1172 1173 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1174 section 6.2.8.1 */ 1175 /* Note: we provide the same info as the PCI routing 1176 table of the Bochs BIOS */ 1177 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1178 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1179 aml_append(method, if_ctx); 1180 else_ctx = aml_else(); 1181 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1182 aml_append(method, else_ctx); 1183 } 1184 aml_append(pci0_scope, method); 1185 aml_append(sb_scope, pci0_scope); 1186 1187 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1188 aml_append(field, aml_named_field("PRQA", 8)); 1189 aml_append(field, aml_named_field("PRQB", 8)); 1190 aml_append(field, aml_named_field("PRQC", 8)); 1191 aml_append(field, aml_named_field("PRQD", 8)); 1192 aml_append(field, aml_reserved_field(0x20)); 1193 aml_append(field, aml_named_field("PRQE", 8)); 1194 aml_append(field, aml_named_field("PRQF", 8)); 1195 aml_append(field, aml_named_field("PRQG", 8)); 1196 aml_append(field, aml_named_field("PRQH", 8)); 1197 aml_append(sb_scope, field); 1198 1199 aml_append(sb_scope, build_irq_status_method()); 1200 aml_append(sb_scope, build_iqcr_method(false)); 1201 1202 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1203 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1204 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1205 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1206 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1207 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1208 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1209 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1210 1211 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1212 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1213 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1214 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1215 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1216 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1217 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1218 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1219 1220 aml_append(table, sb_scope); 1221 } 1222 1223 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1224 { 1225 Aml *dev; 1226 Aml *resource_template; 1227 1228 /* DRAM controller */ 1229 dev = aml_device("DRAC"); 1230 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1231 1232 resource_template = aml_resource_template(); 1233 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1234 aml_append(resource_template, 1235 aml_qword_memory(AML_POS_DECODE, 1236 AML_MIN_FIXED, 1237 AML_MAX_FIXED, 1238 AML_NON_CACHEABLE, 1239 AML_READ_WRITE, 1240 0x0000000000000000, 1241 mcfg->base, 1242 mcfg->base + mcfg->size - 1, 1243 0x0000000000000000, 1244 mcfg->size)); 1245 } else { 1246 aml_append(resource_template, 1247 aml_dword_memory(AML_POS_DECODE, 1248 AML_MIN_FIXED, 1249 AML_MAX_FIXED, 1250 AML_NON_CACHEABLE, 1251 AML_READ_WRITE, 1252 0x0000000000000000, 1253 mcfg->base, 1254 mcfg->base + mcfg->size - 1, 1255 0x0000000000000000, 1256 mcfg->size)); 1257 } 1258 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1259 1260 return dev; 1261 } 1262 1263 static void build_q35_isa_bridge(Aml *table) 1264 { 1265 Aml *dev; 1266 Aml *scope; 1267 1268 scope = aml_scope("_SB.PCI0"); 1269 dev = aml_device("ISA"); 1270 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1271 1272 /* ICH9 PCI to ISA irq remapping */ 1273 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1274 aml_int(0x60), 0x0C)); 1275 1276 aml_append(scope, dev); 1277 aml_append(table, scope); 1278 } 1279 1280 static void build_piix4_isa_bridge(Aml *table) 1281 { 1282 Aml *dev; 1283 Aml *scope; 1284 1285 scope = aml_scope("_SB.PCI0"); 1286 dev = aml_device("ISA"); 1287 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1288 1289 /* PIIX PCI to ISA irq remapping */ 1290 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1291 aml_int(0x60), 0x04)); 1292 1293 aml_append(scope, dev); 1294 aml_append(table, scope); 1295 } 1296 1297 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1298 { 1299 Aml *scope; 1300 Aml *field; 1301 Aml *method; 1302 1303 scope = aml_scope("_SB.PCI0"); 1304 1305 aml_append(scope, 1306 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1307 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1308 aml_append(field, aml_named_field("PCIU", 32)); 1309 aml_append(field, aml_named_field("PCID", 32)); 1310 aml_append(scope, field); 1311 1312 aml_append(scope, 1313 aml_operation_region("SEJ", AML_SYSTEM_IO, 1314 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1315 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1316 aml_append(field, aml_named_field("B0EJ", 32)); 1317 aml_append(scope, field); 1318 1319 aml_append(scope, 1320 aml_operation_region("BNMR", AML_SYSTEM_IO, 1321 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1322 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1323 aml_append(field, aml_named_field("BNUM", 32)); 1324 aml_append(field, aml_named_field("PIDX", 32)); 1325 aml_append(scope, field); 1326 1327 aml_append(scope, aml_mutex("BLCK", 0)); 1328 1329 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1330 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1331 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1332 aml_append(method, 1333 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1334 aml_append(method, aml_release(aml_name("BLCK"))); 1335 aml_append(method, aml_return(aml_int(0))); 1336 aml_append(scope, method); 1337 1338 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1339 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1340 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1341 aml_append(method, 1342 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1343 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1344 aml_append(method, aml_release(aml_name("BLCK"))); 1345 aml_append(method, aml_return(aml_local(0))); 1346 aml_append(scope, method); 1347 1348 aml_append(scope, aml_pci_device_dsm()); 1349 1350 aml_append(table, scope); 1351 } 1352 1353 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1354 { 1355 Aml *if_ctx; 1356 Aml *if_ctx2; 1357 Aml *else_ctx; 1358 Aml *method; 1359 Aml *a_cwd1 = aml_name("CDW1"); 1360 Aml *a_ctrl = aml_local(0); 1361 1362 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1363 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1364 1365 if_ctx = aml_if(aml_equal( 1366 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1367 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1368 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1369 1370 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1371 1372 /* 1373 * Always allow native PME, AER (no dependencies) 1374 * Allow SHPC (PCI bridges can have SHPC controller) 1375 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1376 */ 1377 aml_append(if_ctx, aml_and(a_ctrl, 1378 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1379 1380 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1381 /* Unknown revision */ 1382 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1383 aml_append(if_ctx, if_ctx2); 1384 1385 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1386 /* Capabilities bits were masked */ 1387 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1388 aml_append(if_ctx, if_ctx2); 1389 1390 /* Update DWORD3 in the buffer */ 1391 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1392 aml_append(method, if_ctx); 1393 1394 else_ctx = aml_else(); 1395 /* Unrecognized UUID */ 1396 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1397 aml_append(method, else_ctx); 1398 1399 aml_append(method, aml_return(aml_arg(3))); 1400 return method; 1401 } 1402 1403 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1404 { 1405 Aml *scope = aml_scope("_SB.PCI0"); 1406 Aml *dev = aml_device("SMB0"); 1407 1408 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1409 build_acpi_ipmi_devices(dev, BUS(smbus)); 1410 aml_append(scope, dev); 1411 aml_append(table, scope); 1412 } 1413 1414 static void build_acpi0017(Aml *table) 1415 { 1416 Aml *dev, *scope, *method; 1417 1418 scope = aml_scope("_SB"); 1419 dev = aml_device("CXLM"); 1420 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1421 1422 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1423 aml_append(method, aml_return(aml_int(0x01))); 1424 aml_append(dev, method); 1425 1426 aml_append(scope, dev); 1427 aml_append(table, scope); 1428 } 1429 1430 static void 1431 build_dsdt(GArray *table_data, BIOSLinker *linker, 1432 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1433 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1434 { 1435 CrsRangeEntry *entry; 1436 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1437 CrsRangeSet crs_range_set; 1438 PCMachineState *pcms = PC_MACHINE(machine); 1439 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1440 X86MachineState *x86ms = X86_MACHINE(machine); 1441 AcpiMcfgInfo mcfg; 1442 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1443 uint32_t nr_mem = machine->ram_slots; 1444 int root_bus_limit = 0xFF; 1445 PCIBus *bus = NULL; 1446 #ifdef CONFIG_TPM 1447 TPMIf *tpm = tpm_find(); 1448 #endif 1449 bool cxl_present = false; 1450 int i; 1451 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1452 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1453 .oem_table_id = x86ms->oem_table_id }; 1454 1455 acpi_table_begin(&table, table_data); 1456 dsdt = init_aml_allocator(); 1457 1458 build_dbg_aml(dsdt); 1459 if (misc->is_piix4) { 1460 sb_scope = aml_scope("_SB"); 1461 dev = aml_device("PCI0"); 1462 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1463 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1464 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1465 aml_append(sb_scope, dev); 1466 aml_append(dsdt, sb_scope); 1467 1468 if (misc->has_hpet) { 1469 build_hpet_aml(dsdt); 1470 } 1471 build_piix4_isa_bridge(dsdt); 1472 build_isa_devices_aml(dsdt); 1473 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1474 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1475 } 1476 build_piix4_pci0_int(dsdt); 1477 } else { 1478 sb_scope = aml_scope("_SB"); 1479 dev = aml_device("PCI0"); 1480 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1481 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1482 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1483 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1484 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1485 aml_append(sb_scope, dev); 1486 if (mcfg_valid) { 1487 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1488 } 1489 1490 if (pm->smi_on_cpuhp) { 1491 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1492 dev = aml_device("PCI0.SMI0"); 1493 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1494 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1495 crs = aml_resource_template(); 1496 aml_append(crs, 1497 aml_io( 1498 AML_DECODE16, 1499 ACPI_PORT_SMI_CMD, 1500 ACPI_PORT_SMI_CMD, 1501 1, 1502 2) 1503 ); 1504 aml_append(dev, aml_name_decl("_CRS", crs)); 1505 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1506 aml_int(ACPI_PORT_SMI_CMD), 2)); 1507 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1508 AML_WRITE_AS_ZEROS); 1509 aml_append(field, aml_named_field("SMIC", 8)); 1510 aml_append(field, aml_reserved_field(8)); 1511 aml_append(dev, field); 1512 aml_append(sb_scope, dev); 1513 } 1514 1515 aml_append(dsdt, sb_scope); 1516 1517 if (misc->has_hpet) { 1518 build_hpet_aml(dsdt); 1519 } 1520 build_q35_isa_bridge(dsdt); 1521 build_isa_devices_aml(dsdt); 1522 if (pm->pcihp_bridge_en) { 1523 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1524 } 1525 build_q35_pci0_int(dsdt); 1526 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1527 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1528 } 1529 } 1530 1531 if (vmbus_bridge) { 1532 sb_scope = aml_scope("_SB"); 1533 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1534 aml_append(dsdt, sb_scope); 1535 } 1536 1537 if (pcmc->legacy_cpu_hotplug) { 1538 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1539 } else { 1540 CPUHotplugFeatures opts = { 1541 .acpi_1_compatible = true, .has_legacy_cphp = true, 1542 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1543 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1544 }; 1545 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1546 "\\_SB.PCI0", "\\_GPE._E02"); 1547 } 1548 1549 if (pcms->memhp_io_base && nr_mem) { 1550 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1551 "\\_GPE._E03", AML_SYSTEM_IO, 1552 pcms->memhp_io_base); 1553 } 1554 1555 scope = aml_scope("_GPE"); 1556 { 1557 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1558 1559 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1560 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1561 aml_append(method, 1562 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1563 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1564 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1565 aml_append(scope, method); 1566 } 1567 1568 if (machine->nvdimms_state->is_enabled) { 1569 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1570 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1571 aml_int(0x80))); 1572 aml_append(scope, method); 1573 } 1574 } 1575 aml_append(dsdt, scope); 1576 1577 crs_range_set_init(&crs_range_set); 1578 bus = PC_MACHINE(machine)->bus; 1579 if (bus) { 1580 QLIST_FOREACH(bus, &bus->child, sibling) { 1581 uint8_t bus_num = pci_bus_num(bus); 1582 uint8_t numa_node = pci_bus_numa_node(bus); 1583 1584 /* look only for expander root buses */ 1585 if (!pci_bus_is_root(bus)) { 1586 continue; 1587 } 1588 1589 if (bus_num < root_bus_limit) { 1590 root_bus_limit = bus_num - 1; 1591 } 1592 1593 scope = aml_scope("\\_SB"); 1594 1595 if (pci_bus_is_cxl(bus)) { 1596 dev = aml_device("CL%.02X", bus_num); 1597 } else { 1598 dev = aml_device("PC%.02X", bus_num); 1599 } 1600 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1601 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1602 if (pci_bus_is_cxl(bus)) { 1603 struct Aml *pkg = aml_package(2); 1604 1605 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1606 aml_append(pkg, aml_eisaid("PNP0A08")); 1607 aml_append(pkg, aml_eisaid("PNP0A03")); 1608 aml_append(dev, aml_name_decl("_CID", pkg)); 1609 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1610 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1611 build_cxl_osc_method(dev); 1612 } else if (pci_bus_is_express(bus)) { 1613 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1614 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1615 1616 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1617 aml_append(dev, build_q35_osc_method(true)); 1618 } else { 1619 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1620 } 1621 1622 if (numa_node != NUMA_NODE_UNASSIGNED) { 1623 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1624 } 1625 1626 aml_append(dev, build_prt(false)); 1627 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1628 0, 0, 0, 0); 1629 aml_append(dev, aml_name_decl("_CRS", crs)); 1630 aml_append(scope, dev); 1631 aml_append(dsdt, scope); 1632 1633 /* Handle the ranges for the PXB expanders */ 1634 if (pci_bus_is_cxl(bus)) { 1635 MemoryRegion *mr = &machine->cxl_devices_state->host_mr; 1636 uint64_t base = mr->addr; 1637 1638 cxl_present = true; 1639 crs_range_insert(crs_range_set.mem_ranges, base, 1640 base + memory_region_size(mr) - 1); 1641 } 1642 } 1643 } 1644 1645 if (cxl_present) { 1646 build_acpi0017(dsdt); 1647 } 1648 1649 /* 1650 * At this point crs_range_set has all the ranges used by pci 1651 * busses *other* than PCI0. These ranges will be excluded from 1652 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1653 * too. 1654 */ 1655 if (mcfg_valid) { 1656 crs_range_insert(crs_range_set.mem_ranges, 1657 mcfg.base, mcfg.base + mcfg.size - 1); 1658 } 1659 1660 scope = aml_scope("\\_SB.PCI0"); 1661 /* build PCI0._CRS */ 1662 crs = aml_resource_template(); 1663 aml_append(crs, 1664 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1665 0x0000, 0x0, root_bus_limit, 1666 0x0000, root_bus_limit + 1)); 1667 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1668 1669 aml_append(crs, 1670 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1671 AML_POS_DECODE, AML_ENTIRE_RANGE, 1672 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1673 1674 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1675 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1676 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1677 aml_append(crs, 1678 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1679 AML_POS_DECODE, AML_ENTIRE_RANGE, 1680 0x0000, entry->base, entry->limit, 1681 0x0000, entry->limit - entry->base + 1)); 1682 } 1683 1684 aml_append(crs, 1685 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1686 AML_CACHEABLE, AML_READ_WRITE, 1687 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1688 1689 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1690 range_lob(pci_hole), 1691 range_upb(pci_hole)); 1692 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1693 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1694 aml_append(crs, 1695 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1696 AML_NON_CACHEABLE, AML_READ_WRITE, 1697 0, entry->base, entry->limit, 1698 0, entry->limit - entry->base + 1)); 1699 } 1700 1701 if (!range_is_empty(pci_hole64)) { 1702 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1703 range_lob(pci_hole64), 1704 range_upb(pci_hole64)); 1705 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1706 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1707 aml_append(crs, 1708 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1709 AML_MAX_FIXED, 1710 AML_CACHEABLE, AML_READ_WRITE, 1711 0, entry->base, entry->limit, 1712 0, entry->limit - entry->base + 1)); 1713 } 1714 } 1715 1716 #ifdef CONFIG_TPM 1717 if (TPM_IS_TIS_ISA(tpm_find())) { 1718 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1719 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1720 } 1721 #endif 1722 aml_append(scope, aml_name_decl("_CRS", crs)); 1723 1724 /* reserve GPE0 block resources */ 1725 dev = aml_device("GPE0"); 1726 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1727 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1728 /* device present, functioning, decoding, not shown in UI */ 1729 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1730 crs = aml_resource_template(); 1731 aml_append(crs, 1732 aml_io( 1733 AML_DECODE16, 1734 pm->fadt.gpe0_blk.address, 1735 pm->fadt.gpe0_blk.address, 1736 1, 1737 pm->fadt.gpe0_blk.bit_width / 8) 1738 ); 1739 aml_append(dev, aml_name_decl("_CRS", crs)); 1740 aml_append(scope, dev); 1741 1742 crs_range_set_free(&crs_range_set); 1743 1744 /* reserve PCIHP resources */ 1745 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1746 dev = aml_device("PHPR"); 1747 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1748 aml_append(dev, 1749 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1750 /* device present, functioning, decoding, not shown in UI */ 1751 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1752 crs = aml_resource_template(); 1753 aml_append(crs, 1754 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1755 pm->pcihp_io_len) 1756 ); 1757 aml_append(dev, aml_name_decl("_CRS", crs)); 1758 aml_append(scope, dev); 1759 } 1760 aml_append(dsdt, scope); 1761 1762 /* create S3_ / S4_ / S5_ packages if necessary */ 1763 scope = aml_scope("\\"); 1764 if (!pm->s3_disabled) { 1765 pkg = aml_package(4); 1766 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1767 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1768 aml_append(pkg, aml_int(0)); /* reserved */ 1769 aml_append(pkg, aml_int(0)); /* reserved */ 1770 aml_append(scope, aml_name_decl("_S3", pkg)); 1771 } 1772 1773 if (!pm->s4_disabled) { 1774 pkg = aml_package(4); 1775 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1776 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1777 aml_append(pkg, aml_int(pm->s4_val)); 1778 aml_append(pkg, aml_int(0)); /* reserved */ 1779 aml_append(pkg, aml_int(0)); /* reserved */ 1780 aml_append(scope, aml_name_decl("_S4", pkg)); 1781 } 1782 1783 pkg = aml_package(4); 1784 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1785 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1786 aml_append(pkg, aml_int(0)); /* reserved */ 1787 aml_append(pkg, aml_int(0)); /* reserved */ 1788 aml_append(scope, aml_name_decl("_S5", pkg)); 1789 aml_append(dsdt, scope); 1790 1791 /* create fw_cfg node, unconditionally */ 1792 { 1793 scope = aml_scope("\\_SB.PCI0"); 1794 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1795 aml_append(dsdt, scope); 1796 } 1797 1798 if (misc->applesmc_io_base) { 1799 scope = aml_scope("\\_SB.PCI0.ISA"); 1800 dev = aml_device("SMC"); 1801 1802 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1803 /* device present, functioning, decoding, not shown in UI */ 1804 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1805 1806 crs = aml_resource_template(); 1807 aml_append(crs, 1808 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1809 0x01, APPLESMC_MAX_DATA_LENGTH) 1810 ); 1811 aml_append(crs, aml_irq_no_flags(6)); 1812 aml_append(dev, aml_name_decl("_CRS", crs)); 1813 1814 aml_append(scope, dev); 1815 aml_append(dsdt, scope); 1816 } 1817 1818 if (misc->pvpanic_port) { 1819 scope = aml_scope("\\_SB.PCI0.ISA"); 1820 1821 dev = aml_device("PEVT"); 1822 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1823 1824 crs = aml_resource_template(); 1825 aml_append(crs, 1826 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1827 ); 1828 aml_append(dev, aml_name_decl("_CRS", crs)); 1829 1830 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1831 aml_int(misc->pvpanic_port), 1)); 1832 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1833 aml_append(field, aml_named_field("PEPT", 8)); 1834 aml_append(dev, field); 1835 1836 /* device present, functioning, decoding, shown in UI */ 1837 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1838 1839 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1840 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1841 aml_append(method, aml_return(aml_local(0))); 1842 aml_append(dev, method); 1843 1844 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1845 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1846 aml_append(dev, method); 1847 1848 aml_append(scope, dev); 1849 aml_append(dsdt, scope); 1850 } 1851 1852 sb_scope = aml_scope("\\_SB"); 1853 { 1854 Object *pci_host; 1855 PCIBus *bus = NULL; 1856 1857 pci_host = acpi_get_i386_pci_host(); 1858 1859 if (pci_host) { 1860 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1861 } 1862 1863 if (bus) { 1864 Aml *scope = aml_scope("PCI0"); 1865 /* Scan all PCI buses. Generate tables to support hotplug. */ 1866 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1867 1868 #ifdef CONFIG_TPM 1869 if (TPM_IS_TIS_ISA(tpm)) { 1870 if (misc->tpm_version == TPM_VERSION_2_0) { 1871 dev = aml_device("TPM"); 1872 aml_append(dev, aml_name_decl("_HID", 1873 aml_string("MSFT0101"))); 1874 aml_append(dev, 1875 aml_name_decl("_STR", 1876 aml_string("TPM 2.0 Device"))); 1877 } else { 1878 dev = aml_device("ISA.TPM"); 1879 aml_append(dev, aml_name_decl("_HID", 1880 aml_eisaid("PNP0C31"))); 1881 } 1882 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1883 1884 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1885 crs = aml_resource_template(); 1886 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1887 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1888 /* 1889 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1890 Rewrite to take IRQ from TPM device model and 1891 fix default IRQ value there to use some unused IRQ 1892 */ 1893 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1894 aml_append(dev, aml_name_decl("_CRS", crs)); 1895 1896 tpm_build_ppi_acpi(tpm, dev); 1897 1898 aml_append(scope, dev); 1899 } 1900 #endif 1901 1902 aml_append(sb_scope, scope); 1903 } 1904 } 1905 1906 #ifdef CONFIG_TPM 1907 if (TPM_IS_CRB(tpm)) { 1908 dev = aml_device("TPM"); 1909 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1910 aml_append(dev, aml_name_decl("_STR", 1911 aml_string("TPM 2.0 Device"))); 1912 crs = aml_resource_template(); 1913 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1914 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1915 aml_append(dev, aml_name_decl("_CRS", crs)); 1916 1917 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1918 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1919 1920 tpm_build_ppi_acpi(tpm, dev); 1921 1922 aml_append(sb_scope, dev); 1923 } 1924 #endif 1925 1926 if (pcms->sgx_epc.size != 0) { 1927 uint64_t epc_base = pcms->sgx_epc.base; 1928 uint64_t epc_size = pcms->sgx_epc.size; 1929 1930 dev = aml_device("EPC"); 1931 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1932 aml_append(dev, aml_name_decl("_STR", 1933 aml_unicode("Enclave Page Cache 1.0"))); 1934 crs = aml_resource_template(); 1935 aml_append(crs, 1936 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1937 AML_MAX_FIXED, AML_NON_CACHEABLE, 1938 AML_READ_WRITE, 0, epc_base, 1939 epc_base + epc_size - 1, 0, epc_size)); 1940 aml_append(dev, aml_name_decl("_CRS", crs)); 1941 1942 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1943 aml_append(method, aml_return(aml_int(0x0f))); 1944 aml_append(dev, method); 1945 1946 aml_append(sb_scope, dev); 1947 } 1948 aml_append(dsdt, sb_scope); 1949 1950 /* copy AML table into ACPI tables blob and patch header there */ 1951 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1952 acpi_table_end(linker, &table); 1953 free_aml_allocator(); 1954 } 1955 1956 /* 1957 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1958 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1959 */ 1960 static void 1961 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1962 const char *oem_table_id) 1963 { 1964 AcpiTable table = { .sig = "HPET", .rev = 1, 1965 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1966 1967 acpi_table_begin(&table, table_data); 1968 /* Note timer_block_id value must be kept in sync with value advertised by 1969 * emulated hpet 1970 */ 1971 /* Event Timer Block ID */ 1972 build_append_int_noprefix(table_data, 0x8086a201, 4); 1973 /* BASE_ADDRESS */ 1974 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1975 /* HPET Number */ 1976 build_append_int_noprefix(table_data, 0, 1); 1977 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1978 build_append_int_noprefix(table_data, 0, 2); 1979 /* Page Protection And OEM Attribute */ 1980 build_append_int_noprefix(table_data, 0, 1); 1981 acpi_table_end(linker, &table); 1982 } 1983 1984 #ifdef CONFIG_TPM 1985 /* 1986 * TCPA Description Table 1987 * 1988 * Following Level 00, Rev 00.37 of specs: 1989 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1990 * 7.1.2 ACPI Table Layout 1991 */ 1992 static void 1993 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1994 const char *oem_id, const char *oem_table_id) 1995 { 1996 unsigned log_addr_offset; 1997 AcpiTable table = { .sig = "TCPA", .rev = 2, 1998 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1999 2000 acpi_table_begin(&table, table_data); 2001 /* Platform Class */ 2002 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 2003 /* Log Area Minimum Length (LAML) */ 2004 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 2005 /* Log Area Start Address (LASA) */ 2006 log_addr_offset = table_data->len; 2007 build_append_int_noprefix(table_data, 0, 8); 2008 2009 /* allocate/reserve space for TPM log area */ 2010 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 2011 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 2012 false /* high memory */); 2013 /* log area start address to be filled by Guest linker */ 2014 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2015 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 2016 2017 acpi_table_end(linker, &table); 2018 } 2019 #endif 2020 2021 #define HOLE_640K_START (640 * KiB) 2022 #define HOLE_640K_END (1 * MiB) 2023 2024 /* 2025 * ACPI spec, Revision 3.0 2026 * 5.2.15 System Resource Affinity Table (SRAT) 2027 */ 2028 static void 2029 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2030 { 2031 int i; 2032 int numa_mem_start, slots; 2033 uint64_t mem_len, mem_base, next_base; 2034 MachineClass *mc = MACHINE_GET_CLASS(machine); 2035 X86MachineState *x86ms = X86_MACHINE(machine); 2036 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2037 PCMachineState *pcms = PC_MACHINE(machine); 2038 int nb_numa_nodes = machine->numa_state->num_nodes; 2039 NodeInfo *numa_info = machine->numa_state->nodes; 2040 ram_addr_t hotpluggable_address_space_size = 2041 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 2042 NULL); 2043 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 2044 .oem_table_id = x86ms->oem_table_id }; 2045 2046 acpi_table_begin(&table, table_data); 2047 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 2048 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 2049 2050 for (i = 0; i < apic_ids->len; i++) { 2051 int node_id = apic_ids->cpus[i].props.node_id; 2052 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2053 2054 if (apic_id < 255) { 2055 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 2056 build_append_int_noprefix(table_data, 0, 1); /* Type */ 2057 build_append_int_noprefix(table_data, 16, 1); /* Length */ 2058 /* Proximity Domain [7:0] */ 2059 build_append_int_noprefix(table_data, node_id, 1); 2060 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 2061 /* Flags, Table 5-36 */ 2062 build_append_int_noprefix(table_data, 1, 4); 2063 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 2064 /* Proximity Domain [31:8] */ 2065 build_append_int_noprefix(table_data, 0, 3); 2066 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 2067 } else { 2068 /* 2069 * ACPI spec, Revision 4.0 2070 * 5.2.16.3 Processor Local x2APIC Affinity Structure 2071 */ 2072 build_append_int_noprefix(table_data, 2, 1); /* Type */ 2073 build_append_int_noprefix(table_data, 24, 1); /* Length */ 2074 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2075 /* Proximity Domain */ 2076 build_append_int_noprefix(table_data, node_id, 4); 2077 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 2078 /* Flags, Table 5-39 */ 2079 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 2080 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 2081 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 2082 } 2083 } 2084 2085 /* the memory map is a bit tricky, it contains at least one hole 2086 * from 640k-1M and possibly another one from 3.5G-4G. 2087 */ 2088 next_base = 0; 2089 numa_mem_start = table_data->len; 2090 2091 for (i = 1; i < nb_numa_nodes + 1; ++i) { 2092 mem_base = next_base; 2093 mem_len = numa_info[i - 1].node_mem; 2094 next_base = mem_base + mem_len; 2095 2096 /* Cut out the 640K hole */ 2097 if (mem_base <= HOLE_640K_START && 2098 next_base > HOLE_640K_START) { 2099 mem_len -= next_base - HOLE_640K_START; 2100 if (mem_len > 0) { 2101 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2102 MEM_AFFINITY_ENABLED); 2103 } 2104 2105 /* Check for the rare case: 640K < RAM < 1M */ 2106 if (next_base <= HOLE_640K_END) { 2107 next_base = HOLE_640K_END; 2108 continue; 2109 } 2110 mem_base = HOLE_640K_END; 2111 mem_len = next_base - HOLE_640K_END; 2112 } 2113 2114 /* Cut out the ACPI_PCI hole */ 2115 if (mem_base <= x86ms->below_4g_mem_size && 2116 next_base > x86ms->below_4g_mem_size) { 2117 mem_len -= next_base - x86ms->below_4g_mem_size; 2118 if (mem_len > 0) { 2119 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2120 MEM_AFFINITY_ENABLED); 2121 } 2122 mem_base = 1ULL << 32; 2123 mem_len = next_base - x86ms->below_4g_mem_size; 2124 next_base = mem_base + mem_len; 2125 } 2126 2127 if (mem_len > 0) { 2128 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2129 MEM_AFFINITY_ENABLED); 2130 } 2131 } 2132 2133 if (machine->nvdimms_state->is_enabled) { 2134 nvdimm_build_srat(table_data); 2135 } 2136 2137 sgx_epc_build_srat(table_data); 2138 2139 /* 2140 * TODO: this part is not in ACPI spec and current linux kernel boots fine 2141 * without these entries. But I recall there were issues the last time I 2142 * tried to remove it with some ancient guest OS, however I can't remember 2143 * what that was so keep this around for now 2144 */ 2145 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 2146 for (; slots < nb_numa_nodes + 2; slots++) { 2147 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2148 } 2149 2150 /* 2151 * Entry is required for Windows to enable memory hotplug in OS 2152 * and for Linux to enable SWIOTLB when booted with less than 2153 * 4G of RAM. Windows works better if the entry sets proximity 2154 * to the highest NUMA node in the machine. 2155 * Memory devices may override proximity set by this entry, 2156 * providing _PXM method if necessary. 2157 */ 2158 if (hotpluggable_address_space_size) { 2159 build_srat_memory(table_data, machine->device_memory->base, 2160 hotpluggable_address_space_size, nb_numa_nodes - 1, 2161 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2162 } 2163 2164 acpi_table_end(linker, &table); 2165 } 2166 2167 /* 2168 * Insert DMAR scope for PCI bridges and endpoint devcie 2169 */ 2170 static void 2171 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2172 { 2173 const size_t device_scope_size = 6 /* device scope structure */ + 2174 2 /* 1 path entry */; 2175 GArray *scope_blob = opaque; 2176 2177 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2178 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2179 build_append_int_noprefix(scope_blob, 0x02, 1); 2180 } else { 2181 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2182 build_append_int_noprefix(scope_blob, 0x01, 1); 2183 } 2184 2185 /* length */ 2186 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2187 /* reserved */ 2188 build_append_int_noprefix(scope_blob, 0, 2); 2189 /* enumeration_id */ 2190 build_append_int_noprefix(scope_blob, 0, 1); 2191 /* bus */ 2192 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2193 /* device */ 2194 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2195 /* function */ 2196 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2197 } 2198 2199 /* For a given PCI host bridge, walk and insert DMAR scope */ 2200 static int 2201 dmar_host_bridges(Object *obj, void *opaque) 2202 { 2203 GArray *scope_blob = opaque; 2204 2205 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2206 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2207 2208 if (bus && !pci_bus_bypass_iommu(bus)) { 2209 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2210 } 2211 } 2212 2213 return 0; 2214 } 2215 2216 /* 2217 * Intel ® Virtualization Technology for Directed I/O 2218 * Architecture Specification. Revision 3.3 2219 * 8.1 DMA Remapping Reporting Structure 2220 */ 2221 static void 2222 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2223 const char *oem_table_id) 2224 { 2225 uint8_t dmar_flags = 0; 2226 uint8_t rsvd10[10] = {}; 2227 /* Root complex IOAPIC uses one path only */ 2228 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2229 2 /* 1 path entry */; 2230 X86IOMMUState *iommu = x86_iommu_get_default(); 2231 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2232 GArray *scope_blob = g_array_new(false, true, 1); 2233 2234 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2235 .oem_table_id = oem_table_id }; 2236 2237 /* 2238 * A PCI bus walk, for each PCI host bridge. 2239 * Insert scope for each PCI bridge and endpoint device which 2240 * is attached to a bus with iommu enabled. 2241 */ 2242 object_child_foreach_recursive(object_get_root(), 2243 dmar_host_bridges, scope_blob); 2244 2245 assert(iommu); 2246 if (x86_iommu_ir_supported(iommu)) { 2247 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2248 } 2249 2250 acpi_table_begin(&table, table_data); 2251 /* Host Address Width */ 2252 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2253 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2254 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2255 2256 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2257 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2258 /* Length */ 2259 build_append_int_noprefix(table_data, 2260 16 + ioapic_scope_size + scope_blob->len, 2); 2261 /* Flags */ 2262 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2263 1); 2264 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2265 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2266 /* Register Base Address */ 2267 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2268 2269 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2270 * 8.3.1 (version Oct. 2014 or later). */ 2271 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2272 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2273 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2274 /* Enumeration ID */ 2275 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2276 /* Start Bus Number */ 2277 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2278 /* Path, {Device, Function} pair */ 2279 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2280 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2281 2282 /* Add scope found above */ 2283 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2284 g_array_free(scope_blob, true); 2285 2286 if (iommu->dt_supported) { 2287 /* 8.5 Root Port ATS Capability Reporting Structure */ 2288 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2289 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2290 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2291 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2292 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2293 } 2294 2295 acpi_table_end(linker, &table); 2296 } 2297 2298 /* 2299 * Windows ACPI Emulated Devices Table 2300 * (Version 1.0 - April 6, 2009) 2301 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2302 * 2303 * Helpful to speedup Windows guests and ignored by others. 2304 */ 2305 static void 2306 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2307 const char *oem_table_id) 2308 { 2309 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2310 .oem_table_id = oem_table_id }; 2311 2312 acpi_table_begin(&table, table_data); 2313 /* 2314 * Set "ACPI PM timer good" flag. 2315 * 2316 * Tells Windows guests that our ACPI PM timer is reliable in the 2317 * sense that guest can read it only once to obtain a reliable value. 2318 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2319 */ 2320 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2321 acpi_table_end(linker, &table); 2322 } 2323 2324 /* 2325 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2326 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2327 */ 2328 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2329 2330 /* 2331 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2332 * necessary for the PCI topology. 2333 */ 2334 static void 2335 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2336 { 2337 GArray *table_data = opaque; 2338 uint32_t entry; 2339 2340 /* "Select" IVHD entry, type 0x2 */ 2341 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2342 build_append_int_noprefix(table_data, entry, 4); 2343 2344 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2345 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2346 uint8_t sec = pci_bus_num(sec_bus); 2347 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2348 2349 if (pci_bus_is_express(sec_bus)) { 2350 /* 2351 * Walk the bus if there are subordinates, otherwise use a range 2352 * to cover an entire leaf bus. We could potentially also use a 2353 * range for traversed buses, but we'd need to take care not to 2354 * create both Select and Range entries covering the same device. 2355 * This is easier and potentially more compact. 2356 * 2357 * An example bare metal system seems to use Select entries for 2358 * root ports without a slot (ie. built-ins) and Range entries 2359 * when there is a slot. The same system also only hard-codes 2360 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2361 * making no effort to support nested bridges. We attempt to 2362 * be more thorough here. 2363 */ 2364 if (sec == sub) { /* leaf bus */ 2365 /* "Start of Range" IVHD entry, type 0x3 */ 2366 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2367 build_append_int_noprefix(table_data, entry, 4); 2368 /* "End of Range" IVHD entry, type 0x4 */ 2369 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2370 build_append_int_noprefix(table_data, entry, 4); 2371 } else { 2372 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2373 } 2374 } else { 2375 /* 2376 * If the secondary bus is conventional, then we need to create an 2377 * Alias range for everything downstream. The range covers the 2378 * first devfn on the secondary bus to the last devfn on the 2379 * subordinate bus. The alias target depends on legacy versus 2380 * express bridges, just as in pci_device_iommu_address_space(). 2381 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2382 */ 2383 uint16_t dev_id_a, dev_id_b; 2384 2385 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2386 2387 if (pci_is_express(dev) && 2388 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2389 dev_id_b = dev_id_a; 2390 } else { 2391 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2392 } 2393 2394 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2395 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2396 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2397 2398 /* "End of Range" IVHD entry, type 0x4 */ 2399 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2400 build_append_int_noprefix(table_data, entry, 4); 2401 } 2402 } 2403 } 2404 2405 /* For all PCI host bridges, walk and insert IVHD entries */ 2406 static int 2407 ivrs_host_bridges(Object *obj, void *opaque) 2408 { 2409 GArray *ivhd_blob = opaque; 2410 2411 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2412 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2413 2414 if (bus && !pci_bus_bypass_iommu(bus)) { 2415 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2416 } 2417 } 2418 2419 return 0; 2420 } 2421 2422 static void 2423 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2424 const char *oem_table_id) 2425 { 2426 int ivhd_table_len = 24; 2427 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2428 GArray *ivhd_blob = g_array_new(false, true, 1); 2429 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2430 .oem_table_id = oem_table_id }; 2431 2432 acpi_table_begin(&table, table_data); 2433 /* IVinfo - IO virtualization information common to all 2434 * IOMMU units in a system 2435 */ 2436 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2437 /* reserved */ 2438 build_append_int_noprefix(table_data, 0, 8); 2439 2440 /* IVHD definition - type 10h */ 2441 build_append_int_noprefix(table_data, 0x10, 1); 2442 /* virtualization flags */ 2443 build_append_int_noprefix(table_data, 2444 (1UL << 0) | /* HtTunEn */ 2445 (1UL << 4) | /* iotblSup */ 2446 (1UL << 6) | /* PrefSup */ 2447 (1UL << 7), /* PPRSup */ 2448 1); 2449 2450 /* 2451 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2452 * complete set of IVHD entries. Do this into a separate blob so that we 2453 * can calculate the total IVRS table length here and then append the new 2454 * blob further below. Fall back to an entry covering all devices, which 2455 * is sufficient when no aliases are present. 2456 */ 2457 object_child_foreach_recursive(object_get_root(), 2458 ivrs_host_bridges, ivhd_blob); 2459 2460 if (!ivhd_blob->len) { 2461 /* 2462 * Type 1 device entry reporting all devices 2463 * These are 4-byte device entries currently reporting the range of 2464 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2465 */ 2466 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2467 } 2468 2469 ivhd_table_len += ivhd_blob->len; 2470 2471 /* 2472 * When interrupt remapping is supported, we add a special IVHD device 2473 * for type IO-APIC. 2474 */ 2475 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2476 ivhd_table_len += 8; 2477 } 2478 2479 /* IVHD length */ 2480 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2481 /* DeviceID */ 2482 build_append_int_noprefix(table_data, s->devid, 2); 2483 /* Capability offset */ 2484 build_append_int_noprefix(table_data, s->capab_offset, 2); 2485 /* IOMMU base address */ 2486 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2487 /* PCI Segment Group */ 2488 build_append_int_noprefix(table_data, 0, 2); 2489 /* IOMMU info */ 2490 build_append_int_noprefix(table_data, 0, 2); 2491 /* IOMMU Feature Reporting */ 2492 build_append_int_noprefix(table_data, 2493 (48UL << 30) | /* HATS */ 2494 (48UL << 28) | /* GATS */ 2495 (1UL << 2) | /* GTSup */ 2496 (1UL << 6), /* GASup */ 2497 4); 2498 2499 /* IVHD entries as found above */ 2500 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2501 g_array_free(ivhd_blob, TRUE); 2502 2503 /* 2504 * Add a special IVHD device type. 2505 * Refer to spec - Table 95: IVHD device entry type codes 2506 * 2507 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2508 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2509 */ 2510 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2511 build_append_int_noprefix(table_data, 2512 (0x1ull << 56) | /* type IOAPIC */ 2513 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2514 0x48, /* special device */ 2515 8); 2516 } 2517 acpi_table_end(linker, &table); 2518 } 2519 2520 typedef 2521 struct AcpiBuildState { 2522 /* Copy of table in RAM (for patching). */ 2523 MemoryRegion *table_mr; 2524 /* Is table patched? */ 2525 uint8_t patched; 2526 void *rsdp; 2527 MemoryRegion *rsdp_mr; 2528 MemoryRegion *linker_mr; 2529 } AcpiBuildState; 2530 2531 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2532 { 2533 Object *pci_host; 2534 QObject *o; 2535 2536 pci_host = acpi_get_i386_pci_host(); 2537 if (!pci_host) { 2538 return false; 2539 } 2540 2541 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2542 if (!o) { 2543 return false; 2544 } 2545 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2546 qobject_unref(o); 2547 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2548 return false; 2549 } 2550 2551 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2552 assert(o); 2553 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2554 qobject_unref(o); 2555 return true; 2556 } 2557 2558 static 2559 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2560 { 2561 PCMachineState *pcms = PC_MACHINE(machine); 2562 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2563 X86MachineState *x86ms = X86_MACHINE(machine); 2564 DeviceState *iommu = pcms->iommu; 2565 GArray *table_offsets; 2566 unsigned facs, dsdt, rsdt, fadt; 2567 AcpiPmInfo pm; 2568 AcpiMiscInfo misc; 2569 AcpiMcfgInfo mcfg; 2570 Range pci_hole = {}, pci_hole64 = {}; 2571 uint8_t *u; 2572 size_t aml_len = 0; 2573 GArray *tables_blob = tables->table_data; 2574 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2575 Object *vmgenid_dev; 2576 char *oem_id; 2577 char *oem_table_id; 2578 2579 acpi_get_pm_info(machine, &pm); 2580 acpi_get_misc_info(&misc); 2581 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2582 acpi_get_slic_oem(&slic_oem); 2583 2584 if (slic_oem.id) { 2585 oem_id = slic_oem.id; 2586 } else { 2587 oem_id = x86ms->oem_id; 2588 } 2589 2590 if (slic_oem.table_id) { 2591 oem_table_id = slic_oem.table_id; 2592 } else { 2593 oem_table_id = x86ms->oem_table_id; 2594 } 2595 2596 table_offsets = g_array_new(false, true /* clear */, 2597 sizeof(uint32_t)); 2598 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2599 2600 bios_linker_loader_alloc(tables->linker, 2601 ACPI_BUILD_TABLE_FILE, tables_blob, 2602 64 /* Ensure FACS is aligned */, 2603 false /* high memory */); 2604 2605 /* 2606 * FACS is pointed to by FADT. 2607 * We place it first since it's the only table that has alignment 2608 * requirements. 2609 */ 2610 facs = tables_blob->len; 2611 build_facs(tables_blob); 2612 2613 /* DSDT is pointed to by FADT */ 2614 dsdt = tables_blob->len; 2615 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2616 &pci_hole, &pci_hole64, machine); 2617 2618 /* Count the size of the DSDT and SSDT, we will need it for legacy 2619 * sizing of ACPI tables. 2620 */ 2621 aml_len += tables_blob->len - dsdt; 2622 2623 /* ACPI tables pointed to by RSDT */ 2624 fadt = tables_blob->len; 2625 acpi_add_table(table_offsets, tables_blob); 2626 pm.fadt.facs_tbl_offset = &facs; 2627 pm.fadt.dsdt_tbl_offset = &dsdt; 2628 pm.fadt.xdsdt_tbl_offset = &dsdt; 2629 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2630 aml_len += tables_blob->len - fadt; 2631 2632 acpi_add_table(table_offsets, tables_blob); 2633 acpi_build_madt(tables_blob, tables->linker, x86ms, 2634 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2635 x86ms->oem_table_id); 2636 2637 #ifdef CONFIG_ACPI_ERST 2638 { 2639 Object *erst_dev; 2640 erst_dev = find_erst_dev(); 2641 if (erst_dev) { 2642 acpi_add_table(table_offsets, tables_blob); 2643 build_erst(tables_blob, tables->linker, erst_dev, 2644 x86ms->oem_id, x86ms->oem_table_id); 2645 } 2646 } 2647 #endif 2648 2649 vmgenid_dev = find_vmgenid_dev(); 2650 if (vmgenid_dev) { 2651 acpi_add_table(table_offsets, tables_blob); 2652 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2653 tables->vmgenid, tables->linker, x86ms->oem_id); 2654 } 2655 2656 if (misc.has_hpet) { 2657 acpi_add_table(table_offsets, tables_blob); 2658 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2659 x86ms->oem_table_id); 2660 } 2661 #ifdef CONFIG_TPM 2662 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2663 if (misc.tpm_version == TPM_VERSION_1_2) { 2664 acpi_add_table(table_offsets, tables_blob); 2665 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2666 x86ms->oem_id, x86ms->oem_table_id); 2667 } else { /* TPM_VERSION_2_0 */ 2668 acpi_add_table(table_offsets, tables_blob); 2669 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2670 x86ms->oem_id, x86ms->oem_table_id); 2671 } 2672 } 2673 #endif 2674 if (machine->numa_state->num_nodes) { 2675 acpi_add_table(table_offsets, tables_blob); 2676 build_srat(tables_blob, tables->linker, machine); 2677 if (machine->numa_state->have_numa_distance) { 2678 acpi_add_table(table_offsets, tables_blob); 2679 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2680 x86ms->oem_table_id); 2681 } 2682 if (machine->numa_state->hmat_enabled) { 2683 acpi_add_table(table_offsets, tables_blob); 2684 build_hmat(tables_blob, tables->linker, machine->numa_state, 2685 x86ms->oem_id, x86ms->oem_table_id); 2686 } 2687 } 2688 if (acpi_get_mcfg(&mcfg)) { 2689 acpi_add_table(table_offsets, tables_blob); 2690 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2691 x86ms->oem_table_id); 2692 } 2693 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2694 acpi_add_table(table_offsets, tables_blob); 2695 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2696 x86ms->oem_table_id); 2697 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2698 acpi_add_table(table_offsets, tables_blob); 2699 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2700 x86ms->oem_table_id); 2701 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2702 PCIDevice *pdev = PCI_DEVICE(iommu); 2703 2704 acpi_add_table(table_offsets, tables_blob); 2705 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2706 x86ms->oem_id, x86ms->oem_table_id); 2707 } 2708 if (machine->nvdimms_state->is_enabled) { 2709 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2710 machine->nvdimms_state, machine->ram_slots, 2711 x86ms->oem_id, x86ms->oem_table_id); 2712 } 2713 if (machine->cxl_devices_state->is_enabled) { 2714 cxl_build_cedt(machine, table_offsets, tables_blob, tables->linker, 2715 x86ms->oem_id, x86ms->oem_table_id); 2716 } 2717 2718 acpi_add_table(table_offsets, tables_blob); 2719 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2720 2721 /* Add tables supplied by user (if any) */ 2722 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2723 unsigned len = acpi_table_len(u); 2724 2725 acpi_add_table(table_offsets, tables_blob); 2726 g_array_append_vals(tables_blob, u, len); 2727 } 2728 2729 /* RSDT is pointed to by RSDP */ 2730 rsdt = tables_blob->len; 2731 build_rsdt(tables_blob, tables->linker, table_offsets, 2732 oem_id, oem_table_id); 2733 2734 /* RSDP is in FSEG memory, so allocate it separately */ 2735 { 2736 AcpiRsdpData rsdp_data = { 2737 .revision = 0, 2738 .oem_id = x86ms->oem_id, 2739 .xsdt_tbl_offset = NULL, 2740 .rsdt_tbl_offset = &rsdt, 2741 }; 2742 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2743 if (!pcmc->rsdp_in_ram) { 2744 /* We used to allocate some extra space for RSDP revision 2 but 2745 * only used the RSDP revision 0 space. The extra bytes were 2746 * zeroed out and not used. 2747 * Here we continue wasting those extra 16 bytes to make sure we 2748 * don't break migration for machine types 2.2 and older due to 2749 * RSDP blob size mismatch. 2750 */ 2751 build_append_int_noprefix(tables->rsdp, 0, 16); 2752 } 2753 } 2754 2755 /* We'll expose it all to Guest so we want to reduce 2756 * chance of size changes. 2757 * 2758 * We used to align the tables to 4k, but of course this would 2759 * too simple to be enough. 4k turned out to be too small an 2760 * alignment very soon, and in fact it is almost impossible to 2761 * keep the table size stable for all (max_cpus, max_memory_slots) 2762 * combinations. So the table size is always 64k for pc-i440fx-2.1 2763 * and we give an error if the table grows beyond that limit. 2764 * 2765 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2766 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2767 * than 2.0 and we can always pad the smaller tables with zeros. We can 2768 * then use the exact size of the 2.0 tables. 2769 * 2770 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2771 */ 2772 if (pcmc->legacy_acpi_table_size) { 2773 /* Subtracting aml_len gives the size of fixed tables. Then add the 2774 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2775 */ 2776 int legacy_aml_len = 2777 pcmc->legacy_acpi_table_size + 2778 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2779 int legacy_table_size = 2780 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2781 ACPI_BUILD_ALIGN_SIZE); 2782 if (tables_blob->len > legacy_table_size) { 2783 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2784 warn_report("ACPI table size %u exceeds %d bytes," 2785 " migration may not work", 2786 tables_blob->len, legacy_table_size); 2787 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2788 " or PCI bridges."); 2789 } 2790 g_array_set_size(tables_blob, legacy_table_size); 2791 } else { 2792 /* Make sure we have a buffer in case we need to resize the tables. */ 2793 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2794 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2795 warn_report("ACPI table size %u exceeds %d bytes," 2796 " migration may not work", 2797 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2798 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2799 " or PCI bridges."); 2800 } 2801 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2802 } 2803 2804 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2805 2806 /* Cleanup memory that's no longer used. */ 2807 g_array_free(table_offsets, true); 2808 g_free(slic_oem.id); 2809 g_free(slic_oem.table_id); 2810 } 2811 2812 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2813 { 2814 uint32_t size = acpi_data_len(data); 2815 2816 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2817 memory_region_ram_resize(mr, size, &error_abort); 2818 2819 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2820 memory_region_set_dirty(mr, 0, size); 2821 } 2822 2823 static void acpi_build_update(void *build_opaque) 2824 { 2825 AcpiBuildState *build_state = build_opaque; 2826 AcpiBuildTables tables; 2827 2828 /* No state to update or already patched? Nothing to do. */ 2829 if (!build_state || build_state->patched) { 2830 return; 2831 } 2832 build_state->patched = 1; 2833 2834 acpi_build_tables_init(&tables); 2835 2836 acpi_build(&tables, MACHINE(qdev_get_machine())); 2837 2838 acpi_ram_update(build_state->table_mr, tables.table_data); 2839 2840 if (build_state->rsdp) { 2841 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2842 } else { 2843 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2844 } 2845 2846 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2847 acpi_build_tables_cleanup(&tables, true); 2848 } 2849 2850 static void acpi_build_reset(void *build_opaque) 2851 { 2852 AcpiBuildState *build_state = build_opaque; 2853 build_state->patched = 0; 2854 } 2855 2856 static const VMStateDescription vmstate_acpi_build = { 2857 .name = "acpi_build", 2858 .version_id = 1, 2859 .minimum_version_id = 1, 2860 .fields = (VMStateField[]) { 2861 VMSTATE_UINT8(patched, AcpiBuildState), 2862 VMSTATE_END_OF_LIST() 2863 }, 2864 }; 2865 2866 void acpi_setup(void) 2867 { 2868 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2869 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2870 X86MachineState *x86ms = X86_MACHINE(pcms); 2871 AcpiBuildTables tables; 2872 AcpiBuildState *build_state; 2873 Object *vmgenid_dev; 2874 #ifdef CONFIG_TPM 2875 TPMIf *tpm; 2876 static FwCfgTPMConfig tpm_config; 2877 #endif 2878 2879 if (!x86ms->fw_cfg) { 2880 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2881 return; 2882 } 2883 2884 if (!pcms->acpi_build_enabled) { 2885 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2886 return; 2887 } 2888 2889 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2890 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2891 return; 2892 } 2893 2894 build_state = g_malloc0(sizeof *build_state); 2895 2896 acpi_build_tables_init(&tables); 2897 acpi_build(&tables, MACHINE(pcms)); 2898 2899 /* Now expose it all to Guest */ 2900 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2901 build_state, tables.table_data, 2902 ACPI_BUILD_TABLE_FILE); 2903 assert(build_state->table_mr != NULL); 2904 2905 build_state->linker_mr = 2906 acpi_add_rom_blob(acpi_build_update, build_state, 2907 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2908 2909 #ifdef CONFIG_TPM 2910 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2911 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2912 2913 tpm = tpm_find(); 2914 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2915 tpm_config = (FwCfgTPMConfig) { 2916 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2917 .tpm_version = tpm_get_version(tpm), 2918 .tpmppi_version = TPM_PPI_VERSION_1_30 2919 }; 2920 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2921 &tpm_config, sizeof tpm_config); 2922 } 2923 #endif 2924 2925 vmgenid_dev = find_vmgenid_dev(); 2926 if (vmgenid_dev) { 2927 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2928 tables.vmgenid); 2929 } 2930 2931 if (!pcmc->rsdp_in_ram) { 2932 /* 2933 * Keep for compatibility with old machine types. 2934 * Though RSDP is small, its contents isn't immutable, so 2935 * we'll update it along with the rest of tables on guest access. 2936 */ 2937 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2938 2939 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2940 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2941 acpi_build_update, NULL, build_state, 2942 build_state->rsdp, rsdp_size, true); 2943 build_state->rsdp_mr = NULL; 2944 } else { 2945 build_state->rsdp = NULL; 2946 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2947 build_state, tables.rsdp, 2948 ACPI_BUILD_RSDP_FILE); 2949 } 2950 2951 qemu_register_reset(acpi_build_reset, build_state); 2952 acpi_build_reset(build_state); 2953 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2954 2955 /* Cleanup tables but don't free the memory: we track it 2956 * in build_state. 2957 */ 2958 acpi_build_tables_cleanup(&tables, false); 2959 } 2960