1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "acpi-build.h" 25 #include <glib.h> 26 #include "qemu-common.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/error-report.h" 29 #include "hw/pci/pci.h" 30 #include "qom/cpu.h" 31 #include "hw/i386/pc.h" 32 #include "target-i386/cpu.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/acpi/acpi-defs.h" 35 #include "hw/acpi/acpi.h" 36 #include "hw/nvram/fw_cfg.h" 37 #include "hw/acpi/bios-linker-loader.h" 38 #include "hw/loader.h" 39 #include "hw/isa/isa.h" 40 #include "hw/block/fdc.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "sysemu/tpm.h" 43 #include "hw/acpi/tpm.h" 44 #include "sysemu/tpm_backend.h" 45 #include "hw/timer/mc146818rtc_regs.h" 46 47 /* Supported chipsets: */ 48 #include "hw/acpi/piix4.h" 49 #include "hw/acpi/pcihp.h" 50 #include "hw/i386/ich9.h" 51 #include "hw/pci/pci_bus.h" 52 #include "hw/pci-host/q35.h" 53 #include "hw/i386/intel_iommu.h" 54 #include "hw/timer/hpet.h" 55 56 #include "hw/acpi/aml-build.h" 57 58 #include "qapi/qmp/qint.h" 59 #include "qom/qom-qobject.h" 60 61 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 63 * a little bit, there should be plenty of free space since the DSDT 64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 65 */ 66 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 67 #define ACPI_BUILD_ALIGN_SIZE 0x1000 68 69 #define ACPI_BUILD_TABLE_SIZE 0x20000 70 71 /* #define DEBUG_ACPI_BUILD */ 72 #ifdef DEBUG_ACPI_BUILD 73 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 75 #else 76 #define ACPI_BUILD_DPRINTF(fmt, ...) 77 #endif 78 79 typedef struct AcpiMcfgInfo { 80 uint64_t mcfg_base; 81 uint32_t mcfg_size; 82 } AcpiMcfgInfo; 83 84 typedef struct AcpiPmInfo { 85 bool s3_disabled; 86 bool s4_disabled; 87 bool pcihp_bridge_en; 88 uint8_t s4_val; 89 uint16_t sci_int; 90 uint8_t acpi_enable_cmd; 91 uint8_t acpi_disable_cmd; 92 uint32_t gpe0_blk; 93 uint32_t gpe0_blk_len; 94 uint32_t io_base; 95 uint16_t cpu_hp_io_base; 96 uint16_t cpu_hp_io_len; 97 uint16_t mem_hp_io_base; 98 uint16_t mem_hp_io_len; 99 uint16_t pcihp_io_base; 100 uint16_t pcihp_io_len; 101 } AcpiPmInfo; 102 103 typedef struct AcpiMiscInfo { 104 bool is_piix4; 105 bool has_hpet; 106 TPMVersion tpm_version; 107 const unsigned char *dsdt_code; 108 unsigned dsdt_size; 109 uint16_t pvpanic_port; 110 uint16_t applesmc_io_base; 111 } AcpiMiscInfo; 112 113 typedef struct AcpiBuildPciBusHotplugState { 114 GArray *device_table; 115 GArray *notify_table; 116 struct AcpiBuildPciBusHotplugState *parent; 117 bool pcihp_bridge_en; 118 } AcpiBuildPciBusHotplugState; 119 120 static void acpi_get_pm_info(AcpiPmInfo *pm) 121 { 122 Object *piix = piix4_pm_find(); 123 Object *lpc = ich9_lpc_find(); 124 Object *obj = NULL; 125 QObject *o; 126 127 pm->cpu_hp_io_base = 0; 128 pm->pcihp_io_base = 0; 129 pm->pcihp_io_len = 0; 130 if (piix) { 131 obj = piix; 132 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 133 pm->pcihp_io_base = 134 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 135 pm->pcihp_io_len = 136 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 137 } 138 if (lpc) { 139 obj = lpc; 140 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 141 } 142 assert(obj); 143 144 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN; 145 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 146 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN; 147 148 /* Fill in optional s3/s4 related properties */ 149 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 150 if (o) { 151 pm->s3_disabled = qint_get_int(qobject_to_qint(o)); 152 } else { 153 pm->s3_disabled = false; 154 } 155 qobject_decref(o); 156 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 157 if (o) { 158 pm->s4_disabled = qint_get_int(qobject_to_qint(o)); 159 } else { 160 pm->s4_disabled = false; 161 } 162 qobject_decref(o); 163 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 164 if (o) { 165 pm->s4_val = qint_get_int(qobject_to_qint(o)); 166 } else { 167 pm->s4_val = false; 168 } 169 qobject_decref(o); 170 171 /* Fill in mandatory properties */ 172 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); 173 174 pm->acpi_enable_cmd = object_property_get_int(obj, 175 ACPI_PM_PROP_ACPI_ENABLE_CMD, 176 NULL); 177 pm->acpi_disable_cmd = object_property_get_int(obj, 178 ACPI_PM_PROP_ACPI_DISABLE_CMD, 179 NULL); 180 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE, 181 NULL); 182 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK, 183 NULL); 184 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, 185 NULL); 186 pm->pcihp_bridge_en = 187 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 188 NULL); 189 } 190 191 static void acpi_get_misc_info(AcpiMiscInfo *info) 192 { 193 Object *piix = piix4_pm_find(); 194 Object *lpc = ich9_lpc_find(); 195 assert(!!piix != !!lpc); 196 197 if (piix) { 198 info->is_piix4 = true; 199 } 200 if (lpc) { 201 info->is_piix4 = false; 202 } 203 204 info->has_hpet = hpet_find(); 205 info->tpm_version = tpm_get_version(); 206 info->pvpanic_port = pvpanic_port(); 207 info->applesmc_io_base = applesmc_port(); 208 } 209 210 /* 211 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 212 * On i386 arch we only have two pci hosts, so we can look only for them. 213 */ 214 static Object *acpi_get_i386_pci_host(void) 215 { 216 PCIHostState *host; 217 218 host = OBJECT_CHECK(PCIHostState, 219 object_resolve_path("/machine/i440fx", NULL), 220 TYPE_PCI_HOST_BRIDGE); 221 if (!host) { 222 host = OBJECT_CHECK(PCIHostState, 223 object_resolve_path("/machine/q35", NULL), 224 TYPE_PCI_HOST_BRIDGE); 225 } 226 227 return OBJECT(host); 228 } 229 230 static void acpi_get_pci_info(PcPciInfo *info) 231 { 232 Object *pci_host; 233 234 235 pci_host = acpi_get_i386_pci_host(); 236 g_assert(pci_host); 237 238 info->w32.begin = object_property_get_int(pci_host, 239 PCI_HOST_PROP_PCI_HOLE_START, 240 NULL); 241 info->w32.end = object_property_get_int(pci_host, 242 PCI_HOST_PROP_PCI_HOLE_END, 243 NULL); 244 info->w64.begin = object_property_get_int(pci_host, 245 PCI_HOST_PROP_PCI_HOLE64_START, 246 NULL); 247 info->w64.end = object_property_get_int(pci_host, 248 PCI_HOST_PROP_PCI_HOLE64_END, 249 NULL); 250 } 251 252 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */ 253 254 static void acpi_align_size(GArray *blob, unsigned align) 255 { 256 /* Align size to multiple of given size. This reduces the chance 257 * we need to change size in the future (breaking cross version migration). 258 */ 259 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 260 } 261 262 /* FACS */ 263 static void 264 build_facs(GArray *table_data, GArray *linker) 265 { 266 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 267 memcpy(&facs->signature, "FACS", 4); 268 facs->length = cpu_to_le32(sizeof(*facs)); 269 } 270 271 /* Load chipset information in FADT */ 272 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) 273 { 274 fadt->model = 1; 275 fadt->reserved1 = 0; 276 fadt->sci_int = cpu_to_le16(pm->sci_int); 277 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD); 278 fadt->acpi_enable = pm->acpi_enable_cmd; 279 fadt->acpi_disable = pm->acpi_disable_cmd; 280 /* EVT, CNT, TMR offset matches hw/acpi/core.c */ 281 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base); 282 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04); 283 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08); 284 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk); 285 /* EVT, CNT, TMR length matches hw/acpi/core.c */ 286 fadt->pm1_evt_len = 4; 287 fadt->pm1_cnt_len = 2; 288 fadt->pm_tmr_len = 4; 289 fadt->gpe0_blk_len = pm->gpe0_blk_len; 290 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */ 291 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */ 292 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) | 293 (1 << ACPI_FADT_F_PROC_C1) | 294 (1 << ACPI_FADT_F_SLP_BUTTON) | 295 (1 << ACPI_FADT_F_RTC_S4)); 296 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK); 297 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs 298 * For more than 8 CPUs, "Clustered Logical" mode has to be used 299 */ 300 if (max_cpus > 8) { 301 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); 302 } 303 fadt->century = RTC_CENTURY; 304 } 305 306 307 /* FADT */ 308 static void 309 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, 310 unsigned facs, unsigned dsdt, 311 const char *oem_id, const char *oem_table_id) 312 { 313 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); 314 315 fadt->firmware_ctrl = cpu_to_le32(facs); 316 /* FACS address to be filled by Guest linker */ 317 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 318 ACPI_BUILD_TABLE_FILE, 319 table_data, &fadt->firmware_ctrl, 320 sizeof fadt->firmware_ctrl); 321 322 fadt->dsdt = cpu_to_le32(dsdt); 323 /* DSDT address to be filled by Guest linker */ 324 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 325 ACPI_BUILD_TABLE_FILE, 326 table_data, &fadt->dsdt, 327 sizeof fadt->dsdt); 328 329 fadt_setup(fadt, pm); 330 331 build_header(linker, table_data, 332 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id); 333 } 334 335 static void 336 build_madt(GArray *table_data, GArray *linker, PCMachineState *pcms) 337 { 338 MachineClass *mc = MACHINE_GET_CLASS(pcms); 339 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms)); 340 int madt_start = table_data->len; 341 342 AcpiMultipleApicTable *madt; 343 AcpiMadtIoApic *io_apic; 344 AcpiMadtIntsrcovr *intsrcovr; 345 AcpiMadtLocalNmi *local_nmi; 346 int i; 347 348 madt = acpi_data_push(table_data, sizeof *madt); 349 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 350 madt->flags = cpu_to_le32(1); 351 352 for (i = 0; i < apic_ids->len; i++) { 353 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic); 354 int apic_id = apic_ids->cpus[i].arch_id; 355 356 apic->type = ACPI_APIC_PROCESSOR; 357 apic->length = sizeof(*apic); 358 apic->processor_id = apic_id; 359 apic->local_apic_id = apic_id; 360 if (apic_ids->cpus[i].cpu != NULL) { 361 apic->flags = cpu_to_le32(1); 362 } else { 363 /* ACPI spec says that LAPIC entry for non present 364 * CPU may be omitted from MADT or it must be marked 365 * as disabled. However omitting non present CPU from 366 * MADT breaks hotplug on linux. So possible CPUs 367 * should be put in MADT but kept disabled. 368 */ 369 apic->flags = cpu_to_le32(0); 370 } 371 } 372 g_free(apic_ids); 373 374 io_apic = acpi_data_push(table_data, sizeof *io_apic); 375 io_apic->type = ACPI_APIC_IO; 376 io_apic->length = sizeof(*io_apic); 377 #define ACPI_BUILD_IOAPIC_ID 0x0 378 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 379 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 380 io_apic->interrupt = cpu_to_le32(0); 381 382 if (pcms->apic_xrupt_override) { 383 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 384 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 385 intsrcovr->length = sizeof(*intsrcovr); 386 intsrcovr->source = 0; 387 intsrcovr->gsi = cpu_to_le32(2); 388 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 389 } 390 for (i = 1; i < 16; i++) { 391 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 392 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 393 /* No need for a INT source override structure. */ 394 continue; 395 } 396 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 397 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 398 intsrcovr->length = sizeof(*intsrcovr); 399 intsrcovr->source = i; 400 intsrcovr->gsi = cpu_to_le32(i); 401 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 402 } 403 404 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 405 local_nmi->type = ACPI_APIC_LOCAL_NMI; 406 local_nmi->length = sizeof(*local_nmi); 407 local_nmi->processor_id = 0xff; /* all processors */ 408 local_nmi->flags = cpu_to_le16(0); 409 local_nmi->lint = 1; /* ACPI_LINT1 */ 410 411 build_header(linker, table_data, 412 (void *)(table_data->data + madt_start), "APIC", 413 table_data->len - madt_start, 1, NULL, NULL); 414 } 415 416 /* Assign BSEL property to all buses. In the future, this can be changed 417 * to only assign to buses that support hotplug. 418 */ 419 static void *acpi_set_bsel(PCIBus *bus, void *opaque) 420 { 421 unsigned *bsel_alloc = opaque; 422 unsigned *bus_bsel; 423 424 if (qbus_is_hotpluggable(BUS(bus))) { 425 bus_bsel = g_malloc(sizeof *bus_bsel); 426 427 *bus_bsel = (*bsel_alloc)++; 428 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, 429 bus_bsel, NULL); 430 } 431 432 return bsel_alloc; 433 } 434 435 static void acpi_set_pci_info(void) 436 { 437 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ 438 unsigned bsel_alloc = 0; 439 440 if (bus) { 441 /* Scan all PCI buses. Set property to enable acpi based hotplug. */ 442 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc); 443 } 444 } 445 446 static void build_append_pcihp_notify_entry(Aml *method, int slot) 447 { 448 Aml *if_ctx; 449 int32_t devfn = PCI_DEVFN(slot, 0); 450 451 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 452 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 453 aml_append(method, if_ctx); 454 } 455 456 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 457 bool pcihp_bridge_en) 458 { 459 Aml *dev, *notify_method, *method; 460 QObject *bsel; 461 PCIBus *sec; 462 int i; 463 464 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 465 if (bsel) { 466 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 467 468 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 469 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 470 } 471 472 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 473 DeviceClass *dc; 474 PCIDeviceClass *pc; 475 PCIDevice *pdev = bus->devices[i]; 476 int slot = PCI_SLOT(i); 477 bool hotplug_enabled_dev; 478 bool bridge_in_acpi; 479 480 if (!pdev) { 481 if (bsel) { /* add hotplug slots for non present devices */ 482 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 483 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 484 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 485 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 486 aml_append(method, 487 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 488 ); 489 aml_append(dev, method); 490 aml_append(parent_scope, dev); 491 492 build_append_pcihp_notify_entry(notify_method, slot); 493 } 494 continue; 495 } 496 497 pc = PCI_DEVICE_GET_CLASS(pdev); 498 dc = DEVICE_GET_CLASS(pdev); 499 500 /* When hotplug for bridges is enabled, bridges are 501 * described in ACPI separately (see build_pci_bus_end). 502 * In this case they aren't themselves hot-pluggable. 503 * Hotplugged bridges *are* hot-pluggable. 504 */ 505 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 506 !DEVICE(pdev)->hotplugged; 507 508 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 509 510 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 511 continue; 512 } 513 514 /* start to compose PCI slot descriptor */ 515 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 516 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 517 518 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 519 /* add VGA specific AML methods */ 520 int s3d; 521 522 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 523 s3d = 3; 524 } else { 525 s3d = 0; 526 } 527 528 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 529 aml_append(method, aml_return(aml_int(0))); 530 aml_append(dev, method); 531 532 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 533 aml_append(method, aml_return(aml_int(0))); 534 aml_append(dev, method); 535 536 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 537 aml_append(method, aml_return(aml_int(s3d))); 538 aml_append(dev, method); 539 } else if (hotplug_enabled_dev) { 540 /* add _SUN/_EJ0 to make slot hotpluggable */ 541 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 542 543 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 544 aml_append(method, 545 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 546 ); 547 aml_append(dev, method); 548 549 if (bsel) { 550 build_append_pcihp_notify_entry(notify_method, slot); 551 } 552 } else if (bridge_in_acpi) { 553 /* 554 * device is coldplugged bridge, 555 * add child device descriptions into its scope 556 */ 557 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 558 559 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 560 } 561 /* slot descriptor has been composed, add it into parent context */ 562 aml_append(parent_scope, dev); 563 } 564 565 if (bsel) { 566 aml_append(parent_scope, notify_method); 567 } 568 569 /* Append PCNT method to notify about events on local and child buses. 570 * Add unconditionally for root since DSDT expects it. 571 */ 572 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 573 574 /* If bus supports hotplug select it and notify about local events */ 575 if (bsel) { 576 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel)); 577 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 578 aml_append(method, 579 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 580 ); 581 aml_append(method, 582 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 583 ); 584 } 585 586 /* Notify about child bus events in any case */ 587 if (pcihp_bridge_en) { 588 QLIST_FOREACH(sec, &bus->child, sibling) { 589 int32_t devfn = sec->parent_dev->devfn; 590 591 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 592 } 593 } 594 aml_append(parent_scope, method); 595 qobject_decref(bsel); 596 } 597 598 /** 599 * build_prt_entry: 600 * @link_name: link name for PCI route entry 601 * 602 * build AML package containing a PCI route entry for @link_name 603 */ 604 static Aml *build_prt_entry(const char *link_name) 605 { 606 Aml *a_zero = aml_int(0); 607 Aml *pkg = aml_package(4); 608 aml_append(pkg, a_zero); 609 aml_append(pkg, a_zero); 610 aml_append(pkg, aml_name("%s", link_name)); 611 aml_append(pkg, a_zero); 612 return pkg; 613 } 614 615 /* 616 * initialize_route - Initialize the interrupt routing rule 617 * through a specific LINK: 618 * if (lnk_idx == idx) 619 * route using link 'link_name' 620 */ 621 static Aml *initialize_route(Aml *route, const char *link_name, 622 Aml *lnk_idx, int idx) 623 { 624 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 625 Aml *pkg = build_prt_entry(link_name); 626 627 aml_append(if_ctx, aml_store(pkg, route)); 628 629 return if_ctx; 630 } 631 632 /* 633 * build_prt - Define interrupt rounting rules 634 * 635 * Returns an array of 128 routes, one for each device, 636 * based on device location. 637 * The main goal is to equaly distribute the interrupts 638 * over the 4 existing ACPI links (works only for i440fx). 639 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 640 * 641 */ 642 static Aml *build_prt(bool is_pci0_prt) 643 { 644 Aml *method, *while_ctx, *pin, *res; 645 646 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 647 res = aml_local(0); 648 pin = aml_local(1); 649 aml_append(method, aml_store(aml_package(128), res)); 650 aml_append(method, aml_store(aml_int(0), pin)); 651 652 /* while (pin < 128) */ 653 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 654 { 655 Aml *slot = aml_local(2); 656 Aml *lnk_idx = aml_local(3); 657 Aml *route = aml_local(4); 658 659 /* slot = pin >> 2 */ 660 aml_append(while_ctx, 661 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 662 /* lnk_idx = (slot + pin) & 3 */ 663 aml_append(while_ctx, 664 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 665 lnk_idx)); 666 667 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 668 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 669 if (is_pci0_prt) { 670 Aml *if_device_1, *if_pin_4, *else_pin_4; 671 672 /* device 1 is the power-management device, needs SCI */ 673 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 674 { 675 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 676 { 677 aml_append(if_pin_4, 678 aml_store(build_prt_entry("LNKS"), route)); 679 } 680 aml_append(if_device_1, if_pin_4); 681 else_pin_4 = aml_else(); 682 { 683 aml_append(else_pin_4, 684 aml_store(build_prt_entry("LNKA"), route)); 685 } 686 aml_append(if_device_1, else_pin_4); 687 } 688 aml_append(while_ctx, if_device_1); 689 } else { 690 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 691 } 692 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 693 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 694 695 /* route[0] = 0x[slot]FFFF */ 696 aml_append(while_ctx, 697 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 698 NULL), 699 aml_index(route, aml_int(0)))); 700 /* route[1] = pin & 3 */ 701 aml_append(while_ctx, 702 aml_store(aml_and(pin, aml_int(3), NULL), 703 aml_index(route, aml_int(1)))); 704 /* res[pin] = route */ 705 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 706 /* pin++ */ 707 aml_append(while_ctx, aml_increment(pin)); 708 } 709 aml_append(method, while_ctx); 710 /* return res*/ 711 aml_append(method, aml_return(res)); 712 713 return method; 714 } 715 716 typedef struct CrsRangeEntry { 717 uint64_t base; 718 uint64_t limit; 719 } CrsRangeEntry; 720 721 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 722 { 723 CrsRangeEntry *entry; 724 725 entry = g_malloc(sizeof(*entry)); 726 entry->base = base; 727 entry->limit = limit; 728 729 g_ptr_array_add(ranges, entry); 730 } 731 732 static void crs_range_free(gpointer data) 733 { 734 CrsRangeEntry *entry = (CrsRangeEntry *)data; 735 g_free(entry); 736 } 737 738 static gint crs_range_compare(gconstpointer a, gconstpointer b) 739 { 740 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 741 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 742 743 return (int64_t)entry_a->base - (int64_t)entry_b->base; 744 } 745 746 /* 747 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 748 * interval, computes the 'free' ranges from the same interval. 749 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 750 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 751 */ 752 static void crs_replace_with_free_ranges(GPtrArray *ranges, 753 uint64_t start, uint64_t end) 754 { 755 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free); 756 uint64_t free_base = start; 757 int i; 758 759 g_ptr_array_sort(ranges, crs_range_compare); 760 for (i = 0; i < ranges->len; i++) { 761 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 762 763 if (free_base < used->base) { 764 crs_range_insert(free_ranges, free_base, used->base - 1); 765 } 766 767 free_base = used->limit + 1; 768 } 769 770 if (free_base < end) { 771 crs_range_insert(free_ranges, free_base, end); 772 } 773 774 g_ptr_array_set_size(ranges, 0); 775 for (i = 0; i < free_ranges->len; i++) { 776 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 777 } 778 779 g_ptr_array_free(free_ranges, false); 780 } 781 782 /* 783 * crs_range_merge - merges adjacent ranges in the given array. 784 * Array elements are deleted and replaced with the merged ranges. 785 */ 786 static void crs_range_merge(GPtrArray *range) 787 { 788 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 789 CrsRangeEntry *entry; 790 uint64_t range_base, range_limit; 791 int i; 792 793 if (!range->len) { 794 return; 795 } 796 797 g_ptr_array_sort(range, crs_range_compare); 798 799 entry = g_ptr_array_index(range, 0); 800 range_base = entry->base; 801 range_limit = entry->limit; 802 for (i = 1; i < range->len; i++) { 803 entry = g_ptr_array_index(range, i); 804 if (entry->base - 1 == range_limit) { 805 range_limit = entry->limit; 806 } else { 807 crs_range_insert(tmp, range_base, range_limit); 808 range_base = entry->base; 809 range_limit = entry->limit; 810 } 811 } 812 crs_range_insert(tmp, range_base, range_limit); 813 814 g_ptr_array_set_size(range, 0); 815 for (i = 0; i < tmp->len; i++) { 816 entry = g_ptr_array_index(tmp, i); 817 crs_range_insert(range, entry->base, entry->limit); 818 } 819 g_ptr_array_free(tmp, true); 820 } 821 822 static Aml *build_crs(PCIHostState *host, 823 GPtrArray *io_ranges, GPtrArray *mem_ranges) 824 { 825 Aml *crs = aml_resource_template(); 826 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 827 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 828 CrsRangeEntry *entry; 829 uint8_t max_bus = pci_bus_num(host->bus); 830 uint8_t type; 831 int devfn; 832 int i; 833 834 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 835 uint64_t range_base, range_limit; 836 PCIDevice *dev = host->bus->devices[devfn]; 837 838 if (!dev) { 839 continue; 840 } 841 842 for (i = 0; i < PCI_NUM_REGIONS; i++) { 843 PCIIORegion *r = &dev->io_regions[i]; 844 845 range_base = r->addr; 846 range_limit = r->addr + r->size - 1; 847 848 /* 849 * Work-around for old bioses 850 * that do not support multiple root buses 851 */ 852 if (!range_base || range_base > range_limit) { 853 continue; 854 } 855 856 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 857 crs_range_insert(host_io_ranges, range_base, range_limit); 858 } else { /* "memory" */ 859 crs_range_insert(host_mem_ranges, range_base, range_limit); 860 } 861 } 862 863 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 864 if (type == PCI_HEADER_TYPE_BRIDGE) { 865 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 866 if (subordinate > max_bus) { 867 max_bus = subordinate; 868 } 869 870 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 871 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 872 873 /* 874 * Work-around for old bioses 875 * that do not support multiple root buses 876 */ 877 if (range_base && range_base <= range_limit) { 878 crs_range_insert(host_io_ranges, range_base, range_limit); 879 } 880 881 range_base = 882 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 883 range_limit = 884 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 885 886 /* 887 * Work-around for old bioses 888 * that do not support multiple root buses 889 */ 890 if (range_base && range_base <= range_limit) { 891 crs_range_insert(host_mem_ranges, range_base, range_limit); 892 } 893 894 range_base = 895 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 896 range_limit = 897 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 898 899 /* 900 * Work-around for old bioses 901 * that do not support multiple root buses 902 */ 903 if (range_base && range_base <= range_limit) { 904 crs_range_insert(host_mem_ranges, range_base, range_limit); 905 } 906 } 907 } 908 909 crs_range_merge(host_io_ranges); 910 for (i = 0; i < host_io_ranges->len; i++) { 911 entry = g_ptr_array_index(host_io_ranges, i); 912 aml_append(crs, 913 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 914 AML_POS_DECODE, AML_ENTIRE_RANGE, 915 0, entry->base, entry->limit, 0, 916 entry->limit - entry->base + 1)); 917 crs_range_insert(io_ranges, entry->base, entry->limit); 918 } 919 g_ptr_array_free(host_io_ranges, true); 920 921 crs_range_merge(host_mem_ranges); 922 for (i = 0; i < host_mem_ranges->len; i++) { 923 entry = g_ptr_array_index(host_mem_ranges, i); 924 aml_append(crs, 925 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 926 AML_MAX_FIXED, AML_NON_CACHEABLE, 927 AML_READ_WRITE, 928 0, entry->base, entry->limit, 0, 929 entry->limit - entry->base + 1)); 930 crs_range_insert(mem_ranges, entry->base, entry->limit); 931 } 932 g_ptr_array_free(host_mem_ranges, true); 933 934 aml_append(crs, 935 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 936 0, 937 pci_bus_num(host->bus), 938 max_bus, 939 0, 940 max_bus - pci_bus_num(host->bus) + 1)); 941 942 return crs; 943 } 944 945 static void build_processor_devices(Aml *sb_scope, MachineState *machine, 946 AcpiPmInfo *pm) 947 { 948 int i, apic_idx; 949 Aml *dev; 950 Aml *crs; 951 Aml *pkg; 952 Aml *field; 953 Aml *ifctx; 954 Aml *method; 955 MachineClass *mc = MACHINE_GET_CLASS(machine); 956 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 957 PCMachineState *pcms = PC_MACHINE(machine); 958 959 /* The current AML generator can cover the APIC ID range [0..255], 960 * inclusive, for VCPU hotplug. */ 961 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); 962 g_assert(pcms->apic_id_limit <= ACPI_CPU_HOTPLUG_ID_LIMIT); 963 964 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ 965 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); 966 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 967 aml_append(dev, 968 aml_name_decl("_UID", aml_string("CPU Hotplug resources")) 969 ); 970 /* device present, functioning, decoding, not shown in UI */ 971 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 972 crs = aml_resource_template(); 973 aml_append(crs, 974 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, 975 pm->cpu_hp_io_len) 976 ); 977 aml_append(dev, aml_name_decl("_CRS", crs)); 978 aml_append(sb_scope, dev); 979 /* declare CPU hotplug MMIO region and PRS field to access it */ 980 aml_append(sb_scope, aml_operation_region( 981 "PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len)); 982 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 983 aml_append(field, aml_named_field("PRS", 256)); 984 aml_append(sb_scope, field); 985 986 /* build Processor object for each processor */ 987 for (i = 0; i < apic_ids->len; i++) { 988 int apic_id = apic_ids->cpus[i].arch_id; 989 990 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); 991 992 dev = aml_processor(apic_id, 0, 0, "CP%.02X", apic_id); 993 994 method = aml_method("_MAT", 0, AML_NOTSERIALIZED); 995 aml_append(method, 996 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(apic_id)))); 997 aml_append(dev, method); 998 999 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1000 aml_append(method, 1001 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(apic_id)))); 1002 aml_append(dev, method); 1003 1004 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1005 aml_append(method, 1006 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(apic_id), 1007 aml_arg(0))) 1008 ); 1009 aml_append(dev, method); 1010 1011 aml_append(sb_scope, dev); 1012 } 1013 1014 /* build this code: 1015 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} 1016 */ 1017 /* Arg0 = Processor ID = APIC ID */ 1018 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); 1019 for (i = 0; i < apic_ids->len; i++) { 1020 int apic_id = apic_ids->cpus[i].arch_id; 1021 1022 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(apic_id))); 1023 aml_append(ifctx, 1024 aml_notify(aml_name("CP%.02X", apic_id), aml_arg(1)) 1025 ); 1026 aml_append(method, ifctx); 1027 } 1028 aml_append(sb_scope, method); 1029 1030 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" 1031 * 1032 * Note: The ability to create variable-sized packages was first 1033 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages 1034 * ith up to 255 elements. Windows guests up to win2k8 fail when 1035 * VarPackageOp is used. 1036 */ 1037 pkg = pcms->apic_id_limit <= 255 ? aml_package(pcms->apic_id_limit) : 1038 aml_varpackage(pcms->apic_id_limit); 1039 1040 for (i = 0, apic_idx = 0; i < apic_ids->len; i++) { 1041 int apic_id = apic_ids->cpus[i].arch_id; 1042 1043 for (; apic_idx < apic_id; apic_idx++) { 1044 aml_append(pkg, aml_int(0)); 1045 } 1046 aml_append(pkg, aml_int(apic_ids->cpus[i].cpu ? 1 : 0)); 1047 apic_idx = apic_id + 1; 1048 } 1049 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg)); 1050 g_free(apic_ids); 1051 } 1052 1053 static void build_memory_devices(Aml *sb_scope, int nr_mem, 1054 uint16_t io_base, uint16_t io_len) 1055 { 1056 int i; 1057 Aml *scope; 1058 Aml *crs; 1059 Aml *field; 1060 Aml *dev; 1061 Aml *method; 1062 Aml *ifctx; 1063 1064 /* build memory devices */ 1065 assert(nr_mem <= ACPI_MAX_RAM_SLOTS); 1066 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE); 1067 aml_append(scope, 1068 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem)) 1069 ); 1070 1071 crs = aml_resource_template(); 1072 aml_append(crs, 1073 aml_io(AML_DECODE16, io_base, io_base, 0, io_len) 1074 ); 1075 aml_append(scope, aml_name_decl("_CRS", crs)); 1076 1077 aml_append(scope, aml_operation_region( 1078 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO, 1079 aml_int(io_base), io_len) 1080 ); 1081 1082 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, 1083 AML_NOLOCK, AML_PRESERVE); 1084 aml_append(field, /* read only */ 1085 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32)); 1086 aml_append(field, /* read only */ 1087 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32)); 1088 aml_append(field, /* read only */ 1089 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32)); 1090 aml_append(field, /* read only */ 1091 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32)); 1092 aml_append(field, /* read only */ 1093 aml_named_field(MEMORY_SLOT_PROXIMITY, 32)); 1094 aml_append(scope, field); 1095 1096 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC, 1097 AML_NOLOCK, AML_WRITE_AS_ZEROS); 1098 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); 1099 aml_append(field, /* 1 if enabled, read only */ 1100 aml_named_field(MEMORY_SLOT_ENABLED, 1)); 1101 aml_append(field, 1102 /*(read) 1 if has a insert event. (write) 1 to clear event */ 1103 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1)); 1104 aml_append(field, 1105 /* (read) 1 if has a remove event. (write) 1 to clear event */ 1106 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1)); 1107 aml_append(field, 1108 /* initiates device eject, write only */ 1109 aml_named_field(MEMORY_SLOT_EJECT, 1)); 1110 aml_append(scope, field); 1111 1112 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, 1113 AML_NOLOCK, AML_PRESERVE); 1114 aml_append(field, /* DIMM selector, write only */ 1115 aml_named_field(MEMORY_SLOT_SLECTOR, 32)); 1116 aml_append(field, /* _OST event code, write only */ 1117 aml_named_field(MEMORY_SLOT_OST_EVENT, 32)); 1118 aml_append(field, /* _OST status code, write only */ 1119 aml_named_field(MEMORY_SLOT_OST_STATUS, 32)); 1120 aml_append(scope, field); 1121 aml_append(sb_scope, scope); 1122 1123 for (i = 0; i < nr_mem; i++) { 1124 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "." 1125 const char *s; 1126 1127 dev = aml_device("MP%02X", i); 1128 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); 1129 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); 1130 1131 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1132 s = BASEPATH MEMORY_SLOT_CRS_METHOD; 1133 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1134 aml_append(dev, method); 1135 1136 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1137 s = BASEPATH MEMORY_SLOT_STATUS_METHOD; 1138 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1139 aml_append(dev, method); 1140 1141 method = aml_method("_PXM", 0, AML_NOTSERIALIZED); 1142 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD; 1143 aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); 1144 aml_append(dev, method); 1145 1146 method = aml_method("_OST", 3, AML_NOTSERIALIZED); 1147 s = BASEPATH MEMORY_SLOT_OST_METHOD; 1148 1149 aml_append(method, aml_return(aml_call4( 1150 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) 1151 ))); 1152 aml_append(dev, method); 1153 1154 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 1155 s = BASEPATH MEMORY_SLOT_EJECT_METHOD; 1156 aml_append(method, aml_return(aml_call2( 1157 s, aml_name("_UID"), aml_arg(0)))); 1158 aml_append(dev, method); 1159 1160 aml_append(sb_scope, dev); 1161 } 1162 1163 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { 1164 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } 1165 */ 1166 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); 1167 for (i = 0; i < nr_mem; i++) { 1168 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); 1169 aml_append(ifctx, 1170 aml_notify(aml_name("MP%.02X", i), aml_arg(1)) 1171 ); 1172 aml_append(method, ifctx); 1173 } 1174 aml_append(sb_scope, method); 1175 } 1176 1177 static void build_hpet_aml(Aml *table) 1178 { 1179 Aml *crs; 1180 Aml *field; 1181 Aml *method; 1182 Aml *if_ctx; 1183 Aml *scope = aml_scope("_SB"); 1184 Aml *dev = aml_device("HPET"); 1185 Aml *zero = aml_int(0); 1186 Aml *id = aml_local(0); 1187 Aml *period = aml_local(1); 1188 1189 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1190 aml_append(dev, aml_name_decl("_UID", zero)); 1191 1192 aml_append(dev, 1193 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 1194 HPET_LEN)); 1195 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1196 aml_append(field, aml_named_field("VEND", 32)); 1197 aml_append(field, aml_named_field("PRD", 32)); 1198 aml_append(dev, field); 1199 1200 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1201 aml_append(method, aml_store(aml_name("VEND"), id)); 1202 aml_append(method, aml_store(aml_name("PRD"), period)); 1203 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1204 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1205 aml_equal(id, aml_int(0xffff)))); 1206 { 1207 aml_append(if_ctx, aml_return(zero)); 1208 } 1209 aml_append(method, if_ctx); 1210 1211 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1212 aml_lgreater(period, aml_int(100000000)))); 1213 { 1214 aml_append(if_ctx, aml_return(zero)); 1215 } 1216 aml_append(method, if_ctx); 1217 1218 aml_append(method, aml_return(aml_int(0x0F))); 1219 aml_append(dev, method); 1220 1221 crs = aml_resource_template(); 1222 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1223 aml_append(dev, aml_name_decl("_CRS", crs)); 1224 1225 aml_append(scope, dev); 1226 aml_append(table, scope); 1227 } 1228 1229 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1230 { 1231 Aml *dev, *fdi; 1232 uint8_t maxc, maxh, maxs; 1233 1234 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1235 1236 dev = aml_device("FLP%c", 'A' + idx); 1237 1238 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1239 1240 fdi = aml_package(16); 1241 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1242 aml_append(fdi, 1243 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1244 /* 1245 * the values below are the limits of the drive, and are thus independent 1246 * of the inserted media 1247 */ 1248 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1249 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1250 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1251 /* 1252 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1253 * the drive type, so shall we 1254 */ 1255 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1256 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1257 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1258 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1259 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1260 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1261 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1262 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1263 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1264 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1265 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1266 1267 aml_append(dev, aml_name_decl("_FDI", fdi)); 1268 return dev; 1269 } 1270 1271 static Aml *build_fdc_device_aml(ISADevice *fdc) 1272 { 1273 int i; 1274 Aml *dev; 1275 Aml *crs; 1276 1277 #define ACPI_FDE_MAX_FD 4 1278 uint32_t fde_buf[5] = { 1279 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1280 cpu_to_le32(2) /* tape presence (2 == never present) */ 1281 }; 1282 1283 dev = aml_device("FDC0"); 1284 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1285 1286 crs = aml_resource_template(); 1287 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1288 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1289 aml_append(crs, aml_irq_no_flags(6)); 1290 aml_append(crs, 1291 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1292 aml_append(dev, aml_name_decl("_CRS", crs)); 1293 1294 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1295 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1296 1297 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1298 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1299 aml_append(dev, build_fdinfo_aml(i, type)); 1300 } 1301 } 1302 aml_append(dev, aml_name_decl("_FDE", 1303 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1304 1305 return dev; 1306 } 1307 1308 static Aml *build_rtc_device_aml(void) 1309 { 1310 Aml *dev; 1311 Aml *crs; 1312 1313 dev = aml_device("RTC"); 1314 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1315 crs = aml_resource_template(); 1316 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1317 aml_append(crs, aml_irq_no_flags(8)); 1318 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1319 aml_append(dev, aml_name_decl("_CRS", crs)); 1320 1321 return dev; 1322 } 1323 1324 static Aml *build_kbd_device_aml(void) 1325 { 1326 Aml *dev; 1327 Aml *crs; 1328 Aml *method; 1329 1330 dev = aml_device("KBD"); 1331 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1332 1333 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1334 aml_append(method, aml_return(aml_int(0x0f))); 1335 aml_append(dev, method); 1336 1337 crs = aml_resource_template(); 1338 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1339 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1340 aml_append(crs, aml_irq_no_flags(1)); 1341 aml_append(dev, aml_name_decl("_CRS", crs)); 1342 1343 return dev; 1344 } 1345 1346 static Aml *build_mouse_device_aml(void) 1347 { 1348 Aml *dev; 1349 Aml *crs; 1350 Aml *method; 1351 1352 dev = aml_device("MOU"); 1353 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1354 1355 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1356 aml_append(method, aml_return(aml_int(0x0f))); 1357 aml_append(dev, method); 1358 1359 crs = aml_resource_template(); 1360 aml_append(crs, aml_irq_no_flags(12)); 1361 aml_append(dev, aml_name_decl("_CRS", crs)); 1362 1363 return dev; 1364 } 1365 1366 static Aml *build_lpt_device_aml(void) 1367 { 1368 Aml *dev; 1369 Aml *crs; 1370 Aml *method; 1371 Aml *if_ctx; 1372 Aml *else_ctx; 1373 Aml *zero = aml_int(0); 1374 Aml *is_present = aml_local(0); 1375 1376 dev = aml_device("LPT"); 1377 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1378 1379 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1380 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1381 if_ctx = aml_if(aml_equal(is_present, zero)); 1382 { 1383 aml_append(if_ctx, aml_return(aml_int(0x00))); 1384 } 1385 aml_append(method, if_ctx); 1386 else_ctx = aml_else(); 1387 { 1388 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1389 } 1390 aml_append(method, else_ctx); 1391 aml_append(dev, method); 1392 1393 crs = aml_resource_template(); 1394 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1395 aml_append(crs, aml_irq_no_flags(7)); 1396 aml_append(dev, aml_name_decl("_CRS", crs)); 1397 1398 return dev; 1399 } 1400 1401 static Aml *build_com_device_aml(uint8_t uid) 1402 { 1403 Aml *dev; 1404 Aml *crs; 1405 Aml *method; 1406 Aml *if_ctx; 1407 Aml *else_ctx; 1408 Aml *zero = aml_int(0); 1409 Aml *is_present = aml_local(0); 1410 const char *enabled_field = "CAEN"; 1411 uint8_t irq = 4; 1412 uint16_t io_port = 0x03F8; 1413 1414 assert(uid == 1 || uid == 2); 1415 if (uid == 2) { 1416 enabled_field = "CBEN"; 1417 irq = 3; 1418 io_port = 0x02F8; 1419 } 1420 1421 dev = aml_device("COM%d", uid); 1422 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1423 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1424 1425 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1426 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1427 if_ctx = aml_if(aml_equal(is_present, zero)); 1428 { 1429 aml_append(if_ctx, aml_return(aml_int(0x00))); 1430 } 1431 aml_append(method, if_ctx); 1432 else_ctx = aml_else(); 1433 { 1434 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1435 } 1436 aml_append(method, else_ctx); 1437 aml_append(dev, method); 1438 1439 crs = aml_resource_template(); 1440 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1441 aml_append(crs, aml_irq_no_flags(irq)); 1442 aml_append(dev, aml_name_decl("_CRS", crs)); 1443 1444 return dev; 1445 } 1446 1447 static void build_isa_devices_aml(Aml *table) 1448 { 1449 ISADevice *fdc = pc_find_fdc0(); 1450 1451 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1452 1453 aml_append(scope, build_rtc_device_aml()); 1454 aml_append(scope, build_kbd_device_aml()); 1455 aml_append(scope, build_mouse_device_aml()); 1456 if (fdc) { 1457 aml_append(scope, build_fdc_device_aml(fdc)); 1458 } 1459 aml_append(scope, build_lpt_device_aml()); 1460 aml_append(scope, build_com_device_aml(1)); 1461 aml_append(scope, build_com_device_aml(2)); 1462 1463 aml_append(table, scope); 1464 } 1465 1466 static void build_dbg_aml(Aml *table) 1467 { 1468 Aml *field; 1469 Aml *method; 1470 Aml *while_ctx; 1471 Aml *scope = aml_scope("\\"); 1472 Aml *buf = aml_local(0); 1473 Aml *len = aml_local(1); 1474 Aml *idx = aml_local(2); 1475 1476 aml_append(scope, 1477 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1478 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1479 aml_append(field, aml_named_field("DBGB", 8)); 1480 aml_append(scope, field); 1481 1482 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1483 1484 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1485 aml_append(method, aml_to_buffer(buf, buf)); 1486 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1487 aml_append(method, aml_store(aml_int(0), idx)); 1488 1489 while_ctx = aml_while(aml_lless(idx, len)); 1490 aml_append(while_ctx, 1491 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1492 aml_append(while_ctx, aml_increment(idx)); 1493 aml_append(method, while_ctx); 1494 1495 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1496 aml_append(scope, method); 1497 1498 aml_append(table, scope); 1499 } 1500 1501 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1502 { 1503 Aml *dev; 1504 Aml *crs; 1505 Aml *method; 1506 uint32_t irqs[] = {5, 10, 11}; 1507 1508 dev = aml_device("%s", name); 1509 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1510 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1511 1512 crs = aml_resource_template(); 1513 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1514 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1515 aml_append(dev, aml_name_decl("_PRS", crs)); 1516 1517 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1518 aml_append(method, aml_return(aml_call1("IQST", reg))); 1519 aml_append(dev, method); 1520 1521 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1522 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1523 aml_append(dev, method); 1524 1525 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1526 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1527 aml_append(dev, method); 1528 1529 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1530 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1531 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1532 aml_append(dev, method); 1533 1534 return dev; 1535 } 1536 1537 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1538 { 1539 Aml *dev; 1540 Aml *crs; 1541 Aml *method; 1542 uint32_t irqs; 1543 1544 dev = aml_device("%s", name); 1545 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1546 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1547 1548 crs = aml_resource_template(); 1549 irqs = gsi; 1550 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1551 AML_SHARED, &irqs, 1)); 1552 aml_append(dev, aml_name_decl("_PRS", crs)); 1553 1554 aml_append(dev, aml_name_decl("_CRS", crs)); 1555 1556 /* 1557 * _DIS can be no-op because the interrupt cannot be disabled. 1558 */ 1559 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1560 aml_append(dev, method); 1561 1562 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1563 aml_append(dev, method); 1564 1565 return dev; 1566 } 1567 1568 /* _CRS method - get current settings */ 1569 static Aml *build_iqcr_method(bool is_piix4) 1570 { 1571 Aml *if_ctx; 1572 uint32_t irqs; 1573 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1574 Aml *crs = aml_resource_template(); 1575 1576 irqs = 0; 1577 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1578 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1579 aml_append(method, aml_name_decl("PRR0", crs)); 1580 1581 aml_append(method, 1582 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1583 1584 if (is_piix4) { 1585 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1586 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1587 aml_append(method, if_ctx); 1588 } else { 1589 aml_append(method, 1590 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1591 aml_name("PRRI"))); 1592 } 1593 1594 aml_append(method, aml_return(aml_name("PRR0"))); 1595 return method; 1596 } 1597 1598 /* _STA method - get status */ 1599 static Aml *build_irq_status_method(void) 1600 { 1601 Aml *if_ctx; 1602 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1603 1604 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1605 aml_append(if_ctx, aml_return(aml_int(0x09))); 1606 aml_append(method, if_ctx); 1607 aml_append(method, aml_return(aml_int(0x0B))); 1608 return method; 1609 } 1610 1611 static void build_piix4_pci0_int(Aml *table) 1612 { 1613 Aml *dev; 1614 Aml *crs; 1615 Aml *field; 1616 Aml *method; 1617 uint32_t irqs; 1618 Aml *sb_scope = aml_scope("_SB"); 1619 Aml *pci0_scope = aml_scope("PCI0"); 1620 1621 aml_append(pci0_scope, build_prt(true)); 1622 aml_append(sb_scope, pci0_scope); 1623 1624 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1625 aml_append(field, aml_named_field("PRQ0", 8)); 1626 aml_append(field, aml_named_field("PRQ1", 8)); 1627 aml_append(field, aml_named_field("PRQ2", 8)); 1628 aml_append(field, aml_named_field("PRQ3", 8)); 1629 aml_append(sb_scope, field); 1630 1631 aml_append(sb_scope, build_irq_status_method()); 1632 aml_append(sb_scope, build_iqcr_method(true)); 1633 1634 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1635 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1636 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1637 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1638 1639 dev = aml_device("LNKS"); 1640 { 1641 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1642 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1643 1644 crs = aml_resource_template(); 1645 irqs = 9; 1646 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1647 AML_ACTIVE_HIGH, AML_SHARED, 1648 &irqs, 1)); 1649 aml_append(dev, aml_name_decl("_PRS", crs)); 1650 1651 /* The SCI cannot be disabled and is always attached to GSI 9, 1652 * so these are no-ops. We only need this link to override the 1653 * polarity to active high and match the content of the MADT. 1654 */ 1655 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1656 aml_append(method, aml_return(aml_int(0x0b))); 1657 aml_append(dev, method); 1658 1659 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1660 aml_append(dev, method); 1661 1662 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1663 aml_append(method, aml_return(aml_name("_PRS"))); 1664 aml_append(dev, method); 1665 1666 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1667 aml_append(dev, method); 1668 } 1669 aml_append(sb_scope, dev); 1670 1671 aml_append(table, sb_scope); 1672 } 1673 1674 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1675 { 1676 int i; 1677 int head; 1678 Aml *pkg; 1679 char base = name[3] < 'E' ? 'A' : 'E'; 1680 char *s = g_strdup(name); 1681 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1682 1683 assert(strlen(s) == 4); 1684 1685 head = name[3] - base; 1686 for (i = 0; i < 4; i++) { 1687 if (head + i > 3) { 1688 head = i * -1; 1689 } 1690 s[3] = base + head + i; 1691 pkg = aml_package(4); 1692 aml_append(pkg, a_nr); 1693 aml_append(pkg, aml_int(i)); 1694 aml_append(pkg, aml_name("%s", s)); 1695 aml_append(pkg, aml_int(0)); 1696 aml_append(ctx, pkg); 1697 } 1698 g_free(s); 1699 } 1700 1701 static Aml *build_q35_routing_table(const char *str) 1702 { 1703 int i; 1704 Aml *pkg; 1705 char *name = g_strdup_printf("%s ", str); 1706 1707 pkg = aml_package(128); 1708 for (i = 0; i < 0x18; i++) { 1709 name[3] = 'E' + (i & 0x3); 1710 append_q35_prt_entry(pkg, i, name); 1711 } 1712 1713 name[3] = 'E'; 1714 append_q35_prt_entry(pkg, 0x18, name); 1715 1716 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1717 for (i = 0x0019; i < 0x1e; i++) { 1718 name[3] = 'A'; 1719 append_q35_prt_entry(pkg, i, name); 1720 } 1721 1722 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1723 name[3] = 'E'; 1724 append_q35_prt_entry(pkg, 0x1e, name); 1725 name[3] = 'A'; 1726 append_q35_prt_entry(pkg, 0x1f, name); 1727 1728 g_free(name); 1729 return pkg; 1730 } 1731 1732 static void build_q35_pci0_int(Aml *table) 1733 { 1734 Aml *field; 1735 Aml *method; 1736 Aml *sb_scope = aml_scope("_SB"); 1737 Aml *pci0_scope = aml_scope("PCI0"); 1738 1739 /* Zero => PIC mode, One => APIC Mode */ 1740 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1741 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1742 { 1743 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1744 } 1745 aml_append(table, method); 1746 1747 aml_append(pci0_scope, 1748 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1749 aml_append(pci0_scope, 1750 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1751 1752 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1753 { 1754 Aml *if_ctx; 1755 Aml *else_ctx; 1756 1757 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1758 section 6.2.8.1 */ 1759 /* Note: we provide the same info as the PCI routing 1760 table of the Bochs BIOS */ 1761 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1762 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1763 aml_append(method, if_ctx); 1764 else_ctx = aml_else(); 1765 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1766 aml_append(method, else_ctx); 1767 } 1768 aml_append(pci0_scope, method); 1769 aml_append(sb_scope, pci0_scope); 1770 1771 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1772 aml_append(field, aml_named_field("PRQA", 8)); 1773 aml_append(field, aml_named_field("PRQB", 8)); 1774 aml_append(field, aml_named_field("PRQC", 8)); 1775 aml_append(field, aml_named_field("PRQD", 8)); 1776 aml_append(field, aml_reserved_field(0x20)); 1777 aml_append(field, aml_named_field("PRQE", 8)); 1778 aml_append(field, aml_named_field("PRQF", 8)); 1779 aml_append(field, aml_named_field("PRQG", 8)); 1780 aml_append(field, aml_named_field("PRQH", 8)); 1781 aml_append(sb_scope, field); 1782 1783 aml_append(sb_scope, build_irq_status_method()); 1784 aml_append(sb_scope, build_iqcr_method(false)); 1785 1786 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1787 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1788 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1789 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1790 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1791 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1792 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1793 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1794 1795 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1796 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1797 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1798 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1799 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1800 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1801 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1802 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1803 1804 aml_append(table, sb_scope); 1805 } 1806 1807 static void build_q35_isa_bridge(Aml *table) 1808 { 1809 Aml *dev; 1810 Aml *scope; 1811 Aml *field; 1812 1813 scope = aml_scope("_SB.PCI0"); 1814 dev = aml_device("ISA"); 1815 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1816 1817 /* ICH9 PCI to ISA irq remapping */ 1818 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1819 aml_int(0x60), 0x0C)); 1820 1821 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1822 aml_int(0x80), 0x02)); 1823 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1824 aml_append(field, aml_named_field("COMA", 3)); 1825 aml_append(field, aml_reserved_field(1)); 1826 aml_append(field, aml_named_field("COMB", 3)); 1827 aml_append(field, aml_reserved_field(1)); 1828 aml_append(field, aml_named_field("LPTD", 2)); 1829 aml_append(dev, field); 1830 1831 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1832 aml_int(0x82), 0x02)); 1833 /* enable bits */ 1834 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1835 aml_append(field, aml_named_field("CAEN", 1)); 1836 aml_append(field, aml_named_field("CBEN", 1)); 1837 aml_append(field, aml_named_field("LPEN", 1)); 1838 aml_append(dev, field); 1839 1840 aml_append(scope, dev); 1841 aml_append(table, scope); 1842 } 1843 1844 static void build_piix4_pm(Aml *table) 1845 { 1846 Aml *dev; 1847 Aml *scope; 1848 1849 scope = aml_scope("_SB.PCI0"); 1850 dev = aml_device("PX13"); 1851 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1852 1853 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1854 aml_int(0x00), 0xff)); 1855 aml_append(scope, dev); 1856 aml_append(table, scope); 1857 } 1858 1859 static void build_piix4_isa_bridge(Aml *table) 1860 { 1861 Aml *dev; 1862 Aml *scope; 1863 Aml *field; 1864 1865 scope = aml_scope("_SB.PCI0"); 1866 dev = aml_device("ISA"); 1867 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1868 1869 /* PIIX PCI to ISA irq remapping */ 1870 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1871 aml_int(0x60), 0x04)); 1872 /* enable bits */ 1873 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1874 /* Offset(0x5f),, 7, */ 1875 aml_append(field, aml_reserved_field(0x2f8)); 1876 aml_append(field, aml_reserved_field(7)); 1877 aml_append(field, aml_named_field("LPEN", 1)); 1878 /* Offset(0x67),, 3, */ 1879 aml_append(field, aml_reserved_field(0x38)); 1880 aml_append(field, aml_reserved_field(3)); 1881 aml_append(field, aml_named_field("CAEN", 1)); 1882 aml_append(field, aml_reserved_field(3)); 1883 aml_append(field, aml_named_field("CBEN", 1)); 1884 aml_append(dev, field); 1885 1886 aml_append(scope, dev); 1887 aml_append(table, scope); 1888 } 1889 1890 static void build_piix4_pci_hotplug(Aml *table) 1891 { 1892 Aml *scope; 1893 Aml *field; 1894 Aml *method; 1895 1896 scope = aml_scope("_SB.PCI0"); 1897 1898 aml_append(scope, 1899 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1900 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1901 aml_append(field, aml_named_field("PCIU", 32)); 1902 aml_append(field, aml_named_field("PCID", 32)); 1903 aml_append(scope, field); 1904 1905 aml_append(scope, 1906 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1907 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1908 aml_append(field, aml_named_field("B0EJ", 32)); 1909 aml_append(scope, field); 1910 1911 aml_append(scope, 1912 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1913 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1914 aml_append(field, aml_named_field("BNUM", 32)); 1915 aml_append(scope, field); 1916 1917 aml_append(scope, aml_mutex("BLCK", 0)); 1918 1919 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1920 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1921 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1922 aml_append(method, 1923 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1924 aml_append(method, aml_release(aml_name("BLCK"))); 1925 aml_append(method, aml_return(aml_int(0))); 1926 aml_append(scope, method); 1927 1928 aml_append(table, scope); 1929 } 1930 1931 static Aml *build_q35_osc_method(void) 1932 { 1933 Aml *if_ctx; 1934 Aml *if_ctx2; 1935 Aml *else_ctx; 1936 Aml *method; 1937 Aml *a_cwd1 = aml_name("CDW1"); 1938 Aml *a_ctrl = aml_name("CTRL"); 1939 1940 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1941 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1942 1943 if_ctx = aml_if(aml_equal( 1944 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1945 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1946 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1947 1948 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 1949 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1950 1951 /* 1952 * Always allow native PME, AER (no dependencies) 1953 * Never allow SHPC (no SHPC controller in this system) 1954 */ 1955 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); 1956 1957 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1958 /* Unknown revision */ 1959 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1960 aml_append(if_ctx, if_ctx2); 1961 1962 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1963 /* Capabilities bits were masked */ 1964 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1965 aml_append(if_ctx, if_ctx2); 1966 1967 /* Update DWORD3 in the buffer */ 1968 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1969 aml_append(method, if_ctx); 1970 1971 else_ctx = aml_else(); 1972 /* Unrecognized UUID */ 1973 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1974 aml_append(method, else_ctx); 1975 1976 aml_append(method, aml_return(aml_arg(3))); 1977 return method; 1978 } 1979 1980 static void 1981 build_dsdt(GArray *table_data, GArray *linker, 1982 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1983 PcPciInfo *pci, MachineState *machine) 1984 { 1985 CrsRangeEntry *entry; 1986 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1987 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 1988 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 1989 PCMachineState *pcms = PC_MACHINE(machine); 1990 uint32_t nr_mem = machine->ram_slots; 1991 int root_bus_limit = 0xFF; 1992 PCIBus *bus = NULL; 1993 int i; 1994 1995 dsdt = init_aml_allocator(); 1996 1997 /* Reserve space for header */ 1998 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1999 2000 build_dbg_aml(dsdt); 2001 if (misc->is_piix4) { 2002 sb_scope = aml_scope("_SB"); 2003 dev = aml_device("PCI0"); 2004 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 2005 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 2006 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 2007 aml_append(sb_scope, dev); 2008 aml_append(dsdt, sb_scope); 2009 2010 build_hpet_aml(dsdt); 2011 build_piix4_pm(dsdt); 2012 build_piix4_isa_bridge(dsdt); 2013 build_isa_devices_aml(dsdt); 2014 build_piix4_pci_hotplug(dsdt); 2015 build_piix4_pci0_int(dsdt); 2016 } else { 2017 sb_scope = aml_scope("_SB"); 2018 aml_append(sb_scope, 2019 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c)); 2020 aml_append(sb_scope, 2021 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01)); 2022 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 2023 aml_append(field, aml_named_field("PCIB", 8)); 2024 aml_append(sb_scope, field); 2025 aml_append(dsdt, sb_scope); 2026 2027 sb_scope = aml_scope("_SB"); 2028 dev = aml_device("PCI0"); 2029 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 2030 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 2031 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 2032 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 2033 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 2034 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 2035 aml_append(dev, build_q35_osc_method()); 2036 aml_append(sb_scope, dev); 2037 aml_append(dsdt, sb_scope); 2038 2039 build_hpet_aml(dsdt); 2040 build_q35_isa_bridge(dsdt); 2041 build_isa_devices_aml(dsdt); 2042 build_q35_pci0_int(dsdt); 2043 } 2044 2045 build_cpu_hotplug_aml(dsdt); 2046 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base, 2047 pm->mem_hp_io_len); 2048 2049 scope = aml_scope("_GPE"); 2050 { 2051 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 2052 2053 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED)); 2054 2055 if (misc->is_piix4) { 2056 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 2057 aml_append(method, 2058 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 2059 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 2060 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 2061 aml_append(scope, method); 2062 } else { 2063 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED)); 2064 } 2065 2066 method = aml_method("_E02", 0, AML_NOTSERIALIZED); 2067 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD)); 2068 aml_append(scope, method); 2069 2070 method = aml_method("_E03", 0, AML_NOTSERIALIZED); 2071 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH)); 2072 aml_append(scope, method); 2073 2074 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED)); 2075 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED)); 2076 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED)); 2077 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED)); 2078 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED)); 2079 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED)); 2080 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED)); 2081 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED)); 2082 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED)); 2083 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED)); 2084 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED)); 2085 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED)); 2086 } 2087 aml_append(dsdt, scope); 2088 2089 bus = PC_MACHINE(machine)->bus; 2090 if (bus) { 2091 QLIST_FOREACH(bus, &bus->child, sibling) { 2092 uint8_t bus_num = pci_bus_num(bus); 2093 uint8_t numa_node = pci_bus_numa_node(bus); 2094 2095 /* look only for expander root buses */ 2096 if (!pci_bus_is_root(bus)) { 2097 continue; 2098 } 2099 2100 if (bus_num < root_bus_limit) { 2101 root_bus_limit = bus_num - 1; 2102 } 2103 2104 scope = aml_scope("\\_SB"); 2105 dev = aml_device("PC%.02X", bus_num); 2106 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 2107 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 2108 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 2109 2110 if (numa_node != NUMA_NODE_UNASSIGNED) { 2111 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 2112 } 2113 2114 aml_append(dev, build_prt(false)); 2115 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), 2116 io_ranges, mem_ranges); 2117 aml_append(dev, aml_name_decl("_CRS", crs)); 2118 aml_append(scope, dev); 2119 aml_append(dsdt, scope); 2120 } 2121 } 2122 2123 scope = aml_scope("\\_SB.PCI0"); 2124 /* build PCI0._CRS */ 2125 crs = aml_resource_template(); 2126 aml_append(crs, 2127 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 2128 0x0000, 0x0, root_bus_limit, 2129 0x0000, root_bus_limit + 1)); 2130 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 2131 2132 aml_append(crs, 2133 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2134 AML_POS_DECODE, AML_ENTIRE_RANGE, 2135 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 2136 2137 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF); 2138 for (i = 0; i < io_ranges->len; i++) { 2139 entry = g_ptr_array_index(io_ranges, i); 2140 aml_append(crs, 2141 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 2142 AML_POS_DECODE, AML_ENTIRE_RANGE, 2143 0x0000, entry->base, entry->limit, 2144 0x0000, entry->limit - entry->base + 1)); 2145 } 2146 2147 aml_append(crs, 2148 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2149 AML_CACHEABLE, AML_READ_WRITE, 2150 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 2151 2152 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1); 2153 for (i = 0; i < mem_ranges->len; i++) { 2154 entry = g_ptr_array_index(mem_ranges, i); 2155 aml_append(crs, 2156 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2157 AML_NON_CACHEABLE, AML_READ_WRITE, 2158 0, entry->base, entry->limit, 2159 0, entry->limit - entry->base + 1)); 2160 } 2161 2162 if (pci->w64.begin) { 2163 aml_append(crs, 2164 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 2165 AML_CACHEABLE, AML_READ_WRITE, 2166 0, pci->w64.begin, pci->w64.end - 1, 0, 2167 pci->w64.end - pci->w64.begin)); 2168 } 2169 aml_append(scope, aml_name_decl("_CRS", crs)); 2170 2171 /* reserve GPE0 block resources */ 2172 dev = aml_device("GPE0"); 2173 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2174 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 2175 /* device present, functioning, decoding, not shown in UI */ 2176 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2177 crs = aml_resource_template(); 2178 aml_append(crs, 2179 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) 2180 ); 2181 aml_append(dev, aml_name_decl("_CRS", crs)); 2182 aml_append(scope, dev); 2183 2184 g_ptr_array_free(io_ranges, true); 2185 g_ptr_array_free(mem_ranges, true); 2186 2187 /* reserve PCIHP resources */ 2188 if (pm->pcihp_io_len) { 2189 dev = aml_device("PHPR"); 2190 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2191 aml_append(dev, 2192 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2193 /* device present, functioning, decoding, not shown in UI */ 2194 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2195 crs = aml_resource_template(); 2196 aml_append(crs, 2197 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2198 pm->pcihp_io_len) 2199 ); 2200 aml_append(dev, aml_name_decl("_CRS", crs)); 2201 aml_append(scope, dev); 2202 } 2203 aml_append(dsdt, scope); 2204 2205 /* create S3_ / S4_ / S5_ packages if necessary */ 2206 scope = aml_scope("\\"); 2207 if (!pm->s3_disabled) { 2208 pkg = aml_package(4); 2209 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2210 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2211 aml_append(pkg, aml_int(0)); /* reserved */ 2212 aml_append(pkg, aml_int(0)); /* reserved */ 2213 aml_append(scope, aml_name_decl("_S3", pkg)); 2214 } 2215 2216 if (!pm->s4_disabled) { 2217 pkg = aml_package(4); 2218 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2219 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2220 aml_append(pkg, aml_int(pm->s4_val)); 2221 aml_append(pkg, aml_int(0)); /* reserved */ 2222 aml_append(pkg, aml_int(0)); /* reserved */ 2223 aml_append(scope, aml_name_decl("_S4", pkg)); 2224 } 2225 2226 pkg = aml_package(4); 2227 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2228 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2229 aml_append(pkg, aml_int(0)); /* reserved */ 2230 aml_append(pkg, aml_int(0)); /* reserved */ 2231 aml_append(scope, aml_name_decl("_S5", pkg)); 2232 aml_append(dsdt, scope); 2233 2234 /* create fw_cfg node, unconditionally */ 2235 { 2236 /* when using port i/o, the 8-bit data register *always* overlaps 2237 * with half of the 16-bit control register. Hence, the total size 2238 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2239 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2240 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), 2241 "dma_enabled", NULL) ? 2242 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2243 FW_CFG_CTL_SIZE; 2244 2245 scope = aml_scope("\\_SB.PCI0"); 2246 dev = aml_device("FWCF"); 2247 2248 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2249 2250 /* device present, functioning, decoding, not shown in UI */ 2251 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2252 2253 crs = aml_resource_template(); 2254 aml_append(crs, 2255 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2256 ); 2257 aml_append(dev, aml_name_decl("_CRS", crs)); 2258 2259 aml_append(scope, dev); 2260 aml_append(dsdt, scope); 2261 } 2262 2263 if (misc->applesmc_io_base) { 2264 scope = aml_scope("\\_SB.PCI0.ISA"); 2265 dev = aml_device("SMC"); 2266 2267 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2268 /* device present, functioning, decoding, not shown in UI */ 2269 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2270 2271 crs = aml_resource_template(); 2272 aml_append(crs, 2273 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2274 0x01, APPLESMC_MAX_DATA_LENGTH) 2275 ); 2276 aml_append(crs, aml_irq_no_flags(6)); 2277 aml_append(dev, aml_name_decl("_CRS", crs)); 2278 2279 aml_append(scope, dev); 2280 aml_append(dsdt, scope); 2281 } 2282 2283 if (misc->pvpanic_port) { 2284 scope = aml_scope("\\_SB.PCI0.ISA"); 2285 2286 dev = aml_device("PEVT"); 2287 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2288 2289 crs = aml_resource_template(); 2290 aml_append(crs, 2291 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2292 ); 2293 aml_append(dev, aml_name_decl("_CRS", crs)); 2294 2295 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2296 aml_int(misc->pvpanic_port), 1)); 2297 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2298 aml_append(field, aml_named_field("PEPT", 8)); 2299 aml_append(dev, field); 2300 2301 /* device present, functioning, decoding, shown in UI */ 2302 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2303 2304 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2305 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2306 aml_append(method, aml_return(aml_local(0))); 2307 aml_append(dev, method); 2308 2309 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2310 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2311 aml_append(dev, method); 2312 2313 aml_append(scope, dev); 2314 aml_append(dsdt, scope); 2315 } 2316 2317 sb_scope = aml_scope("\\_SB"); 2318 { 2319 build_processor_devices(sb_scope, machine, pm); 2320 2321 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base, 2322 pm->mem_hp_io_len); 2323 2324 { 2325 Object *pci_host; 2326 PCIBus *bus = NULL; 2327 2328 pci_host = acpi_get_i386_pci_host(); 2329 if (pci_host) { 2330 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2331 } 2332 2333 if (bus) { 2334 Aml *scope = aml_scope("PCI0"); 2335 /* Scan all PCI buses. Generate tables to support hotplug. */ 2336 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2337 2338 if (misc->tpm_version != TPM_VERSION_UNSPEC) { 2339 dev = aml_device("ISA.TPM"); 2340 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31"))); 2341 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2342 crs = aml_resource_template(); 2343 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2344 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2345 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); 2346 aml_append(dev, aml_name_decl("_CRS", crs)); 2347 aml_append(scope, dev); 2348 } 2349 2350 aml_append(sb_scope, scope); 2351 } 2352 } 2353 aml_append(dsdt, sb_scope); 2354 } 2355 2356 /* copy AML table into ACPI tables blob and patch header there */ 2357 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2358 build_header(linker, table_data, 2359 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2360 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2361 free_aml_allocator(); 2362 } 2363 2364 static void 2365 build_hpet(GArray *table_data, GArray *linker) 2366 { 2367 Acpi20Hpet *hpet; 2368 2369 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2370 /* Note timer_block_id value must be kept in sync with value advertised by 2371 * emulated hpet 2372 */ 2373 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2374 hpet->addr.address = cpu_to_le64(HPET_BASE); 2375 build_header(linker, table_data, 2376 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2377 } 2378 2379 static void 2380 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog) 2381 { 2382 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2383 uint64_t log_area_start_address = acpi_data_len(tcpalog); 2384 2385 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2386 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2387 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address); 2388 2389 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1, 2390 false /* high memory */); 2391 2392 /* log area start address to be filled by Guest linker */ 2393 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2394 ACPI_BUILD_TPMLOG_FILE, 2395 table_data, &tcpa->log_area_start_address, 2396 sizeof(tcpa->log_area_start_address)); 2397 2398 build_header(linker, table_data, 2399 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2400 2401 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 2402 } 2403 2404 static void 2405 build_tpm2(GArray *table_data, GArray *linker) 2406 { 2407 Acpi20TPM2 *tpm2_ptr; 2408 2409 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2410 2411 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2412 tpm2_ptr->control_area_address = cpu_to_le64(0); 2413 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2414 2415 build_header(linker, table_data, 2416 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2417 } 2418 2419 typedef enum { 2420 MEM_AFFINITY_NOFLAGS = 0, 2421 MEM_AFFINITY_ENABLED = (1 << 0), 2422 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1), 2423 MEM_AFFINITY_NON_VOLATILE = (1 << 2), 2424 } MemoryAffinityFlags; 2425 2426 static void 2427 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, 2428 uint64_t len, int node, MemoryAffinityFlags flags) 2429 { 2430 numamem->type = ACPI_SRAT_MEMORY; 2431 numamem->length = sizeof(*numamem); 2432 memset(numamem->proximity, 0, 4); 2433 numamem->proximity[0] = node; 2434 numamem->flags = cpu_to_le32(flags); 2435 numamem->base_addr = cpu_to_le64(base); 2436 numamem->range_length = cpu_to_le64(len); 2437 } 2438 2439 static void 2440 build_srat(GArray *table_data, GArray *linker, MachineState *machine) 2441 { 2442 AcpiSystemResourceAffinityTable *srat; 2443 AcpiSratProcessorAffinity *core; 2444 AcpiSratMemoryAffinity *numamem; 2445 2446 int i; 2447 uint64_t curnode; 2448 int srat_start, numa_start, slots; 2449 uint64_t mem_len, mem_base, next_base; 2450 MachineClass *mc = MACHINE_GET_CLASS(machine); 2451 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2452 PCMachineState *pcms = PC_MACHINE(machine); 2453 ram_addr_t hotplugabble_address_space_size = 2454 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE, 2455 NULL); 2456 2457 srat_start = table_data->len; 2458 2459 srat = acpi_data_push(table_data, sizeof *srat); 2460 srat->reserved1 = cpu_to_le32(1); 2461 2462 for (i = 0; i < apic_ids->len; i++) { 2463 int apic_id = apic_ids->cpus[i].arch_id; 2464 2465 core = acpi_data_push(table_data, sizeof *core); 2466 core->type = ACPI_SRAT_PROCESSOR; 2467 core->length = sizeof(*core); 2468 core->local_apic_id = apic_id; 2469 curnode = pcms->node_cpu[apic_id]; 2470 core->proximity_lo = curnode; 2471 memset(core->proximity_hi, 0, 3); 2472 core->local_sapic_eid = 0; 2473 core->flags = cpu_to_le32(1); 2474 } 2475 2476 2477 /* the memory map is a bit tricky, it contains at least one hole 2478 * from 640k-1M and possibly another one from 3.5G-4G. 2479 */ 2480 next_base = 0; 2481 numa_start = table_data->len; 2482 2483 numamem = acpi_data_push(table_data, sizeof *numamem); 2484 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED); 2485 next_base = 1024 * 1024; 2486 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2487 mem_base = next_base; 2488 mem_len = pcms->node_mem[i - 1]; 2489 if (i == 1) { 2490 mem_len -= 1024 * 1024; 2491 } 2492 next_base = mem_base + mem_len; 2493 2494 /* Cut out the ACPI_PCI hole */ 2495 if (mem_base <= pcms->below_4g_mem_size && 2496 next_base > pcms->below_4g_mem_size) { 2497 mem_len -= next_base - pcms->below_4g_mem_size; 2498 if (mem_len > 0) { 2499 numamem = acpi_data_push(table_data, sizeof *numamem); 2500 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 2501 MEM_AFFINITY_ENABLED); 2502 } 2503 mem_base = 1ULL << 32; 2504 mem_len = next_base - pcms->below_4g_mem_size; 2505 next_base += (1ULL << 32) - pcms->below_4g_mem_size; 2506 } 2507 numamem = acpi_data_push(table_data, sizeof *numamem); 2508 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 2509 MEM_AFFINITY_ENABLED); 2510 } 2511 slots = (table_data->len - numa_start) / sizeof *numamem; 2512 for (; slots < pcms->numa_nodes + 2; slots++) { 2513 numamem = acpi_data_push(table_data, sizeof *numamem); 2514 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2515 } 2516 2517 /* 2518 * Entry is required for Windows to enable memory hotplug in OS. 2519 * Memory devices may override proximity set by this entry, 2520 * providing _PXM method if necessary. 2521 */ 2522 if (hotplugabble_address_space_size) { 2523 numamem = acpi_data_push(table_data, sizeof *numamem); 2524 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base, 2525 hotplugabble_address_space_size, 0, 2526 MEM_AFFINITY_HOTPLUGGABLE | 2527 MEM_AFFINITY_ENABLED); 2528 } 2529 2530 build_header(linker, table_data, 2531 (void *)(table_data->data + srat_start), 2532 "SRAT", 2533 table_data->len - srat_start, 1, NULL, NULL); 2534 g_free(apic_ids); 2535 } 2536 2537 static void 2538 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info) 2539 { 2540 AcpiTableMcfg *mcfg; 2541 const char *sig; 2542 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]); 2543 2544 mcfg = acpi_data_push(table_data, len); 2545 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base); 2546 /* Only a single allocation so no need to play with segments */ 2547 mcfg->allocation[0].pci_segment = cpu_to_le16(0); 2548 mcfg->allocation[0].start_bus_number = 0; 2549 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1); 2550 2551 /* MCFG is used for ECAM which can be enabled or disabled by guest. 2552 * To avoid table size changes (which create migration issues), 2553 * always create the table even if there are no allocations, 2554 * but set the signature to a reserved value in this case. 2555 * ACPI spec requires OSPMs to ignore such tables. 2556 */ 2557 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) { 2558 /* Reserved signature: ignored by OSPM */ 2559 sig = "QEMU"; 2560 } else { 2561 sig = "MCFG"; 2562 } 2563 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL); 2564 } 2565 2566 static void 2567 build_dmar_q35(GArray *table_data, GArray *linker) 2568 { 2569 int dmar_start = table_data->len; 2570 2571 AcpiTableDmar *dmar; 2572 AcpiDmarHardwareUnit *drhd; 2573 2574 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2575 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1; 2576 dmar->flags = 0; /* No intr_remap for now */ 2577 2578 /* DMAR Remapping Hardware Unit Definition structure */ 2579 drhd = acpi_data_push(table_data, sizeof(*drhd)); 2580 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2581 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ 2582 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2583 drhd->pci_segment = cpu_to_le16(0); 2584 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2585 2586 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2587 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2588 } 2589 2590 static GArray * 2591 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) 2592 { 2593 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp); 2594 2595 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16, 2596 true /* fseg memory */); 2597 2598 memcpy(&rsdp->signature, "RSD PTR ", 8); 2599 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6); 2600 rsdp->rsdt_physical_address = cpu_to_le32(rsdt); 2601 /* Address to be filled by Guest linker */ 2602 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE, 2603 ACPI_BUILD_TABLE_FILE, 2604 rsdp_table, &rsdp->rsdt_physical_address, 2605 sizeof rsdp->rsdt_physical_address); 2606 rsdp->checksum = 0; 2607 /* Checksum to be filled by Guest linker */ 2608 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE, 2609 rsdp_table, rsdp, sizeof *rsdp, 2610 &rsdp->checksum); 2611 2612 return rsdp_table; 2613 } 2614 2615 typedef 2616 struct AcpiBuildState { 2617 /* Copy of table in RAM (for patching). */ 2618 MemoryRegion *table_mr; 2619 /* Is table patched? */ 2620 uint8_t patched; 2621 void *rsdp; 2622 MemoryRegion *rsdp_mr; 2623 MemoryRegion *linker_mr; 2624 } AcpiBuildState; 2625 2626 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2627 { 2628 Object *pci_host; 2629 QObject *o; 2630 2631 pci_host = acpi_get_i386_pci_host(); 2632 g_assert(pci_host); 2633 2634 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2635 if (!o) { 2636 return false; 2637 } 2638 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o)); 2639 qobject_decref(o); 2640 2641 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2642 assert(o); 2643 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o)); 2644 qobject_decref(o); 2645 return true; 2646 } 2647 2648 static bool acpi_has_iommu(void) 2649 { 2650 bool ambiguous; 2651 Object *intel_iommu; 2652 2653 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 2654 &ambiguous); 2655 return intel_iommu && !ambiguous; 2656 } 2657 2658 static 2659 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2660 { 2661 PCMachineState *pcms = PC_MACHINE(machine); 2662 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2663 GArray *table_offsets; 2664 unsigned facs, dsdt, rsdt, fadt; 2665 AcpiPmInfo pm; 2666 AcpiMiscInfo misc; 2667 AcpiMcfgInfo mcfg; 2668 PcPciInfo pci; 2669 uint8_t *u; 2670 size_t aml_len = 0; 2671 GArray *tables_blob = tables->table_data; 2672 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2673 2674 acpi_get_pm_info(&pm); 2675 acpi_get_misc_info(&misc); 2676 acpi_get_pci_info(&pci); 2677 acpi_get_slic_oem(&slic_oem); 2678 2679 table_offsets = g_array_new(false, true /* clear */, 2680 sizeof(uint32_t)); 2681 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2682 2683 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE, 2684 64 /* Ensure FACS is aligned */, 2685 false /* high memory */); 2686 2687 /* 2688 * FACS is pointed to by FADT. 2689 * We place it first since it's the only table that has alignment 2690 * requirements. 2691 */ 2692 facs = tables_blob->len; 2693 build_facs(tables_blob, tables->linker); 2694 2695 /* DSDT is pointed to by FADT */ 2696 dsdt = tables_blob->len; 2697 build_dsdt(tables_blob, tables->linker, &pm, &misc, &pci, machine); 2698 2699 /* Count the size of the DSDT and SSDT, we will need it for legacy 2700 * sizing of ACPI tables. 2701 */ 2702 aml_len += tables_blob->len - dsdt; 2703 2704 /* ACPI tables pointed to by RSDT */ 2705 fadt = tables_blob->len; 2706 acpi_add_table(table_offsets, tables_blob); 2707 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt, 2708 slic_oem.id, slic_oem.table_id); 2709 aml_len += tables_blob->len - fadt; 2710 2711 acpi_add_table(table_offsets, tables_blob); 2712 build_madt(tables_blob, tables->linker, pcms); 2713 2714 if (misc.has_hpet) { 2715 acpi_add_table(table_offsets, tables_blob); 2716 build_hpet(tables_blob, tables->linker); 2717 } 2718 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2719 acpi_add_table(table_offsets, tables_blob); 2720 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2721 2722 if (misc.tpm_version == TPM_VERSION_2_0) { 2723 acpi_add_table(table_offsets, tables_blob); 2724 build_tpm2(tables_blob, tables->linker); 2725 } 2726 } 2727 if (pcms->numa_nodes) { 2728 acpi_add_table(table_offsets, tables_blob); 2729 build_srat(tables_blob, tables->linker, machine); 2730 } 2731 if (acpi_get_mcfg(&mcfg)) { 2732 acpi_add_table(table_offsets, tables_blob); 2733 build_mcfg_q35(tables_blob, tables->linker, &mcfg); 2734 } 2735 if (acpi_has_iommu()) { 2736 acpi_add_table(table_offsets, tables_blob); 2737 build_dmar_q35(tables_blob, tables->linker); 2738 } 2739 if (pcms->acpi_nvdimm_state.is_enabled) { 2740 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker); 2741 } 2742 2743 /* Add tables supplied by user (if any) */ 2744 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2745 unsigned len = acpi_table_len(u); 2746 2747 acpi_add_table(table_offsets, tables_blob); 2748 g_array_append_vals(tables_blob, u, len); 2749 } 2750 2751 /* RSDT is pointed to by RSDP */ 2752 rsdt = tables_blob->len; 2753 build_rsdt(tables_blob, tables->linker, table_offsets, 2754 slic_oem.id, slic_oem.table_id); 2755 2756 /* RSDP is in FSEG memory, so allocate it separately */ 2757 build_rsdp(tables->rsdp, tables->linker, rsdt); 2758 2759 /* We'll expose it all to Guest so we want to reduce 2760 * chance of size changes. 2761 * 2762 * We used to align the tables to 4k, but of course this would 2763 * too simple to be enough. 4k turned out to be too small an 2764 * alignment very soon, and in fact it is almost impossible to 2765 * keep the table size stable for all (max_cpus, max_memory_slots) 2766 * combinations. So the table size is always 64k for pc-i440fx-2.1 2767 * and we give an error if the table grows beyond that limit. 2768 * 2769 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2770 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2771 * than 2.0 and we can always pad the smaller tables with zeros. We can 2772 * then use the exact size of the 2.0 tables. 2773 * 2774 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2775 */ 2776 if (pcmc->legacy_acpi_table_size) { 2777 /* Subtracting aml_len gives the size of fixed tables. Then add the 2778 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2779 */ 2780 int legacy_aml_len = 2781 pcmc->legacy_acpi_table_size + 2782 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus; 2783 int legacy_table_size = 2784 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2785 ACPI_BUILD_ALIGN_SIZE); 2786 if (tables_blob->len > legacy_table_size) { 2787 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2788 error_report("Warning: migration may not work."); 2789 } 2790 g_array_set_size(tables_blob, legacy_table_size); 2791 } else { 2792 /* Make sure we have a buffer in case we need to resize the tables. */ 2793 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2794 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2795 error_report("Warning: ACPI tables are larger than 64k."); 2796 error_report("Warning: migration may not work."); 2797 error_report("Warning: please remove CPUs, NUMA nodes, " 2798 "memory slots or PCI bridges."); 2799 } 2800 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2801 } 2802 2803 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE); 2804 2805 /* Cleanup memory that's no longer used. */ 2806 g_array_free(table_offsets, true); 2807 } 2808 2809 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2810 { 2811 uint32_t size = acpi_data_len(data); 2812 2813 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2814 memory_region_ram_resize(mr, size, &error_abort); 2815 2816 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2817 memory_region_set_dirty(mr, 0, size); 2818 } 2819 2820 static void acpi_build_update(void *build_opaque) 2821 { 2822 AcpiBuildState *build_state = build_opaque; 2823 AcpiBuildTables tables; 2824 2825 /* No state to update or already patched? Nothing to do. */ 2826 if (!build_state || build_state->patched) { 2827 return; 2828 } 2829 build_state->patched = 1; 2830 2831 acpi_build_tables_init(&tables); 2832 2833 acpi_build(&tables, MACHINE(qdev_get_machine())); 2834 2835 acpi_ram_update(build_state->table_mr, tables.table_data); 2836 2837 if (build_state->rsdp) { 2838 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2839 } else { 2840 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2841 } 2842 2843 acpi_ram_update(build_state->linker_mr, tables.linker); 2844 acpi_build_tables_cleanup(&tables, true); 2845 } 2846 2847 static void acpi_build_reset(void *build_opaque) 2848 { 2849 AcpiBuildState *build_state = build_opaque; 2850 build_state->patched = 0; 2851 } 2852 2853 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 2854 GArray *blob, const char *name, 2855 uint64_t max_size) 2856 { 2857 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 2858 name, acpi_build_update, build_state); 2859 } 2860 2861 static const VMStateDescription vmstate_acpi_build = { 2862 .name = "acpi_build", 2863 .version_id = 1, 2864 .minimum_version_id = 1, 2865 .fields = (VMStateField[]) { 2866 VMSTATE_UINT8(patched, AcpiBuildState), 2867 VMSTATE_END_OF_LIST() 2868 }, 2869 }; 2870 2871 void acpi_setup(void) 2872 { 2873 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2874 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2875 AcpiBuildTables tables; 2876 AcpiBuildState *build_state; 2877 2878 if (!pcms->fw_cfg) { 2879 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2880 return; 2881 } 2882 2883 if (!pcmc->has_acpi_build) { 2884 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2885 return; 2886 } 2887 2888 if (!acpi_enabled) { 2889 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2890 return; 2891 } 2892 2893 build_state = g_malloc0(sizeof *build_state); 2894 2895 acpi_set_pci_info(); 2896 2897 acpi_build_tables_init(&tables); 2898 acpi_build(&tables, MACHINE(pcms)); 2899 2900 /* Now expose it all to Guest */ 2901 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 2902 ACPI_BUILD_TABLE_FILE, 2903 ACPI_BUILD_TABLE_MAX_SIZE); 2904 assert(build_state->table_mr != NULL); 2905 2906 build_state->linker_mr = 2907 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0); 2908 2909 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2910 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2911 2912 if (!pcmc->rsdp_in_ram) { 2913 /* 2914 * Keep for compatibility with old machine types. 2915 * Though RSDP is small, its contents isn't immutable, so 2916 * we'll update it along with the rest of tables on guest access. 2917 */ 2918 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2919 2920 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2921 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2922 acpi_build_update, build_state, 2923 build_state->rsdp, rsdp_size); 2924 build_state->rsdp_mr = NULL; 2925 } else { 2926 build_state->rsdp = NULL; 2927 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 2928 ACPI_BUILD_RSDP_FILE, 0); 2929 } 2930 2931 qemu_register_reset(acpi_build_reset, build_state); 2932 acpi_build_reset(build_state); 2933 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2934 2935 /* Cleanup tables but don't free the memory: we track it 2936 * in build_state. 2937 */ 2938 acpi_build_tables_cleanup(&tables, false); 2939 } 2940