1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/rtc/mc146818rtc_regs.h" 49 #include "migration/vmstate.h" 50 #include "hw/mem/memory-device.h" 51 #include "hw/mem/nvdimm.h" 52 #include "sysemu/numa.h" 53 #include "sysemu/reset.h" 54 #include "hw/hyperv/vmbus-bridge.h" 55 56 /* Supported chipsets: */ 57 #include "hw/southbridge/piix.h" 58 #include "hw/acpi/pcihp.h" 59 #include "hw/i386/fw_cfg.h" 60 #include "hw/i386/ich9.h" 61 #include "hw/pci/pci_bus.h" 62 #include "hw/pci-host/q35.h" 63 #include "hw/i386/x86-iommu.h" 64 65 #include "hw/acpi/aml-build.h" 66 #include "hw/acpi/utils.h" 67 #include "hw/acpi/pci.h" 68 #include "hw/acpi/cxl.h" 69 70 #include "qom/qom-qobject.h" 71 #include "hw/i386/amd_iommu.h" 72 #include "hw/i386/intel_iommu.h" 73 #include "hw/virtio/virtio-iommu.h" 74 75 #include "hw/acpi/hmat.h" 76 #include "hw/acpi/viot.h" 77 #include "hw/acpi/cxl.h" 78 79 #include CONFIG_DEVICES 80 81 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 82 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 83 * a little bit, there should be plenty of free space since the DSDT 84 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 85 */ 86 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 87 #define ACPI_BUILD_ALIGN_SIZE 0x1000 88 89 #define ACPI_BUILD_TABLE_SIZE 0x20000 90 91 /* #define DEBUG_ACPI_BUILD */ 92 #ifdef DEBUG_ACPI_BUILD 93 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 94 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 95 #else 96 #define ACPI_BUILD_DPRINTF(fmt, ...) 97 #endif 98 99 typedef struct AcpiPmInfo { 100 bool s3_disabled; 101 bool s4_disabled; 102 bool pcihp_bridge_en; 103 bool smi_on_cpuhp; 104 bool smi_on_cpu_unplug; 105 bool pcihp_root_en; 106 uint8_t s4_val; 107 AcpiFadtData fadt; 108 uint16_t cpu_hp_io_base; 109 uint16_t pcihp_io_base; 110 uint16_t pcihp_io_len; 111 } AcpiPmInfo; 112 113 typedef struct AcpiMiscInfo { 114 bool is_piix4; 115 bool has_hpet; 116 #ifdef CONFIG_TPM 117 TPMVersion tpm_version; 118 #endif 119 const unsigned char *dsdt_code; 120 unsigned dsdt_size; 121 } AcpiMiscInfo; 122 123 typedef struct AcpiBuildPciBusHotplugState { 124 GArray *device_table; 125 GArray *notify_table; 126 struct AcpiBuildPciBusHotplugState *parent; 127 bool pcihp_bridge_en; 128 } AcpiBuildPciBusHotplugState; 129 130 typedef struct FwCfgTPMConfig { 131 uint32_t tpmppi_address; 132 uint8_t tpm_version; 133 uint8_t tpmppi_version; 134 } QEMU_PACKED FwCfgTPMConfig; 135 136 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 137 138 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 139 .space_id = AML_AS_SYSTEM_IO, 140 .address = NVDIMM_ACPI_IO_BASE, 141 .bit_width = NVDIMM_ACPI_IO_LEN << 3 142 }; 143 144 static void init_common_fadt_data(MachineState *ms, Object *o, 145 AcpiFadtData *data) 146 { 147 X86MachineState *x86ms = X86_MACHINE(ms); 148 /* 149 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 150 * behavior for compatibility irrelevant to smm_enabled, which doesn't 151 * comforms to ACPI spec. 152 */ 153 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 154 true : x86_machine_is_smm_enabled(x86ms); 155 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 156 AmlAddressSpace as = AML_AS_SYSTEM_IO; 157 AcpiFadtData fadt = { 158 .rev = 3, 159 .flags = 160 (1 << ACPI_FADT_F_WBINVD) | 161 (1 << ACPI_FADT_F_PROC_C1) | 162 (1 << ACPI_FADT_F_SLP_BUTTON) | 163 (1 << ACPI_FADT_F_RTC_S4) | 164 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 165 /* APIC destination mode ("Flat Logical") has an upper limit of 8 166 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 167 * used 168 */ 169 ((ms->smp.max_cpus > 8) ? 170 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 171 .int_model = 1 /* Multiple APIC */, 172 .rtc_century = RTC_CENTURY, 173 .plvl2_lat = 0xfff /* C2 state not supported */, 174 .plvl3_lat = 0xfff /* C3 state not supported */, 175 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 176 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 177 .acpi_enable_cmd = 178 smm_enabled ? 179 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 180 0, 181 .acpi_disable_cmd = 182 smm_enabled ? 183 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 184 0, 185 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 186 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 187 .address = io + 0x04 }, 188 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 189 .gpe0_blk = { .space_id = as, .bit_width = 190 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 191 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 192 }, 193 }; 194 195 /* 196 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 197 * Flags, bit offset 1 - 8042. 198 */ 199 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 200 201 *data = fadt; 202 } 203 204 static Object *object_resolve_type_unambiguous(const char *typename) 205 { 206 bool ambig; 207 Object *o = object_resolve_path_type("", typename, &ambig); 208 209 if (ambig || !o) { 210 return NULL; 211 } 212 return o; 213 } 214 215 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 216 { 217 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 218 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 219 Object *obj = piix ? piix : lpc; 220 QObject *o; 221 pm->cpu_hp_io_base = 0; 222 pm->pcihp_io_base = 0; 223 pm->pcihp_io_len = 0; 224 pm->smi_on_cpuhp = false; 225 pm->smi_on_cpu_unplug = false; 226 227 assert(obj); 228 init_common_fadt_data(machine, obj, &pm->fadt); 229 if (piix) { 230 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 231 pm->fadt.rev = 1; 232 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 233 } 234 if (lpc) { 235 uint64_t smi_features = object_property_get_uint(lpc, 236 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 237 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 238 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 239 pm->fadt.reset_reg = r; 240 pm->fadt.reset_val = 0xf; 241 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 242 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 243 pm->smi_on_cpuhp = 244 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 245 pm->smi_on_cpu_unplug = 246 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 247 } 248 pm->pcihp_io_base = 249 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 250 pm->pcihp_io_len = 251 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 252 253 /* The above need not be conditional on machine type because the reset port 254 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 255 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 256 257 /* Fill in optional s3/s4 related properties */ 258 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 259 if (o) { 260 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 261 } else { 262 pm->s3_disabled = false; 263 } 264 qobject_unref(o); 265 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 266 if (o) { 267 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 268 } else { 269 pm->s4_disabled = false; 270 } 271 qobject_unref(o); 272 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 273 if (o) { 274 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 275 } else { 276 pm->s4_val = false; 277 } 278 qobject_unref(o); 279 280 pm->pcihp_bridge_en = 281 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 282 NULL); 283 pm->pcihp_root_en = 284 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 285 NULL); 286 } 287 288 static void acpi_get_misc_info(AcpiMiscInfo *info) 289 { 290 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 291 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 292 assert(!!piix != !!lpc); 293 294 if (piix) { 295 info->is_piix4 = true; 296 } 297 if (lpc) { 298 info->is_piix4 = false; 299 } 300 301 info->has_hpet = hpet_find(); 302 #ifdef CONFIG_TPM 303 info->tpm_version = tpm_get_version(tpm_find()); 304 #endif 305 } 306 307 /* 308 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 309 * On i386 arch we only have two pci hosts, so we can look only for them. 310 */ 311 Object *acpi_get_i386_pci_host(void) 312 { 313 PCIHostState *host; 314 315 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 316 if (!host) { 317 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 318 } 319 320 return OBJECT(host); 321 } 322 323 static void acpi_get_pci_holes(Range *hole, Range *hole64) 324 { 325 Object *pci_host; 326 327 pci_host = acpi_get_i386_pci_host(); 328 329 if (!pci_host) { 330 return; 331 } 332 333 range_set_bounds1(hole, 334 object_property_get_uint(pci_host, 335 PCI_HOST_PROP_PCI_HOLE_START, 336 NULL), 337 object_property_get_uint(pci_host, 338 PCI_HOST_PROP_PCI_HOLE_END, 339 NULL)); 340 range_set_bounds1(hole64, 341 object_property_get_uint(pci_host, 342 PCI_HOST_PROP_PCI_HOLE64_START, 343 NULL), 344 object_property_get_uint(pci_host, 345 PCI_HOST_PROP_PCI_HOLE64_END, 346 NULL)); 347 } 348 349 static void acpi_align_size(GArray *blob, unsigned align) 350 { 351 /* Align size to multiple of given size. This reduces the chance 352 * we need to change size in the future (breaking cross version migration). 353 */ 354 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 355 } 356 357 /* 358 * ACPI spec 1.0b, 359 * 5.2.6 Firmware ACPI Control Structure 360 */ 361 static void 362 build_facs(GArray *table_data) 363 { 364 const char *sig = "FACS"; 365 const uint8_t reserved[40] = {}; 366 367 g_array_append_vals(table_data, sig, 4); /* Signature */ 368 build_append_int_noprefix(table_data, 64, 4); /* Length */ 369 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 370 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 371 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 372 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 373 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 374 } 375 376 static void build_append_pcihp_notify_entry(Aml *method, int slot) 377 { 378 Aml *if_ctx; 379 int32_t devfn = PCI_DEVFN(slot, 0); 380 381 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 382 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 383 aml_append(method, if_ctx); 384 } 385 386 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 387 bool pcihp_bridge_en) 388 { 389 Aml *dev, *notify_method = NULL, *method; 390 QObject *bsel; 391 PCIBus *sec; 392 int devfn; 393 394 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 395 if (bsel) { 396 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 397 398 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 399 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 400 } 401 402 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 403 DeviceClass *dc; 404 PCIDeviceClass *pc; 405 PCIDevice *pdev = bus->devices[devfn]; 406 int slot = PCI_SLOT(devfn); 407 int func = PCI_FUNC(devfn); 408 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 409 int adr = slot << 16 | func; 410 bool hotplug_enabled_dev; 411 bool bridge_in_acpi; 412 bool cold_plugged_bridge; 413 414 if (!pdev) { 415 /* 416 * add hotplug slots for non present devices. 417 * hotplug is supported only for non-multifunction device 418 * so generate device description only for function 0 419 */ 420 if (bsel && !func) { 421 if (pci_bus_is_express(bus) && slot > 0) { 422 break; 423 } 424 dev = aml_device("S%.02X", devfn); 425 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 426 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 427 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 428 aml_append(method, 429 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 430 ); 431 aml_append(dev, method); 432 method = aml_method("_DSM", 4, AML_SERIALIZED); 433 aml_append(method, 434 aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1), 435 aml_arg(2), aml_arg(3), 436 aml_name("BSEL"), aml_name("_SUN"))) 437 ); 438 aml_append(dev, method); 439 aml_append(parent_scope, dev); 440 441 build_append_pcihp_notify_entry(notify_method, slot); 442 } 443 continue; 444 } 445 446 pc = PCI_DEVICE_GET_CLASS(pdev); 447 dc = DEVICE_GET_CLASS(pdev); 448 449 /* 450 * Cold plugged bridges aren't themselves hot-pluggable. 451 * Hotplugged bridges *are* hot-pluggable. 452 */ 453 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 454 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 455 456 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 457 458 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 459 continue; 460 } 461 462 /* 463 * allow describing coldplugged bridges in ACPI even if they are not 464 * on function 0, as they are not unpluggable, for all other devices 465 * generate description only for function 0 per slot 466 */ 467 if (func && !bridge_in_acpi) { 468 continue; 469 } 470 471 /* start to compose PCI device descriptor */ 472 dev = aml_device("S%.02X", devfn); 473 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 474 475 if (bsel) { 476 /* 477 * Can't declare _SUN here for every device as it changes 'slot' 478 * enumeration order in linux kernel, so use another variable for it 479 */ 480 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 481 method = aml_method("_DSM", 4, AML_SERIALIZED); 482 aml_append(method, aml_return( 483 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2), 484 aml_arg(3), aml_name("BSEL"), aml_name("ASUN")) 485 )); 486 aml_append(dev, method); 487 } 488 489 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 490 /* add VGA specific AML methods */ 491 int s3d; 492 493 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 494 s3d = 3; 495 } else { 496 s3d = 0; 497 } 498 499 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 500 aml_append(method, aml_return(aml_int(0))); 501 aml_append(dev, method); 502 503 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 504 aml_append(method, aml_return(aml_int(0))); 505 aml_append(dev, method); 506 507 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 508 aml_append(method, aml_return(aml_int(s3d))); 509 aml_append(dev, method); 510 } else if (hotplug_enabled_dev) { 511 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 512 /* add _EJ0 to make slot hotpluggable */ 513 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 514 aml_append(method, 515 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 516 ); 517 aml_append(dev, method); 518 519 if (bsel) { 520 build_append_pcihp_notify_entry(notify_method, slot); 521 } 522 } else if (bridge_in_acpi) { 523 /* 524 * device is coldplugged bridge, 525 * add child device descriptions into its scope 526 */ 527 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 528 529 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 530 } 531 /* device descriptor has been composed, add it into parent context */ 532 aml_append(parent_scope, dev); 533 } 534 535 if (bsel) { 536 aml_append(parent_scope, notify_method); 537 } 538 539 /* Append PCNT method to notify about events on local and child buses. 540 * Add this method for root bus only when hotplug is enabled since DSDT 541 * expects it. 542 */ 543 if (bsel || pcihp_bridge_en) { 544 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 545 546 /* If bus supports hotplug select it and notify about local events */ 547 if (bsel) { 548 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 549 550 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 551 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 552 aml_int(1))); /* Device Check */ 553 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 554 aml_int(3))); /* Eject Request */ 555 } 556 557 /* Notify about child bus events in any case */ 558 if (pcihp_bridge_en) { 559 QLIST_FOREACH(sec, &bus->child, sibling) { 560 if (pci_bus_is_root(sec)) { 561 continue; 562 } 563 564 aml_append(method, aml_name("^S%.02X.PCNT", 565 sec->parent_dev->devfn)); 566 } 567 } 568 569 aml_append(parent_scope, method); 570 } 571 qobject_unref(bsel); 572 } 573 574 Aml *aml_pci_device_dsm(void) 575 { 576 Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx; 577 Aml *acpi_index = aml_local(0); 578 Aml *zero = aml_int(0); 579 Aml *bnum = aml_arg(4); 580 Aml *func = aml_arg(2); 581 Aml *rev = aml_arg(1); 582 Aml *sunum = aml_arg(5); 583 584 method = aml_method("PDSM", 6, AML_SERIALIZED); 585 586 /* 587 * PCI Firmware Specification 3.1 588 * 4.6. _DSM Definitions for PCI 589 */ 590 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 591 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 592 { 593 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 594 ifctx1 = aml_if(aml_equal(func, zero)); 595 { 596 uint8_t byte_list[1]; 597 598 ifctx2 = aml_if(aml_equal(rev, aml_int(2))); 599 { 600 /* 601 * advertise function 7 if device has acpi-index 602 * acpi_index values: 603 * 0: not present (default value) 604 * FFFFFFFF: not supported (old QEMU without PIDX reg) 605 * other: device's acpi-index 606 */ 607 ifctx3 = aml_if(aml_lnot( 608 aml_or(aml_equal(acpi_index, zero), 609 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 610 )); 611 { 612 byte_list[0] = 613 1 /* have supported functions */ | 614 1 << 7 /* support for function 7 */ 615 ; 616 aml_append(ifctx3, aml_return(aml_buffer(1, byte_list))); 617 } 618 aml_append(ifctx2, ifctx3); 619 } 620 aml_append(ifctx1, ifctx2); 621 622 byte_list[0] = 0; /* nothing supported */ 623 aml_append(ifctx1, aml_return(aml_buffer(1, byte_list))); 624 } 625 aml_append(ifctx, ifctx1); 626 elsectx = aml_else(); 627 /* 628 * PCI Firmware Specification 3.1 629 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 630 * Operating Systems 631 */ 632 ifctx1 = aml_if(aml_equal(func, aml_int(7))); 633 { 634 Aml *pkg = aml_package(2); 635 Aml *ret = aml_local(1); 636 637 aml_append(pkg, zero); 638 /* 639 * optional, if not impl. should return null string 640 */ 641 aml_append(pkg, aml_string("%s", "")); 642 aml_append(ifctx1, aml_store(pkg, ret)); 643 /* 644 * update acpi-index to actual value 645 */ 646 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); 647 aml_append(ifctx1, aml_return(ret)); 648 } 649 aml_append(elsectx, ifctx1); 650 aml_append(ifctx, elsectx); 651 } 652 aml_append(method, ifctx); 653 return method; 654 } 655 656 /** 657 * build_prt_entry: 658 * @link_name: link name for PCI route entry 659 * 660 * build AML package containing a PCI route entry for @link_name 661 */ 662 static Aml *build_prt_entry(const char *link_name) 663 { 664 Aml *a_zero = aml_int(0); 665 Aml *pkg = aml_package(4); 666 aml_append(pkg, a_zero); 667 aml_append(pkg, a_zero); 668 aml_append(pkg, aml_name("%s", link_name)); 669 aml_append(pkg, a_zero); 670 return pkg; 671 } 672 673 /* 674 * initialize_route - Initialize the interrupt routing rule 675 * through a specific LINK: 676 * if (lnk_idx == idx) 677 * route using link 'link_name' 678 */ 679 static Aml *initialize_route(Aml *route, const char *link_name, 680 Aml *lnk_idx, int idx) 681 { 682 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 683 Aml *pkg = build_prt_entry(link_name); 684 685 aml_append(if_ctx, aml_store(pkg, route)); 686 687 return if_ctx; 688 } 689 690 /* 691 * build_prt - Define interrupt rounting rules 692 * 693 * Returns an array of 128 routes, one for each device, 694 * based on device location. 695 * The main goal is to equaly distribute the interrupts 696 * over the 4 existing ACPI links (works only for i440fx). 697 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 698 * 699 */ 700 static Aml *build_prt(bool is_pci0_prt) 701 { 702 Aml *method, *while_ctx, *pin, *res; 703 704 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 705 res = aml_local(0); 706 pin = aml_local(1); 707 aml_append(method, aml_store(aml_package(128), res)); 708 aml_append(method, aml_store(aml_int(0), pin)); 709 710 /* while (pin < 128) */ 711 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 712 { 713 Aml *slot = aml_local(2); 714 Aml *lnk_idx = aml_local(3); 715 Aml *route = aml_local(4); 716 717 /* slot = pin >> 2 */ 718 aml_append(while_ctx, 719 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 720 /* lnk_idx = (slot + pin) & 3 */ 721 aml_append(while_ctx, 722 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 723 lnk_idx)); 724 725 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 726 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 727 if (is_pci0_prt) { 728 Aml *if_device_1, *if_pin_4, *else_pin_4; 729 730 /* device 1 is the power-management device, needs SCI */ 731 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 732 { 733 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 734 { 735 aml_append(if_pin_4, 736 aml_store(build_prt_entry("LNKS"), route)); 737 } 738 aml_append(if_device_1, if_pin_4); 739 else_pin_4 = aml_else(); 740 { 741 aml_append(else_pin_4, 742 aml_store(build_prt_entry("LNKA"), route)); 743 } 744 aml_append(if_device_1, else_pin_4); 745 } 746 aml_append(while_ctx, if_device_1); 747 } else { 748 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 749 } 750 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 751 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 752 753 /* route[0] = 0x[slot]FFFF */ 754 aml_append(while_ctx, 755 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 756 NULL), 757 aml_index(route, aml_int(0)))); 758 /* route[1] = pin & 3 */ 759 aml_append(while_ctx, 760 aml_store(aml_and(pin, aml_int(3), NULL), 761 aml_index(route, aml_int(1)))); 762 /* res[pin] = route */ 763 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 764 /* pin++ */ 765 aml_append(while_ctx, aml_increment(pin)); 766 } 767 aml_append(method, while_ctx); 768 /* return res*/ 769 aml_append(method, aml_return(res)); 770 771 return method; 772 } 773 774 static void build_hpet_aml(Aml *table) 775 { 776 Aml *crs; 777 Aml *field; 778 Aml *method; 779 Aml *if_ctx; 780 Aml *scope = aml_scope("_SB"); 781 Aml *dev = aml_device("HPET"); 782 Aml *zero = aml_int(0); 783 Aml *id = aml_local(0); 784 Aml *period = aml_local(1); 785 786 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 787 aml_append(dev, aml_name_decl("_UID", zero)); 788 789 aml_append(dev, 790 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 791 HPET_LEN)); 792 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 793 aml_append(field, aml_named_field("VEND", 32)); 794 aml_append(field, aml_named_field("PRD", 32)); 795 aml_append(dev, field); 796 797 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 798 aml_append(method, aml_store(aml_name("VEND"), id)); 799 aml_append(method, aml_store(aml_name("PRD"), period)); 800 aml_append(method, aml_shiftright(id, aml_int(16), id)); 801 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 802 aml_equal(id, aml_int(0xffff)))); 803 { 804 aml_append(if_ctx, aml_return(zero)); 805 } 806 aml_append(method, if_ctx); 807 808 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 809 aml_lgreater(period, aml_int(100000000)))); 810 { 811 aml_append(if_ctx, aml_return(zero)); 812 } 813 aml_append(method, if_ctx); 814 815 aml_append(method, aml_return(aml_int(0x0F))); 816 aml_append(dev, method); 817 818 crs = aml_resource_template(); 819 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 820 aml_append(dev, aml_name_decl("_CRS", crs)); 821 822 aml_append(scope, dev); 823 aml_append(table, scope); 824 } 825 826 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 827 { 828 Aml *dev; 829 Aml *method; 830 Aml *crs; 831 832 dev = aml_device("VMBS"); 833 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 834 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 835 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 836 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 837 838 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 839 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 840 aml_name("STA"))); 841 aml_append(dev, method); 842 843 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 844 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 845 aml_name("STA"))); 846 aml_append(dev, method); 847 848 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 849 aml_append(method, aml_return(aml_name("STA"))); 850 aml_append(dev, method); 851 852 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 853 854 crs = aml_resource_template(); 855 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 856 aml_append(dev, aml_name_decl("_CRS", crs)); 857 858 return dev; 859 } 860 861 static void build_dbg_aml(Aml *table) 862 { 863 Aml *field; 864 Aml *method; 865 Aml *while_ctx; 866 Aml *scope = aml_scope("\\"); 867 Aml *buf = aml_local(0); 868 Aml *len = aml_local(1); 869 Aml *idx = aml_local(2); 870 871 aml_append(scope, 872 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 873 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 874 aml_append(field, aml_named_field("DBGB", 8)); 875 aml_append(scope, field); 876 877 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 878 879 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 880 aml_append(method, aml_to_buffer(buf, buf)); 881 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 882 aml_append(method, aml_store(aml_int(0), idx)); 883 884 while_ctx = aml_while(aml_lless(idx, len)); 885 aml_append(while_ctx, 886 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 887 aml_append(while_ctx, aml_increment(idx)); 888 aml_append(method, while_ctx); 889 890 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 891 aml_append(scope, method); 892 893 aml_append(table, scope); 894 } 895 896 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 897 { 898 Aml *dev; 899 Aml *crs; 900 Aml *method; 901 uint32_t irqs[] = {5, 10, 11}; 902 903 dev = aml_device("%s", name); 904 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 905 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 906 907 crs = aml_resource_template(); 908 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 909 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 910 aml_append(dev, aml_name_decl("_PRS", crs)); 911 912 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 913 aml_append(method, aml_return(aml_call1("IQST", reg))); 914 aml_append(dev, method); 915 916 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 917 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 918 aml_append(dev, method); 919 920 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 921 aml_append(method, aml_return(aml_call1("IQCR", reg))); 922 aml_append(dev, method); 923 924 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 925 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 926 aml_append(method, aml_store(aml_name("PRRI"), reg)); 927 aml_append(dev, method); 928 929 return dev; 930 } 931 932 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 933 { 934 Aml *dev; 935 Aml *crs; 936 Aml *method; 937 uint32_t irqs; 938 939 dev = aml_device("%s", name); 940 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 941 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 942 943 crs = aml_resource_template(); 944 irqs = gsi; 945 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 946 AML_SHARED, &irqs, 1)); 947 aml_append(dev, aml_name_decl("_PRS", crs)); 948 949 aml_append(dev, aml_name_decl("_CRS", crs)); 950 951 /* 952 * _DIS can be no-op because the interrupt cannot be disabled. 953 */ 954 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 955 aml_append(dev, method); 956 957 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 958 aml_append(dev, method); 959 960 return dev; 961 } 962 963 /* _CRS method - get current settings */ 964 static Aml *build_iqcr_method(bool is_piix4) 965 { 966 Aml *if_ctx; 967 uint32_t irqs; 968 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 969 Aml *crs = aml_resource_template(); 970 971 irqs = 0; 972 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 973 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 974 aml_append(method, aml_name_decl("PRR0", crs)); 975 976 aml_append(method, 977 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 978 979 if (is_piix4) { 980 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 981 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 982 aml_append(method, if_ctx); 983 } else { 984 aml_append(method, 985 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 986 aml_name("PRRI"))); 987 } 988 989 aml_append(method, aml_return(aml_name("PRR0"))); 990 return method; 991 } 992 993 /* _STA method - get status */ 994 static Aml *build_irq_status_method(void) 995 { 996 Aml *if_ctx; 997 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 998 999 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1000 aml_append(if_ctx, aml_return(aml_int(0x09))); 1001 aml_append(method, if_ctx); 1002 aml_append(method, aml_return(aml_int(0x0B))); 1003 return method; 1004 } 1005 1006 static void build_piix4_pci0_int(Aml *table) 1007 { 1008 Aml *dev; 1009 Aml *crs; 1010 Aml *field; 1011 Aml *method; 1012 uint32_t irqs; 1013 Aml *sb_scope = aml_scope("_SB"); 1014 Aml *pci0_scope = aml_scope("PCI0"); 1015 1016 aml_append(pci0_scope, build_prt(true)); 1017 aml_append(sb_scope, pci0_scope); 1018 1019 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1020 aml_append(field, aml_named_field("PRQ0", 8)); 1021 aml_append(field, aml_named_field("PRQ1", 8)); 1022 aml_append(field, aml_named_field("PRQ2", 8)); 1023 aml_append(field, aml_named_field("PRQ3", 8)); 1024 aml_append(sb_scope, field); 1025 1026 aml_append(sb_scope, build_irq_status_method()); 1027 aml_append(sb_scope, build_iqcr_method(true)); 1028 1029 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1030 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1031 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1032 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1033 1034 dev = aml_device("LNKS"); 1035 { 1036 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1037 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1038 1039 crs = aml_resource_template(); 1040 irqs = 9; 1041 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1042 AML_ACTIVE_HIGH, AML_SHARED, 1043 &irqs, 1)); 1044 aml_append(dev, aml_name_decl("_PRS", crs)); 1045 1046 /* The SCI cannot be disabled and is always attached to GSI 9, 1047 * so these are no-ops. We only need this link to override the 1048 * polarity to active high and match the content of the MADT. 1049 */ 1050 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1051 aml_append(method, aml_return(aml_int(0x0b))); 1052 aml_append(dev, method); 1053 1054 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1055 aml_append(dev, method); 1056 1057 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1058 aml_append(method, aml_return(aml_name("_PRS"))); 1059 aml_append(dev, method); 1060 1061 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1062 aml_append(dev, method); 1063 } 1064 aml_append(sb_scope, dev); 1065 1066 aml_append(table, sb_scope); 1067 } 1068 1069 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1070 { 1071 int i; 1072 int head; 1073 Aml *pkg; 1074 char base = name[3] < 'E' ? 'A' : 'E'; 1075 char *s = g_strdup(name); 1076 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1077 1078 assert(strlen(s) == 4); 1079 1080 head = name[3] - base; 1081 for (i = 0; i < 4; i++) { 1082 if (head + i > 3) { 1083 head = i * -1; 1084 } 1085 s[3] = base + head + i; 1086 pkg = aml_package(4); 1087 aml_append(pkg, a_nr); 1088 aml_append(pkg, aml_int(i)); 1089 aml_append(pkg, aml_name("%s", s)); 1090 aml_append(pkg, aml_int(0)); 1091 aml_append(ctx, pkg); 1092 } 1093 g_free(s); 1094 } 1095 1096 static Aml *build_q35_routing_table(const char *str) 1097 { 1098 int i; 1099 Aml *pkg; 1100 char *name = g_strdup_printf("%s ", str); 1101 1102 pkg = aml_package(128); 1103 for (i = 0; i < 0x18; i++) { 1104 name[3] = 'E' + (i & 0x3); 1105 append_q35_prt_entry(pkg, i, name); 1106 } 1107 1108 name[3] = 'E'; 1109 append_q35_prt_entry(pkg, 0x18, name); 1110 1111 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1112 for (i = 0x0019; i < 0x1e; i++) { 1113 name[3] = 'A'; 1114 append_q35_prt_entry(pkg, i, name); 1115 } 1116 1117 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1118 name[3] = 'E'; 1119 append_q35_prt_entry(pkg, 0x1e, name); 1120 name[3] = 'A'; 1121 append_q35_prt_entry(pkg, 0x1f, name); 1122 1123 g_free(name); 1124 return pkg; 1125 } 1126 1127 static void build_q35_pci0_int(Aml *table) 1128 { 1129 Aml *field; 1130 Aml *method; 1131 Aml *sb_scope = aml_scope("_SB"); 1132 Aml *pci0_scope = aml_scope("PCI0"); 1133 1134 /* Zero => PIC mode, One => APIC Mode */ 1135 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1136 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1137 { 1138 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1139 } 1140 aml_append(table, method); 1141 1142 aml_append(pci0_scope, 1143 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1144 aml_append(pci0_scope, 1145 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1146 1147 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1148 { 1149 Aml *if_ctx; 1150 Aml *else_ctx; 1151 1152 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1153 section 6.2.8.1 */ 1154 /* Note: we provide the same info as the PCI routing 1155 table of the Bochs BIOS */ 1156 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1157 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1158 aml_append(method, if_ctx); 1159 else_ctx = aml_else(); 1160 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1161 aml_append(method, else_ctx); 1162 } 1163 aml_append(pci0_scope, method); 1164 aml_append(sb_scope, pci0_scope); 1165 1166 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1167 aml_append(field, aml_named_field("PRQA", 8)); 1168 aml_append(field, aml_named_field("PRQB", 8)); 1169 aml_append(field, aml_named_field("PRQC", 8)); 1170 aml_append(field, aml_named_field("PRQD", 8)); 1171 aml_append(field, aml_reserved_field(0x20)); 1172 aml_append(field, aml_named_field("PRQE", 8)); 1173 aml_append(field, aml_named_field("PRQF", 8)); 1174 aml_append(field, aml_named_field("PRQG", 8)); 1175 aml_append(field, aml_named_field("PRQH", 8)); 1176 aml_append(sb_scope, field); 1177 1178 aml_append(sb_scope, build_irq_status_method()); 1179 aml_append(sb_scope, build_iqcr_method(false)); 1180 1181 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1182 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1183 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1184 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1185 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1186 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1187 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1188 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1189 1190 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1191 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1192 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1193 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1194 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1195 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1196 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1197 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1198 1199 aml_append(table, sb_scope); 1200 } 1201 1202 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1203 { 1204 Aml *dev; 1205 Aml *resource_template; 1206 1207 /* DRAM controller */ 1208 dev = aml_device("DRAC"); 1209 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1210 1211 resource_template = aml_resource_template(); 1212 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1213 aml_append(resource_template, 1214 aml_qword_memory(AML_POS_DECODE, 1215 AML_MIN_FIXED, 1216 AML_MAX_FIXED, 1217 AML_NON_CACHEABLE, 1218 AML_READ_WRITE, 1219 0x0000000000000000, 1220 mcfg->base, 1221 mcfg->base + mcfg->size - 1, 1222 0x0000000000000000, 1223 mcfg->size)); 1224 } else { 1225 aml_append(resource_template, 1226 aml_dword_memory(AML_POS_DECODE, 1227 AML_MIN_FIXED, 1228 AML_MAX_FIXED, 1229 AML_NON_CACHEABLE, 1230 AML_READ_WRITE, 1231 0x0000000000000000, 1232 mcfg->base, 1233 mcfg->base + mcfg->size - 1, 1234 0x0000000000000000, 1235 mcfg->size)); 1236 } 1237 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1238 1239 return dev; 1240 } 1241 1242 static void build_q35_isa_bridge(Aml *table) 1243 { 1244 Aml *dev; 1245 Aml *scope; 1246 Object *obj; 1247 bool ambiguous; 1248 1249 /* 1250 * temporarily fish out isa bridge, build_q35_isa_bridge() will be dropped 1251 * once PCI is converted to AcpiDevAmlIf and would be ble to generate 1252 * AML for bridge itself 1253 */ 1254 obj = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambiguous); 1255 assert(obj && !ambiguous); 1256 1257 scope = aml_scope("_SB.PCI0"); 1258 dev = aml_device("ISA"); 1259 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1260 1261 call_dev_aml_func(DEVICE(obj), dev); 1262 aml_append(scope, dev); 1263 aml_append(table, scope); 1264 } 1265 1266 static void build_piix4_isa_bridge(Aml *table) 1267 { 1268 Aml *dev; 1269 Aml *scope; 1270 Object *obj; 1271 bool ambiguous; 1272 1273 /* 1274 * temporarily fish out isa bridge, build_piix4_isa_bridge() will be dropped 1275 * once PCI is converted to AcpiDevAmlIf and would be ble to generate 1276 * AML for bridge itself 1277 */ 1278 obj = object_resolve_path_type("", TYPE_PIIX3_PCI_DEVICE, &ambiguous); 1279 assert(obj && !ambiguous); 1280 1281 scope = aml_scope("_SB.PCI0"); 1282 dev = aml_device("ISA"); 1283 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1284 1285 call_dev_aml_func(DEVICE(obj), dev); 1286 aml_append(scope, dev); 1287 aml_append(table, scope); 1288 } 1289 1290 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1291 { 1292 Aml *scope; 1293 Aml *field; 1294 Aml *method; 1295 1296 scope = aml_scope("_SB.PCI0"); 1297 1298 aml_append(scope, 1299 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1300 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1301 aml_append(field, aml_named_field("PCIU", 32)); 1302 aml_append(field, aml_named_field("PCID", 32)); 1303 aml_append(scope, field); 1304 1305 aml_append(scope, 1306 aml_operation_region("SEJ", AML_SYSTEM_IO, 1307 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1308 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1309 aml_append(field, aml_named_field("B0EJ", 32)); 1310 aml_append(scope, field); 1311 1312 aml_append(scope, 1313 aml_operation_region("BNMR", AML_SYSTEM_IO, 1314 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1315 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1316 aml_append(field, aml_named_field("BNUM", 32)); 1317 aml_append(field, aml_named_field("PIDX", 32)); 1318 aml_append(scope, field); 1319 1320 aml_append(scope, aml_mutex("BLCK", 0)); 1321 1322 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1323 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1324 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1325 aml_append(method, 1326 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1327 aml_append(method, aml_release(aml_name("BLCK"))); 1328 aml_append(method, aml_return(aml_int(0))); 1329 aml_append(scope, method); 1330 1331 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1332 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1333 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1334 aml_append(method, 1335 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1336 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1337 aml_append(method, aml_release(aml_name("BLCK"))); 1338 aml_append(method, aml_return(aml_local(0))); 1339 aml_append(scope, method); 1340 1341 aml_append(scope, aml_pci_device_dsm()); 1342 1343 aml_append(table, scope); 1344 } 1345 1346 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1347 { 1348 Aml *if_ctx; 1349 Aml *if_ctx2; 1350 Aml *else_ctx; 1351 Aml *method; 1352 Aml *a_cwd1 = aml_name("CDW1"); 1353 Aml *a_ctrl = aml_local(0); 1354 1355 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1356 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1357 1358 if_ctx = aml_if(aml_equal( 1359 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1360 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1361 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1362 1363 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1364 1365 /* 1366 * Always allow native PME, AER (no dependencies) 1367 * Allow SHPC (PCI bridges can have SHPC controller) 1368 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1369 */ 1370 aml_append(if_ctx, aml_and(a_ctrl, 1371 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1372 1373 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1374 /* Unknown revision */ 1375 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1376 aml_append(if_ctx, if_ctx2); 1377 1378 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1379 /* Capabilities bits were masked */ 1380 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1381 aml_append(if_ctx, if_ctx2); 1382 1383 /* Update DWORD3 in the buffer */ 1384 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1385 aml_append(method, if_ctx); 1386 1387 else_ctx = aml_else(); 1388 /* Unrecognized UUID */ 1389 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1390 aml_append(method, else_ctx); 1391 1392 aml_append(method, aml_return(aml_arg(3))); 1393 return method; 1394 } 1395 1396 static void build_smb0(Aml *table, int devnr, int func) 1397 { 1398 Aml *scope = aml_scope("_SB.PCI0"); 1399 Aml *dev = aml_device("SMB0"); 1400 bool ambiguous; 1401 Object *obj; 1402 /* 1403 * temporarily fish out device hosting SMBUS, build_smb0 will be gone once 1404 * PCI enumeration will be switched to call_dev_aml_func() 1405 */ 1406 obj = object_resolve_path_type("", TYPE_ICH9_SMB_DEVICE, &ambiguous); 1407 assert(obj && !ambiguous); 1408 1409 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1410 call_dev_aml_func(DEVICE(obj), dev); 1411 aml_append(scope, dev); 1412 aml_append(table, scope); 1413 } 1414 1415 static void build_acpi0017(Aml *table) 1416 { 1417 Aml *dev, *scope, *method; 1418 1419 scope = aml_scope("_SB"); 1420 dev = aml_device("CXLM"); 1421 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1422 1423 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1424 aml_append(method, aml_return(aml_int(0x01))); 1425 aml_append(dev, method); 1426 1427 aml_append(scope, dev); 1428 aml_append(table, scope); 1429 } 1430 1431 static void 1432 build_dsdt(GArray *table_data, BIOSLinker *linker, 1433 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1434 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1435 { 1436 CrsRangeEntry *entry; 1437 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1438 CrsRangeSet crs_range_set; 1439 PCMachineState *pcms = PC_MACHINE(machine); 1440 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1441 X86MachineState *x86ms = X86_MACHINE(machine); 1442 AcpiMcfgInfo mcfg; 1443 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1444 uint32_t nr_mem = machine->ram_slots; 1445 int root_bus_limit = 0xFF; 1446 PCIBus *bus = NULL; 1447 #ifdef CONFIG_TPM 1448 TPMIf *tpm = tpm_find(); 1449 #endif 1450 bool cxl_present = false; 1451 int i; 1452 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1453 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1454 .oem_table_id = x86ms->oem_table_id }; 1455 1456 acpi_table_begin(&table, table_data); 1457 dsdt = init_aml_allocator(); 1458 1459 build_dbg_aml(dsdt); 1460 if (misc->is_piix4) { 1461 sb_scope = aml_scope("_SB"); 1462 dev = aml_device("PCI0"); 1463 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1464 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1465 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1466 aml_append(sb_scope, dev); 1467 aml_append(dsdt, sb_scope); 1468 1469 if (misc->has_hpet) { 1470 build_hpet_aml(dsdt); 1471 } 1472 build_piix4_isa_bridge(dsdt); 1473 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1474 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1475 } 1476 build_piix4_pci0_int(dsdt); 1477 } else { 1478 sb_scope = aml_scope("_SB"); 1479 dev = aml_device("PCI0"); 1480 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1481 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1482 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1483 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1484 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1485 aml_append(sb_scope, dev); 1486 if (mcfg_valid) { 1487 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1488 } 1489 1490 if (pm->smi_on_cpuhp) { 1491 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1492 dev = aml_device("PCI0.SMI0"); 1493 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1494 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1495 crs = aml_resource_template(); 1496 aml_append(crs, 1497 aml_io( 1498 AML_DECODE16, 1499 ACPI_PORT_SMI_CMD, 1500 ACPI_PORT_SMI_CMD, 1501 1, 1502 2) 1503 ); 1504 aml_append(dev, aml_name_decl("_CRS", crs)); 1505 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1506 aml_int(ACPI_PORT_SMI_CMD), 2)); 1507 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1508 AML_WRITE_AS_ZEROS); 1509 aml_append(field, aml_named_field("SMIC", 8)); 1510 aml_append(field, aml_reserved_field(8)); 1511 aml_append(dev, field); 1512 aml_append(sb_scope, dev); 1513 } 1514 1515 aml_append(dsdt, sb_scope); 1516 1517 if (misc->has_hpet) { 1518 build_hpet_aml(dsdt); 1519 } 1520 build_q35_isa_bridge(dsdt); 1521 if (pm->pcihp_bridge_en) { 1522 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1523 } 1524 build_q35_pci0_int(dsdt); 1525 if (pcms->smbus) { 1526 build_smb0(dsdt, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1527 } 1528 } 1529 1530 if (vmbus_bridge) { 1531 sb_scope = aml_scope("_SB"); 1532 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1533 aml_append(dsdt, sb_scope); 1534 } 1535 1536 if (pcmc->legacy_cpu_hotplug) { 1537 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1538 } else { 1539 CPUHotplugFeatures opts = { 1540 .acpi_1_compatible = true, .has_legacy_cphp = true, 1541 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1542 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1543 }; 1544 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1545 "\\_SB.PCI0", "\\_GPE._E02"); 1546 } 1547 1548 if (pcms->memhp_io_base && nr_mem) { 1549 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1550 "\\_GPE._E03", AML_SYSTEM_IO, 1551 pcms->memhp_io_base); 1552 } 1553 1554 scope = aml_scope("_GPE"); 1555 { 1556 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1557 1558 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1559 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1560 aml_append(method, 1561 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1562 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1563 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1564 aml_append(scope, method); 1565 } 1566 1567 if (machine->nvdimms_state->is_enabled) { 1568 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1569 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1570 aml_int(0x80))); 1571 aml_append(scope, method); 1572 } 1573 } 1574 aml_append(dsdt, scope); 1575 1576 crs_range_set_init(&crs_range_set); 1577 bus = PC_MACHINE(machine)->bus; 1578 if (bus) { 1579 QLIST_FOREACH(bus, &bus->child, sibling) { 1580 uint8_t bus_num = pci_bus_num(bus); 1581 uint8_t numa_node = pci_bus_numa_node(bus); 1582 1583 /* look only for expander root buses */ 1584 if (!pci_bus_is_root(bus)) { 1585 continue; 1586 } 1587 1588 if (bus_num < root_bus_limit) { 1589 root_bus_limit = bus_num - 1; 1590 } 1591 1592 scope = aml_scope("\\_SB"); 1593 1594 if (pci_bus_is_cxl(bus)) { 1595 dev = aml_device("CL%.02X", bus_num); 1596 } else { 1597 dev = aml_device("PC%.02X", bus_num); 1598 } 1599 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1600 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1601 if (pci_bus_is_cxl(bus)) { 1602 struct Aml *pkg = aml_package(2); 1603 1604 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1605 aml_append(pkg, aml_eisaid("PNP0A08")); 1606 aml_append(pkg, aml_eisaid("PNP0A03")); 1607 aml_append(dev, aml_name_decl("_CID", pkg)); 1608 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1609 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1610 build_cxl_osc_method(dev); 1611 } else if (pci_bus_is_express(bus)) { 1612 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1613 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1614 1615 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1616 aml_append(dev, build_q35_osc_method(true)); 1617 } else { 1618 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1619 } 1620 1621 if (numa_node != NUMA_NODE_UNASSIGNED) { 1622 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1623 } 1624 1625 aml_append(dev, build_prt(false)); 1626 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1627 0, 0, 0, 0); 1628 aml_append(dev, aml_name_decl("_CRS", crs)); 1629 aml_append(scope, dev); 1630 aml_append(dsdt, scope); 1631 1632 /* Handle the ranges for the PXB expanders */ 1633 if (pci_bus_is_cxl(bus)) { 1634 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1635 uint64_t base = mr->addr; 1636 1637 cxl_present = true; 1638 crs_range_insert(crs_range_set.mem_ranges, base, 1639 base + memory_region_size(mr) - 1); 1640 } 1641 } 1642 } 1643 1644 if (cxl_present) { 1645 build_acpi0017(dsdt); 1646 } 1647 1648 /* 1649 * At this point crs_range_set has all the ranges used by pci 1650 * busses *other* than PCI0. These ranges will be excluded from 1651 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1652 * too. 1653 */ 1654 if (mcfg_valid) { 1655 crs_range_insert(crs_range_set.mem_ranges, 1656 mcfg.base, mcfg.base + mcfg.size - 1); 1657 } 1658 1659 scope = aml_scope("\\_SB.PCI0"); 1660 /* build PCI0._CRS */ 1661 crs = aml_resource_template(); 1662 aml_append(crs, 1663 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1664 0x0000, 0x0, root_bus_limit, 1665 0x0000, root_bus_limit + 1)); 1666 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1667 1668 aml_append(crs, 1669 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1670 AML_POS_DECODE, AML_ENTIRE_RANGE, 1671 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1672 1673 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1674 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1675 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1676 aml_append(crs, 1677 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1678 AML_POS_DECODE, AML_ENTIRE_RANGE, 1679 0x0000, entry->base, entry->limit, 1680 0x0000, entry->limit - entry->base + 1)); 1681 } 1682 1683 aml_append(crs, 1684 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1685 AML_CACHEABLE, AML_READ_WRITE, 1686 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1687 1688 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1689 range_lob(pci_hole), 1690 range_upb(pci_hole)); 1691 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1692 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1693 aml_append(crs, 1694 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1695 AML_NON_CACHEABLE, AML_READ_WRITE, 1696 0, entry->base, entry->limit, 1697 0, entry->limit - entry->base + 1)); 1698 } 1699 1700 if (!range_is_empty(pci_hole64)) { 1701 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1702 range_lob(pci_hole64), 1703 range_upb(pci_hole64)); 1704 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1705 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1706 aml_append(crs, 1707 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1708 AML_MAX_FIXED, 1709 AML_CACHEABLE, AML_READ_WRITE, 1710 0, entry->base, entry->limit, 1711 0, entry->limit - entry->base + 1)); 1712 } 1713 } 1714 1715 #ifdef CONFIG_TPM 1716 if (TPM_IS_TIS_ISA(tpm_find())) { 1717 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1718 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1719 } 1720 #endif 1721 aml_append(scope, aml_name_decl("_CRS", crs)); 1722 1723 /* reserve GPE0 block resources */ 1724 dev = aml_device("GPE0"); 1725 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1726 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1727 /* device present, functioning, decoding, not shown in UI */ 1728 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1729 crs = aml_resource_template(); 1730 aml_append(crs, 1731 aml_io( 1732 AML_DECODE16, 1733 pm->fadt.gpe0_blk.address, 1734 pm->fadt.gpe0_blk.address, 1735 1, 1736 pm->fadt.gpe0_blk.bit_width / 8) 1737 ); 1738 aml_append(dev, aml_name_decl("_CRS", crs)); 1739 aml_append(scope, dev); 1740 1741 crs_range_set_free(&crs_range_set); 1742 1743 /* reserve PCIHP resources */ 1744 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1745 dev = aml_device("PHPR"); 1746 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1747 aml_append(dev, 1748 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1749 /* device present, functioning, decoding, not shown in UI */ 1750 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1751 crs = aml_resource_template(); 1752 aml_append(crs, 1753 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1754 pm->pcihp_io_len) 1755 ); 1756 aml_append(dev, aml_name_decl("_CRS", crs)); 1757 aml_append(scope, dev); 1758 } 1759 aml_append(dsdt, scope); 1760 1761 /* create S3_ / S4_ / S5_ packages if necessary */ 1762 scope = aml_scope("\\"); 1763 if (!pm->s3_disabled) { 1764 pkg = aml_package(4); 1765 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1766 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1767 aml_append(pkg, aml_int(0)); /* reserved */ 1768 aml_append(pkg, aml_int(0)); /* reserved */ 1769 aml_append(scope, aml_name_decl("_S3", pkg)); 1770 } 1771 1772 if (!pm->s4_disabled) { 1773 pkg = aml_package(4); 1774 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1775 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1776 aml_append(pkg, aml_int(pm->s4_val)); 1777 aml_append(pkg, aml_int(0)); /* reserved */ 1778 aml_append(pkg, aml_int(0)); /* reserved */ 1779 aml_append(scope, aml_name_decl("_S4", pkg)); 1780 } 1781 1782 pkg = aml_package(4); 1783 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1784 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1785 aml_append(pkg, aml_int(0)); /* reserved */ 1786 aml_append(pkg, aml_int(0)); /* reserved */ 1787 aml_append(scope, aml_name_decl("_S5", pkg)); 1788 aml_append(dsdt, scope); 1789 1790 /* create fw_cfg node, unconditionally */ 1791 { 1792 scope = aml_scope("\\_SB.PCI0"); 1793 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1794 aml_append(dsdt, scope); 1795 } 1796 1797 sb_scope = aml_scope("\\_SB"); 1798 { 1799 Object *pci_host = acpi_get_i386_pci_host(); 1800 1801 if (pci_host) { 1802 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1803 Aml *scope = aml_scope("PCI0"); 1804 /* Scan all PCI buses. Generate tables to support hotplug. */ 1805 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1806 aml_append(sb_scope, scope); 1807 } 1808 } 1809 1810 #ifdef CONFIG_TPM 1811 if (TPM_IS_CRB(tpm)) { 1812 dev = aml_device("TPM"); 1813 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1814 aml_append(dev, aml_name_decl("_STR", 1815 aml_string("TPM 2.0 Device"))); 1816 crs = aml_resource_template(); 1817 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1818 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1819 aml_append(dev, aml_name_decl("_CRS", crs)); 1820 1821 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1822 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1823 1824 tpm_build_ppi_acpi(tpm, dev); 1825 1826 aml_append(sb_scope, dev); 1827 } 1828 #endif 1829 1830 if (pcms->sgx_epc.size != 0) { 1831 uint64_t epc_base = pcms->sgx_epc.base; 1832 uint64_t epc_size = pcms->sgx_epc.size; 1833 1834 dev = aml_device("EPC"); 1835 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1836 aml_append(dev, aml_name_decl("_STR", 1837 aml_unicode("Enclave Page Cache 1.0"))); 1838 crs = aml_resource_template(); 1839 aml_append(crs, 1840 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1841 AML_MAX_FIXED, AML_NON_CACHEABLE, 1842 AML_READ_WRITE, 0, epc_base, 1843 epc_base + epc_size - 1, 0, epc_size)); 1844 aml_append(dev, aml_name_decl("_CRS", crs)); 1845 1846 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1847 aml_append(method, aml_return(aml_int(0x0f))); 1848 aml_append(dev, method); 1849 1850 aml_append(sb_scope, dev); 1851 } 1852 aml_append(dsdt, sb_scope); 1853 1854 /* copy AML table into ACPI tables blob and patch header there */ 1855 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1856 acpi_table_end(linker, &table); 1857 free_aml_allocator(); 1858 } 1859 1860 /* 1861 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1862 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1863 */ 1864 static void 1865 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1866 const char *oem_table_id) 1867 { 1868 AcpiTable table = { .sig = "HPET", .rev = 1, 1869 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1870 1871 acpi_table_begin(&table, table_data); 1872 /* Note timer_block_id value must be kept in sync with value advertised by 1873 * emulated hpet 1874 */ 1875 /* Event Timer Block ID */ 1876 build_append_int_noprefix(table_data, 0x8086a201, 4); 1877 /* BASE_ADDRESS */ 1878 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1879 /* HPET Number */ 1880 build_append_int_noprefix(table_data, 0, 1); 1881 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1882 build_append_int_noprefix(table_data, 0, 2); 1883 /* Page Protection And OEM Attribute */ 1884 build_append_int_noprefix(table_data, 0, 1); 1885 acpi_table_end(linker, &table); 1886 } 1887 1888 #ifdef CONFIG_TPM 1889 /* 1890 * TCPA Description Table 1891 * 1892 * Following Level 00, Rev 00.37 of specs: 1893 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1894 * 7.1.2 ACPI Table Layout 1895 */ 1896 static void 1897 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1898 const char *oem_id, const char *oem_table_id) 1899 { 1900 unsigned log_addr_offset; 1901 AcpiTable table = { .sig = "TCPA", .rev = 2, 1902 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1903 1904 acpi_table_begin(&table, table_data); 1905 /* Platform Class */ 1906 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1907 /* Log Area Minimum Length (LAML) */ 1908 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1909 /* Log Area Start Address (LASA) */ 1910 log_addr_offset = table_data->len; 1911 build_append_int_noprefix(table_data, 0, 8); 1912 1913 /* allocate/reserve space for TPM log area */ 1914 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1915 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1916 false /* high memory */); 1917 /* log area start address to be filled by Guest linker */ 1918 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1919 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1920 1921 acpi_table_end(linker, &table); 1922 } 1923 #endif 1924 1925 #define HOLE_640K_START (640 * KiB) 1926 #define HOLE_640K_END (1 * MiB) 1927 1928 /* 1929 * ACPI spec, Revision 3.0 1930 * 5.2.15 System Resource Affinity Table (SRAT) 1931 */ 1932 static void 1933 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1934 { 1935 int i; 1936 int numa_mem_start, slots; 1937 uint64_t mem_len, mem_base, next_base; 1938 MachineClass *mc = MACHINE_GET_CLASS(machine); 1939 X86MachineState *x86ms = X86_MACHINE(machine); 1940 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1941 PCMachineState *pcms = PC_MACHINE(machine); 1942 int nb_numa_nodes = machine->numa_state->num_nodes; 1943 NodeInfo *numa_info = machine->numa_state->nodes; 1944 ram_addr_t hotpluggable_address_space_size = 1945 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1946 NULL); 1947 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1948 .oem_table_id = x86ms->oem_table_id }; 1949 1950 acpi_table_begin(&table, table_data); 1951 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1952 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1953 1954 for (i = 0; i < apic_ids->len; i++) { 1955 int node_id = apic_ids->cpus[i].props.node_id; 1956 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1957 1958 if (apic_id < 255) { 1959 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1960 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1961 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1962 /* Proximity Domain [7:0] */ 1963 build_append_int_noprefix(table_data, node_id, 1); 1964 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1965 /* Flags, Table 5-36 */ 1966 build_append_int_noprefix(table_data, 1, 4); 1967 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1968 /* Proximity Domain [31:8] */ 1969 build_append_int_noprefix(table_data, 0, 3); 1970 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1971 } else { 1972 /* 1973 * ACPI spec, Revision 4.0 1974 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1975 */ 1976 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1977 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1978 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1979 /* Proximity Domain */ 1980 build_append_int_noprefix(table_data, node_id, 4); 1981 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1982 /* Flags, Table 5-39 */ 1983 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1984 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1985 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1986 } 1987 } 1988 1989 /* the memory map is a bit tricky, it contains at least one hole 1990 * from 640k-1M and possibly another one from 3.5G-4G. 1991 */ 1992 next_base = 0; 1993 numa_mem_start = table_data->len; 1994 1995 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1996 mem_base = next_base; 1997 mem_len = numa_info[i - 1].node_mem; 1998 next_base = mem_base + mem_len; 1999 2000 /* Cut out the 640K hole */ 2001 if (mem_base <= HOLE_640K_START && 2002 next_base > HOLE_640K_START) { 2003 mem_len -= next_base - HOLE_640K_START; 2004 if (mem_len > 0) { 2005 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2006 MEM_AFFINITY_ENABLED); 2007 } 2008 2009 /* Check for the rare case: 640K < RAM < 1M */ 2010 if (next_base <= HOLE_640K_END) { 2011 next_base = HOLE_640K_END; 2012 continue; 2013 } 2014 mem_base = HOLE_640K_END; 2015 mem_len = next_base - HOLE_640K_END; 2016 } 2017 2018 /* Cut out the ACPI_PCI hole */ 2019 if (mem_base <= x86ms->below_4g_mem_size && 2020 next_base > x86ms->below_4g_mem_size) { 2021 mem_len -= next_base - x86ms->below_4g_mem_size; 2022 if (mem_len > 0) { 2023 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2024 MEM_AFFINITY_ENABLED); 2025 } 2026 mem_base = 1ULL << 32; 2027 mem_len = next_base - x86ms->below_4g_mem_size; 2028 next_base = mem_base + mem_len; 2029 } 2030 2031 if (mem_len > 0) { 2032 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2033 MEM_AFFINITY_ENABLED); 2034 } 2035 } 2036 2037 if (machine->nvdimms_state->is_enabled) { 2038 nvdimm_build_srat(table_data); 2039 } 2040 2041 sgx_epc_build_srat(table_data); 2042 2043 /* 2044 * TODO: this part is not in ACPI spec and current linux kernel boots fine 2045 * without these entries. But I recall there were issues the last time I 2046 * tried to remove it with some ancient guest OS, however I can't remember 2047 * what that was so keep this around for now 2048 */ 2049 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 2050 for (; slots < nb_numa_nodes + 2; slots++) { 2051 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2052 } 2053 2054 /* 2055 * Entry is required for Windows to enable memory hotplug in OS 2056 * and for Linux to enable SWIOTLB when booted with less than 2057 * 4G of RAM. Windows works better if the entry sets proximity 2058 * to the highest NUMA node in the machine. 2059 * Memory devices may override proximity set by this entry, 2060 * providing _PXM method if necessary. 2061 */ 2062 if (hotpluggable_address_space_size) { 2063 build_srat_memory(table_data, machine->device_memory->base, 2064 hotpluggable_address_space_size, nb_numa_nodes - 1, 2065 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2066 } 2067 2068 acpi_table_end(linker, &table); 2069 } 2070 2071 /* 2072 * Insert DMAR scope for PCI bridges and endpoint devcie 2073 */ 2074 static void 2075 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2076 { 2077 const size_t device_scope_size = 6 /* device scope structure */ + 2078 2 /* 1 path entry */; 2079 GArray *scope_blob = opaque; 2080 2081 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2082 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2083 build_append_int_noprefix(scope_blob, 0x02, 1); 2084 } else { 2085 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2086 build_append_int_noprefix(scope_blob, 0x01, 1); 2087 } 2088 2089 /* length */ 2090 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2091 /* reserved */ 2092 build_append_int_noprefix(scope_blob, 0, 2); 2093 /* enumeration_id */ 2094 build_append_int_noprefix(scope_blob, 0, 1); 2095 /* bus */ 2096 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2097 /* device */ 2098 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2099 /* function */ 2100 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2101 } 2102 2103 /* For a given PCI host bridge, walk and insert DMAR scope */ 2104 static int 2105 dmar_host_bridges(Object *obj, void *opaque) 2106 { 2107 GArray *scope_blob = opaque; 2108 2109 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2110 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2111 2112 if (bus && !pci_bus_bypass_iommu(bus)) { 2113 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2114 } 2115 } 2116 2117 return 0; 2118 } 2119 2120 /* 2121 * Intel ® Virtualization Technology for Directed I/O 2122 * Architecture Specification. Revision 3.3 2123 * 8.1 DMA Remapping Reporting Structure 2124 */ 2125 static void 2126 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2127 const char *oem_table_id) 2128 { 2129 uint8_t dmar_flags = 0; 2130 uint8_t rsvd10[10] = {}; 2131 /* Root complex IOAPIC uses one path only */ 2132 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2133 2 /* 1 path entry */; 2134 X86IOMMUState *iommu = x86_iommu_get_default(); 2135 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2136 GArray *scope_blob = g_array_new(false, true, 1); 2137 2138 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2139 .oem_table_id = oem_table_id }; 2140 2141 /* 2142 * A PCI bus walk, for each PCI host bridge. 2143 * Insert scope for each PCI bridge and endpoint device which 2144 * is attached to a bus with iommu enabled. 2145 */ 2146 object_child_foreach_recursive(object_get_root(), 2147 dmar_host_bridges, scope_blob); 2148 2149 assert(iommu); 2150 if (x86_iommu_ir_supported(iommu)) { 2151 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2152 } 2153 2154 acpi_table_begin(&table, table_data); 2155 /* Host Address Width */ 2156 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2157 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2158 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2159 2160 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2161 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2162 /* Length */ 2163 build_append_int_noprefix(table_data, 2164 16 + ioapic_scope_size + scope_blob->len, 2); 2165 /* Flags */ 2166 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2167 1); 2168 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2169 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2170 /* Register Base Address */ 2171 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2172 2173 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2174 * 8.3.1 (version Oct. 2014 or later). */ 2175 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2176 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2177 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2178 /* Enumeration ID */ 2179 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2180 /* Start Bus Number */ 2181 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2182 /* Path, {Device, Function} pair */ 2183 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2184 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2185 2186 /* Add scope found above */ 2187 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2188 g_array_free(scope_blob, true); 2189 2190 if (iommu->dt_supported) { 2191 /* 8.5 Root Port ATS Capability Reporting Structure */ 2192 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2193 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2194 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2195 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2196 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2197 } 2198 2199 acpi_table_end(linker, &table); 2200 } 2201 2202 /* 2203 * Windows ACPI Emulated Devices Table 2204 * (Version 1.0 - April 6, 2009) 2205 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2206 * 2207 * Helpful to speedup Windows guests and ignored by others. 2208 */ 2209 static void 2210 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2211 const char *oem_table_id) 2212 { 2213 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2214 .oem_table_id = oem_table_id }; 2215 2216 acpi_table_begin(&table, table_data); 2217 /* 2218 * Set "ACPI PM timer good" flag. 2219 * 2220 * Tells Windows guests that our ACPI PM timer is reliable in the 2221 * sense that guest can read it only once to obtain a reliable value. 2222 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2223 */ 2224 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2225 acpi_table_end(linker, &table); 2226 } 2227 2228 /* 2229 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2230 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2231 */ 2232 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2233 2234 /* 2235 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2236 * necessary for the PCI topology. 2237 */ 2238 static void 2239 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2240 { 2241 GArray *table_data = opaque; 2242 uint32_t entry; 2243 2244 /* "Select" IVHD entry, type 0x2 */ 2245 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2246 build_append_int_noprefix(table_data, entry, 4); 2247 2248 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2249 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2250 uint8_t sec = pci_bus_num(sec_bus); 2251 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2252 2253 if (pci_bus_is_express(sec_bus)) { 2254 /* 2255 * Walk the bus if there are subordinates, otherwise use a range 2256 * to cover an entire leaf bus. We could potentially also use a 2257 * range for traversed buses, but we'd need to take care not to 2258 * create both Select and Range entries covering the same device. 2259 * This is easier and potentially more compact. 2260 * 2261 * An example bare metal system seems to use Select entries for 2262 * root ports without a slot (ie. built-ins) and Range entries 2263 * when there is a slot. The same system also only hard-codes 2264 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2265 * making no effort to support nested bridges. We attempt to 2266 * be more thorough here. 2267 */ 2268 if (sec == sub) { /* leaf bus */ 2269 /* "Start of Range" IVHD entry, type 0x3 */ 2270 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2271 build_append_int_noprefix(table_data, entry, 4); 2272 /* "End of Range" IVHD entry, type 0x4 */ 2273 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2274 build_append_int_noprefix(table_data, entry, 4); 2275 } else { 2276 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2277 } 2278 } else { 2279 /* 2280 * If the secondary bus is conventional, then we need to create an 2281 * Alias range for everything downstream. The range covers the 2282 * first devfn on the secondary bus to the last devfn on the 2283 * subordinate bus. The alias target depends on legacy versus 2284 * express bridges, just as in pci_device_iommu_address_space(). 2285 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2286 */ 2287 uint16_t dev_id_a, dev_id_b; 2288 2289 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2290 2291 if (pci_is_express(dev) && 2292 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2293 dev_id_b = dev_id_a; 2294 } else { 2295 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2296 } 2297 2298 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2299 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2300 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2301 2302 /* "End of Range" IVHD entry, type 0x4 */ 2303 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2304 build_append_int_noprefix(table_data, entry, 4); 2305 } 2306 } 2307 } 2308 2309 /* For all PCI host bridges, walk and insert IVHD entries */ 2310 static int 2311 ivrs_host_bridges(Object *obj, void *opaque) 2312 { 2313 GArray *ivhd_blob = opaque; 2314 2315 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2316 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2317 2318 if (bus && !pci_bus_bypass_iommu(bus)) { 2319 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2320 } 2321 } 2322 2323 return 0; 2324 } 2325 2326 static void 2327 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2328 const char *oem_table_id) 2329 { 2330 int ivhd_table_len = 24; 2331 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2332 GArray *ivhd_blob = g_array_new(false, true, 1); 2333 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2334 .oem_table_id = oem_table_id }; 2335 2336 acpi_table_begin(&table, table_data); 2337 /* IVinfo - IO virtualization information common to all 2338 * IOMMU units in a system 2339 */ 2340 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2341 /* reserved */ 2342 build_append_int_noprefix(table_data, 0, 8); 2343 2344 /* IVHD definition - type 10h */ 2345 build_append_int_noprefix(table_data, 0x10, 1); 2346 /* virtualization flags */ 2347 build_append_int_noprefix(table_data, 2348 (1UL << 0) | /* HtTunEn */ 2349 (1UL << 4) | /* iotblSup */ 2350 (1UL << 6) | /* PrefSup */ 2351 (1UL << 7), /* PPRSup */ 2352 1); 2353 2354 /* 2355 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2356 * complete set of IVHD entries. Do this into a separate blob so that we 2357 * can calculate the total IVRS table length here and then append the new 2358 * blob further below. Fall back to an entry covering all devices, which 2359 * is sufficient when no aliases are present. 2360 */ 2361 object_child_foreach_recursive(object_get_root(), 2362 ivrs_host_bridges, ivhd_blob); 2363 2364 if (!ivhd_blob->len) { 2365 /* 2366 * Type 1 device entry reporting all devices 2367 * These are 4-byte device entries currently reporting the range of 2368 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2369 */ 2370 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2371 } 2372 2373 ivhd_table_len += ivhd_blob->len; 2374 2375 /* 2376 * When interrupt remapping is supported, we add a special IVHD device 2377 * for type IO-APIC. 2378 */ 2379 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2380 ivhd_table_len += 8; 2381 } 2382 2383 /* IVHD length */ 2384 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2385 /* DeviceID */ 2386 build_append_int_noprefix(table_data, s->devid, 2); 2387 /* Capability offset */ 2388 build_append_int_noprefix(table_data, s->capab_offset, 2); 2389 /* IOMMU base address */ 2390 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2391 /* PCI Segment Group */ 2392 build_append_int_noprefix(table_data, 0, 2); 2393 /* IOMMU info */ 2394 build_append_int_noprefix(table_data, 0, 2); 2395 /* IOMMU Feature Reporting */ 2396 build_append_int_noprefix(table_data, 2397 (48UL << 30) | /* HATS */ 2398 (48UL << 28) | /* GATS */ 2399 (1UL << 2) | /* GTSup */ 2400 (1UL << 6), /* GASup */ 2401 4); 2402 2403 /* IVHD entries as found above */ 2404 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2405 g_array_free(ivhd_blob, TRUE); 2406 2407 /* 2408 * Add a special IVHD device type. 2409 * Refer to spec - Table 95: IVHD device entry type codes 2410 * 2411 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2412 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2413 */ 2414 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2415 build_append_int_noprefix(table_data, 2416 (0x1ull << 56) | /* type IOAPIC */ 2417 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2418 0x48, /* special device */ 2419 8); 2420 } 2421 acpi_table_end(linker, &table); 2422 } 2423 2424 typedef 2425 struct AcpiBuildState { 2426 /* Copy of table in RAM (for patching). */ 2427 MemoryRegion *table_mr; 2428 /* Is table patched? */ 2429 uint8_t patched; 2430 void *rsdp; 2431 MemoryRegion *rsdp_mr; 2432 MemoryRegion *linker_mr; 2433 } AcpiBuildState; 2434 2435 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2436 { 2437 Object *pci_host; 2438 QObject *o; 2439 2440 pci_host = acpi_get_i386_pci_host(); 2441 if (!pci_host) { 2442 return false; 2443 } 2444 2445 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2446 if (!o) { 2447 return false; 2448 } 2449 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2450 qobject_unref(o); 2451 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2452 return false; 2453 } 2454 2455 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2456 assert(o); 2457 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2458 qobject_unref(o); 2459 return true; 2460 } 2461 2462 static 2463 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2464 { 2465 PCMachineState *pcms = PC_MACHINE(machine); 2466 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2467 X86MachineState *x86ms = X86_MACHINE(machine); 2468 DeviceState *iommu = pcms->iommu; 2469 GArray *table_offsets; 2470 unsigned facs, dsdt, rsdt, fadt; 2471 AcpiPmInfo pm; 2472 AcpiMiscInfo misc; 2473 AcpiMcfgInfo mcfg; 2474 Range pci_hole = {}, pci_hole64 = {}; 2475 uint8_t *u; 2476 size_t aml_len = 0; 2477 GArray *tables_blob = tables->table_data; 2478 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2479 Object *vmgenid_dev; 2480 char *oem_id; 2481 char *oem_table_id; 2482 2483 acpi_get_pm_info(machine, &pm); 2484 acpi_get_misc_info(&misc); 2485 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2486 acpi_get_slic_oem(&slic_oem); 2487 2488 if (slic_oem.id) { 2489 oem_id = slic_oem.id; 2490 } else { 2491 oem_id = x86ms->oem_id; 2492 } 2493 2494 if (slic_oem.table_id) { 2495 oem_table_id = slic_oem.table_id; 2496 } else { 2497 oem_table_id = x86ms->oem_table_id; 2498 } 2499 2500 table_offsets = g_array_new(false, true /* clear */, 2501 sizeof(uint32_t)); 2502 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2503 2504 bios_linker_loader_alloc(tables->linker, 2505 ACPI_BUILD_TABLE_FILE, tables_blob, 2506 64 /* Ensure FACS is aligned */, 2507 false /* high memory */); 2508 2509 /* 2510 * FACS is pointed to by FADT. 2511 * We place it first since it's the only table that has alignment 2512 * requirements. 2513 */ 2514 facs = tables_blob->len; 2515 build_facs(tables_blob); 2516 2517 /* DSDT is pointed to by FADT */ 2518 dsdt = tables_blob->len; 2519 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2520 &pci_hole, &pci_hole64, machine); 2521 2522 /* Count the size of the DSDT and SSDT, we will need it for legacy 2523 * sizing of ACPI tables. 2524 */ 2525 aml_len += tables_blob->len - dsdt; 2526 2527 /* ACPI tables pointed to by RSDT */ 2528 fadt = tables_blob->len; 2529 acpi_add_table(table_offsets, tables_blob); 2530 pm.fadt.facs_tbl_offset = &facs; 2531 pm.fadt.dsdt_tbl_offset = &dsdt; 2532 pm.fadt.xdsdt_tbl_offset = &dsdt; 2533 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2534 aml_len += tables_blob->len - fadt; 2535 2536 acpi_add_table(table_offsets, tables_blob); 2537 acpi_build_madt(tables_blob, tables->linker, x86ms, 2538 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2539 x86ms->oem_table_id); 2540 2541 #ifdef CONFIG_ACPI_ERST 2542 { 2543 Object *erst_dev; 2544 erst_dev = find_erst_dev(); 2545 if (erst_dev) { 2546 acpi_add_table(table_offsets, tables_blob); 2547 build_erst(tables_blob, tables->linker, erst_dev, 2548 x86ms->oem_id, x86ms->oem_table_id); 2549 } 2550 } 2551 #endif 2552 2553 vmgenid_dev = find_vmgenid_dev(); 2554 if (vmgenid_dev) { 2555 acpi_add_table(table_offsets, tables_blob); 2556 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2557 tables->vmgenid, tables->linker, x86ms->oem_id); 2558 } 2559 2560 if (misc.has_hpet) { 2561 acpi_add_table(table_offsets, tables_blob); 2562 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2563 x86ms->oem_table_id); 2564 } 2565 #ifdef CONFIG_TPM 2566 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2567 if (misc.tpm_version == TPM_VERSION_1_2) { 2568 acpi_add_table(table_offsets, tables_blob); 2569 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2570 x86ms->oem_id, x86ms->oem_table_id); 2571 } else { /* TPM_VERSION_2_0 */ 2572 acpi_add_table(table_offsets, tables_blob); 2573 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2574 x86ms->oem_id, x86ms->oem_table_id); 2575 } 2576 } 2577 #endif 2578 if (machine->numa_state->num_nodes) { 2579 acpi_add_table(table_offsets, tables_blob); 2580 build_srat(tables_blob, tables->linker, machine); 2581 if (machine->numa_state->have_numa_distance) { 2582 acpi_add_table(table_offsets, tables_blob); 2583 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2584 x86ms->oem_table_id); 2585 } 2586 if (machine->numa_state->hmat_enabled) { 2587 acpi_add_table(table_offsets, tables_blob); 2588 build_hmat(tables_blob, tables->linker, machine->numa_state, 2589 x86ms->oem_id, x86ms->oem_table_id); 2590 } 2591 } 2592 if (acpi_get_mcfg(&mcfg)) { 2593 acpi_add_table(table_offsets, tables_blob); 2594 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2595 x86ms->oem_table_id); 2596 } 2597 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2598 acpi_add_table(table_offsets, tables_blob); 2599 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2600 x86ms->oem_table_id); 2601 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2602 acpi_add_table(table_offsets, tables_blob); 2603 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2604 x86ms->oem_table_id); 2605 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2606 PCIDevice *pdev = PCI_DEVICE(iommu); 2607 2608 acpi_add_table(table_offsets, tables_blob); 2609 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2610 x86ms->oem_id, x86ms->oem_table_id); 2611 } 2612 if (machine->nvdimms_state->is_enabled) { 2613 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2614 machine->nvdimms_state, machine->ram_slots, 2615 x86ms->oem_id, x86ms->oem_table_id); 2616 } 2617 if (pcms->cxl_devices_state.is_enabled) { 2618 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2619 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2620 } 2621 2622 acpi_add_table(table_offsets, tables_blob); 2623 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2624 2625 /* Add tables supplied by user (if any) */ 2626 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2627 unsigned len = acpi_table_len(u); 2628 2629 acpi_add_table(table_offsets, tables_blob); 2630 g_array_append_vals(tables_blob, u, len); 2631 } 2632 2633 /* RSDT is pointed to by RSDP */ 2634 rsdt = tables_blob->len; 2635 build_rsdt(tables_blob, tables->linker, table_offsets, 2636 oem_id, oem_table_id); 2637 2638 /* RSDP is in FSEG memory, so allocate it separately */ 2639 { 2640 AcpiRsdpData rsdp_data = { 2641 .revision = 0, 2642 .oem_id = x86ms->oem_id, 2643 .xsdt_tbl_offset = NULL, 2644 .rsdt_tbl_offset = &rsdt, 2645 }; 2646 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2647 if (!pcmc->rsdp_in_ram) { 2648 /* We used to allocate some extra space for RSDP revision 2 but 2649 * only used the RSDP revision 0 space. The extra bytes were 2650 * zeroed out and not used. 2651 * Here we continue wasting those extra 16 bytes to make sure we 2652 * don't break migration for machine types 2.2 and older due to 2653 * RSDP blob size mismatch. 2654 */ 2655 build_append_int_noprefix(tables->rsdp, 0, 16); 2656 } 2657 } 2658 2659 /* We'll expose it all to Guest so we want to reduce 2660 * chance of size changes. 2661 * 2662 * We used to align the tables to 4k, but of course this would 2663 * too simple to be enough. 4k turned out to be too small an 2664 * alignment very soon, and in fact it is almost impossible to 2665 * keep the table size stable for all (max_cpus, max_memory_slots) 2666 * combinations. So the table size is always 64k for pc-i440fx-2.1 2667 * and we give an error if the table grows beyond that limit. 2668 * 2669 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2670 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2671 * than 2.0 and we can always pad the smaller tables with zeros. We can 2672 * then use the exact size of the 2.0 tables. 2673 * 2674 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2675 */ 2676 if (pcmc->legacy_acpi_table_size) { 2677 /* Subtracting aml_len gives the size of fixed tables. Then add the 2678 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2679 */ 2680 int legacy_aml_len = 2681 pcmc->legacy_acpi_table_size + 2682 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2683 int legacy_table_size = 2684 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2685 ACPI_BUILD_ALIGN_SIZE); 2686 if (tables_blob->len > legacy_table_size) { 2687 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2688 warn_report("ACPI table size %u exceeds %d bytes," 2689 " migration may not work", 2690 tables_blob->len, legacy_table_size); 2691 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2692 " or PCI bridges."); 2693 } 2694 g_array_set_size(tables_blob, legacy_table_size); 2695 } else { 2696 /* Make sure we have a buffer in case we need to resize the tables. */ 2697 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2698 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2699 warn_report("ACPI table size %u exceeds %d bytes," 2700 " migration may not work", 2701 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2702 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2703 " or PCI bridges."); 2704 } 2705 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2706 } 2707 2708 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2709 2710 /* Cleanup memory that's no longer used. */ 2711 g_array_free(table_offsets, true); 2712 g_free(slic_oem.id); 2713 g_free(slic_oem.table_id); 2714 } 2715 2716 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2717 { 2718 uint32_t size = acpi_data_len(data); 2719 2720 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2721 memory_region_ram_resize(mr, size, &error_abort); 2722 2723 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2724 memory_region_set_dirty(mr, 0, size); 2725 } 2726 2727 static void acpi_build_update(void *build_opaque) 2728 { 2729 AcpiBuildState *build_state = build_opaque; 2730 AcpiBuildTables tables; 2731 2732 /* No state to update or already patched? Nothing to do. */ 2733 if (!build_state || build_state->patched) { 2734 return; 2735 } 2736 build_state->patched = 1; 2737 2738 acpi_build_tables_init(&tables); 2739 2740 acpi_build(&tables, MACHINE(qdev_get_machine())); 2741 2742 acpi_ram_update(build_state->table_mr, tables.table_data); 2743 2744 if (build_state->rsdp) { 2745 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2746 } else { 2747 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2748 } 2749 2750 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2751 acpi_build_tables_cleanup(&tables, true); 2752 } 2753 2754 static void acpi_build_reset(void *build_opaque) 2755 { 2756 AcpiBuildState *build_state = build_opaque; 2757 build_state->patched = 0; 2758 } 2759 2760 static const VMStateDescription vmstate_acpi_build = { 2761 .name = "acpi_build", 2762 .version_id = 1, 2763 .minimum_version_id = 1, 2764 .fields = (VMStateField[]) { 2765 VMSTATE_UINT8(patched, AcpiBuildState), 2766 VMSTATE_END_OF_LIST() 2767 }, 2768 }; 2769 2770 void acpi_setup(void) 2771 { 2772 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2773 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2774 X86MachineState *x86ms = X86_MACHINE(pcms); 2775 AcpiBuildTables tables; 2776 AcpiBuildState *build_state; 2777 Object *vmgenid_dev; 2778 #ifdef CONFIG_TPM 2779 TPMIf *tpm; 2780 static FwCfgTPMConfig tpm_config; 2781 #endif 2782 2783 if (!x86ms->fw_cfg) { 2784 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2785 return; 2786 } 2787 2788 if (!pcms->acpi_build_enabled) { 2789 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2790 return; 2791 } 2792 2793 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2794 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2795 return; 2796 } 2797 2798 build_state = g_malloc0(sizeof *build_state); 2799 2800 acpi_build_tables_init(&tables); 2801 acpi_build(&tables, MACHINE(pcms)); 2802 2803 /* Now expose it all to Guest */ 2804 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2805 build_state, tables.table_data, 2806 ACPI_BUILD_TABLE_FILE); 2807 assert(build_state->table_mr != NULL); 2808 2809 build_state->linker_mr = 2810 acpi_add_rom_blob(acpi_build_update, build_state, 2811 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2812 2813 #ifdef CONFIG_TPM 2814 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2815 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2816 2817 tpm = tpm_find(); 2818 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2819 tpm_config = (FwCfgTPMConfig) { 2820 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2821 .tpm_version = tpm_get_version(tpm), 2822 .tpmppi_version = TPM_PPI_VERSION_1_30 2823 }; 2824 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2825 &tpm_config, sizeof tpm_config); 2826 } 2827 #endif 2828 2829 vmgenid_dev = find_vmgenid_dev(); 2830 if (vmgenid_dev) { 2831 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2832 tables.vmgenid); 2833 } 2834 2835 if (!pcmc->rsdp_in_ram) { 2836 /* 2837 * Keep for compatibility with old machine types. 2838 * Though RSDP is small, its contents isn't immutable, so 2839 * we'll update it along with the rest of tables on guest access. 2840 */ 2841 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2842 2843 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2844 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2845 acpi_build_update, NULL, build_state, 2846 build_state->rsdp, rsdp_size, true); 2847 build_state->rsdp_mr = NULL; 2848 } else { 2849 build_state->rsdp = NULL; 2850 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2851 build_state, tables.rsdp, 2852 ACPI_BUILD_RSDP_FILE); 2853 } 2854 2855 qemu_register_reset(acpi_build_reset, build_state); 2856 acpi_build_reset(build_state); 2857 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2858 2859 /* Cleanup tables but don't free the memory: we track it 2860 * in build_state. 2861 */ 2862 acpi_build_tables_cleanup(&tables, false); 2863 } 2864