1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/ich9.h" 59 #include "hw/southbridge/piix.h" 60 #include "hw/acpi/pcihp.h" 61 #include "hw/i386/fw_cfg.h" 62 #include "hw/i386/pc.h" 63 #include "hw/pci/pci_bus.h" 64 #include "hw/pci-host/i440fx.h" 65 #include "hw/pci-host/q35.h" 66 #include "hw/i386/x86-iommu.h" 67 68 #include "hw/acpi/aml-build.h" 69 #include "hw/acpi/utils.h" 70 #include "hw/acpi/pci.h" 71 #include "hw/acpi/cxl.h" 72 73 #include "qom/qom-qobject.h" 74 #include "hw/i386/amd_iommu.h" 75 #include "hw/i386/intel_iommu.h" 76 #include "hw/virtio/virtio-iommu.h" 77 78 #include "hw/acpi/hmat.h" 79 #include "hw/acpi/viot.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 89 #define ACPI_BUILD_ALIGN_SIZE 0x1000 90 91 #define ACPI_BUILD_TABLE_SIZE 0x20000 92 93 /* #define DEBUG_ACPI_BUILD */ 94 #ifdef DEBUG_ACPI_BUILD 95 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 97 #else 98 #define ACPI_BUILD_DPRINTF(fmt, ...) 99 #endif 100 101 typedef struct AcpiPmInfo { 102 bool s3_disabled; 103 bool s4_disabled; 104 bool pcihp_bridge_en; 105 bool smi_on_cpuhp; 106 bool smi_on_cpu_unplug; 107 bool pcihp_root_en; 108 uint8_t s4_val; 109 AcpiFadtData fadt; 110 uint16_t cpu_hp_io_base; 111 uint16_t pcihp_io_base; 112 uint16_t pcihp_io_len; 113 } AcpiPmInfo; 114 115 typedef struct AcpiMiscInfo { 116 bool has_hpet; 117 #ifdef CONFIG_TPM 118 TPMVersion tpm_version; 119 #endif 120 } AcpiMiscInfo; 121 122 typedef struct FwCfgTPMConfig { 123 uint32_t tpmppi_address; 124 uint8_t tpm_version; 125 uint8_t tpmppi_version; 126 } QEMU_PACKED FwCfgTPMConfig; 127 128 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 129 130 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 131 .space_id = AML_AS_SYSTEM_IO, 132 .address = NVDIMM_ACPI_IO_BASE, 133 .bit_width = NVDIMM_ACPI_IO_LEN << 3 134 }; 135 136 static void init_common_fadt_data(MachineState *ms, Object *o, 137 AcpiFadtData *data) 138 { 139 X86MachineState *x86ms = X86_MACHINE(ms); 140 /* 141 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 142 * behavior for compatibility irrelevant to smm_enabled, which doesn't 143 * comforms to ACPI spec. 144 */ 145 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 146 true : x86_machine_is_smm_enabled(x86ms); 147 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 148 AmlAddressSpace as = AML_AS_SYSTEM_IO; 149 AcpiFadtData fadt = { 150 .rev = 3, 151 .flags = 152 (1 << ACPI_FADT_F_WBINVD) | 153 (1 << ACPI_FADT_F_PROC_C1) | 154 (1 << ACPI_FADT_F_SLP_BUTTON) | 155 (1 << ACPI_FADT_F_RTC_S4) | 156 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 157 /* APIC destination mode ("Flat Logical") has an upper limit of 8 158 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 159 * used 160 */ 161 ((ms->smp.max_cpus > 8) ? 162 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 163 .int_model = 1 /* Multiple APIC */, 164 .rtc_century = RTC_CENTURY, 165 .plvl2_lat = 0xfff /* C2 state not supported */, 166 .plvl3_lat = 0xfff /* C3 state not supported */, 167 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 168 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 169 .acpi_enable_cmd = 170 smm_enabled ? 171 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 172 0, 173 .acpi_disable_cmd = 174 smm_enabled ? 175 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 176 0, 177 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 178 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 179 .address = io + 0x04 }, 180 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 181 .gpe0_blk = { .space_id = as, .bit_width = 182 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 183 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 184 }, 185 }; 186 187 /* 188 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 189 * Flags, bit offset 1 - 8042. 190 */ 191 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 192 193 *data = fadt; 194 } 195 196 static Object *object_resolve_type_unambiguous(const char *typename) 197 { 198 bool ambig; 199 Object *o = object_resolve_path_type("", typename, &ambig); 200 201 if (ambig || !o) { 202 return NULL; 203 } 204 return o; 205 } 206 207 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 208 { 209 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 210 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 211 Object *obj = piix ? piix : lpc; 212 QObject *o; 213 pm->cpu_hp_io_base = 0; 214 pm->pcihp_io_base = 0; 215 pm->pcihp_io_len = 0; 216 pm->smi_on_cpuhp = false; 217 pm->smi_on_cpu_unplug = false; 218 219 assert(obj); 220 init_common_fadt_data(machine, obj, &pm->fadt); 221 if (piix) { 222 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 223 pm->fadt.rev = 1; 224 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 225 } 226 if (lpc) { 227 uint64_t smi_features = object_property_get_uint(lpc, 228 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 229 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 230 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 231 pm->fadt.reset_reg = r; 232 pm->fadt.reset_val = 0xf; 233 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 234 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 235 pm->smi_on_cpuhp = 236 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 237 pm->smi_on_cpu_unplug = 238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 239 } 240 pm->pcihp_io_base = 241 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 242 pm->pcihp_io_len = 243 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 244 245 /* The above need not be conditional on machine type because the reset port 246 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 247 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 248 249 /* Fill in optional s3/s4 related properties */ 250 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 251 if (o) { 252 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 253 } else { 254 pm->s3_disabled = false; 255 } 256 qobject_unref(o); 257 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 258 if (o) { 259 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 260 } else { 261 pm->s4_disabled = false; 262 } 263 qobject_unref(o); 264 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 265 if (o) { 266 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 267 } else { 268 pm->s4_val = false; 269 } 270 qobject_unref(o); 271 272 pm->pcihp_bridge_en = 273 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 274 NULL); 275 pm->pcihp_root_en = 276 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 277 NULL); 278 } 279 280 static void acpi_get_misc_info(AcpiMiscInfo *info) 281 { 282 info->has_hpet = hpet_find(); 283 #ifdef CONFIG_TPM 284 info->tpm_version = tpm_get_version(tpm_find()); 285 #endif 286 } 287 288 /* 289 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 290 * On i386 arch we only have two pci hosts, so we can look only for them. 291 */ 292 Object *acpi_get_i386_pci_host(void) 293 { 294 PCIHostState *host; 295 296 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 297 if (!host) { 298 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 299 } 300 301 return OBJECT(host); 302 } 303 304 static void acpi_get_pci_holes(Range *hole, Range *hole64) 305 { 306 Object *pci_host; 307 308 pci_host = acpi_get_i386_pci_host(); 309 310 if (!pci_host) { 311 return; 312 } 313 314 range_set_bounds1(hole, 315 object_property_get_uint(pci_host, 316 PCI_HOST_PROP_PCI_HOLE_START, 317 NULL), 318 object_property_get_uint(pci_host, 319 PCI_HOST_PROP_PCI_HOLE_END, 320 NULL)); 321 range_set_bounds1(hole64, 322 object_property_get_uint(pci_host, 323 PCI_HOST_PROP_PCI_HOLE64_START, 324 NULL), 325 object_property_get_uint(pci_host, 326 PCI_HOST_PROP_PCI_HOLE64_END, 327 NULL)); 328 } 329 330 static void acpi_align_size(GArray *blob, unsigned align) 331 { 332 /* Align size to multiple of given size. This reduces the chance 333 * we need to change size in the future (breaking cross version migration). 334 */ 335 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 336 } 337 338 /* 339 * ACPI spec 1.0b, 340 * 5.2.6 Firmware ACPI Control Structure 341 */ 342 static void 343 build_facs(GArray *table_data) 344 { 345 const char *sig = "FACS"; 346 const uint8_t reserved[40] = {}; 347 348 g_array_append_vals(table_data, sig, 4); /* Signature */ 349 build_append_int_noprefix(table_data, 64, 4); /* Length */ 350 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 351 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 352 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 353 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 354 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 355 } 356 357 Aml *aml_pci_device_dsm(void) 358 { 359 Aml *method; 360 361 method = aml_method("_DSM", 4, AML_SERIALIZED); 362 { 363 Aml *params = aml_local(0); 364 Aml *pkg = aml_package(2); 365 aml_append(pkg, aml_name("BSEL")); 366 aml_append(pkg, aml_name("ASUN")); 367 aml_append(method, aml_store(pkg, params)); 368 aml_append(method, 369 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 370 aml_arg(2), aml_arg(3), params)) 371 ); 372 } 373 return method; 374 } 375 376 static void build_append_pcihp_notify_entry(Aml *method, int slot) 377 { 378 Aml *if_ctx; 379 int32_t devfn = PCI_DEVFN(slot, 0); 380 381 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 382 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 383 aml_append(method, if_ctx); 384 } 385 386 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) 387 { 388 const PCIDevice *pdev = bus->devices[devfn]; 389 390 if (PCI_FUNC(devfn)) { 391 if (IS_PCI_BRIDGE(pdev)) { 392 /* 393 * Ignore only hotplugged PCI bridges on !0 functions, but 394 * allow describing cold plugged bridges on all functions 395 */ 396 if (DEVICE(pdev)->hotplugged) { 397 return true; 398 } 399 } else if (!get_dev_aml_func(DEVICE(pdev))) { 400 /* 401 * Ignore all other devices on !0 functions unless they 402 * have AML description (i.e have get_dev_aml_func() != 0) 403 */ 404 return true; 405 } 406 } 407 return false; 408 } 409 410 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) 411 { 412 PCIDevice *pdev = bus->devices[devfn]; 413 if (pdev) { 414 return is_devfn_ignored_generic(devfn, bus) || 415 !DEVICE_GET_CLASS(pdev)->hotpluggable || 416 /* Cold plugged bridges aren't themselves hot-pluggable */ 417 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); 418 } else { /* non populated slots */ 419 /* 420 * hotplug is supported only for non-multifunction device 421 * so generate device description only for function 0 422 */ 423 if (PCI_FUNC(devfn) || 424 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { 425 return true; 426 } 427 } 428 return false; 429 } 430 431 static void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus, 432 QObject *bsel) 433 { 434 int devfn; 435 Aml *dev, *notify_method = NULL, *method; 436 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 437 438 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 439 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 440 441 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 442 int slot = PCI_SLOT(devfn); 443 int adr = slot << 16 | PCI_FUNC(devfn); 444 445 if (is_devfn_ignored_hotplug(devfn, bus)) { 446 continue; 447 } 448 449 if (bus->devices[devfn]) { 450 dev = aml_scope("S%.02X", devfn); 451 } else { 452 dev = aml_device("S%.02X", devfn); 453 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 454 } 455 456 /* 457 * Can't declare _SUN here for every device as it changes 'slot' 458 * enumeration order in linux kernel, so use another variable for it 459 */ 460 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 461 aml_append(dev, aml_pci_device_dsm()); 462 463 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 464 /* add _EJ0 to make slot hotpluggable */ 465 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 466 aml_append(method, 467 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 468 ); 469 aml_append(dev, method); 470 471 build_append_pcihp_notify_entry(notify_method, slot); 472 473 /* device descriptor has been composed, add it into parent context */ 474 aml_append(parent_scope, dev); 475 } 476 aml_append(parent_scope, notify_method); 477 } 478 479 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) 480 { 481 QObject *bsel; 482 int devfn; 483 Aml *dev; 484 485 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 486 487 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 488 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 489 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); 490 PCIDevice *pdev = bus->devices[devfn]; 491 492 if (!pdev || is_devfn_ignored_generic(devfn, bus)) { 493 continue; 494 } 495 496 /* start to compose PCI device descriptor */ 497 dev = aml_device("S%.02X", devfn); 498 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 499 500 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); 501 502 /* device descriptor has been composed, add it into parent context */ 503 aml_append(parent_scope, dev); 504 } 505 506 if (bsel) { 507 build_append_pcihp_slots(parent_scope, bus, bsel); 508 } 509 510 qobject_unref(bsel); 511 } 512 513 static bool build_append_notfication_callback(Aml *parent_scope, 514 const PCIBus *bus) 515 { 516 Aml *method; 517 PCIBus *sec; 518 QObject *bsel; 519 int nr_notifiers = 0; 520 GQueue *pcnt_bus_list = g_queue_new(); 521 522 QLIST_FOREACH(sec, &bus->child, sibling) { 523 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn); 524 if (pci_bus_is_root(sec)) { 525 continue; 526 } 527 nr_notifiers = nr_notifiers + 528 build_append_notfication_callback(br_scope, sec); 529 /* 530 * add new child scope to parent 531 * and keep track of bus that have PCNT, 532 * bus list is used later to call children PCNTs from this level PCNT 533 */ 534 if (nr_notifiers) { 535 g_queue_push_tail(pcnt_bus_list, sec); 536 aml_append(parent_scope, br_scope); 537 } 538 } 539 540 /* 541 * Append PCNT method to notify about events on local and child buses. 542 * ps: hostbridge might not have hotplug (bsel) enabled but might have 543 * child bridges that do have bsel. 544 */ 545 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 546 547 /* If bus supports hotplug select it and notify about local events */ 548 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 549 if (bsel) { 550 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 551 552 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 553 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 554 aml_int(1))); /* Device Check */ 555 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 556 aml_int(3))); /* Eject Request */ 557 nr_notifiers++; 558 } 559 560 /* Notify about child bus events in any case */ 561 while ((sec = g_queue_pop_head(pcnt_bus_list))) { 562 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn)); 563 } 564 565 aml_append(parent_scope, method); 566 qobject_unref(bsel); 567 g_queue_free(pcnt_bus_list); 568 return !!nr_notifiers; 569 } 570 571 static Aml *aml_pci_pdsm(void) 572 { 573 Aml *method, *UUID, *ifctx, *ifctx1; 574 Aml *ret = aml_local(0); 575 Aml *caps = aml_local(1); 576 Aml *acpi_index = aml_local(2); 577 Aml *zero = aml_int(0); 578 Aml *one = aml_int(1); 579 Aml *func = aml_arg(2); 580 Aml *rev = aml_arg(1); 581 Aml *params = aml_arg(4); 582 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 583 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 584 585 method = aml_method("PDSM", 5, AML_SERIALIZED); 586 587 /* get supported functions */ 588 ifctx = aml_if(aml_equal(func, zero)); 589 { 590 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 591 aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret)); 592 aml_append(ifctx, aml_store(zero, caps)); 593 594 /* 595 * PCI Firmware Specification 3.1 596 * 4.6. _DSM Definitions for PCI 597 */ 598 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 599 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 600 { 601 /* call is for unsupported UUID, bail out */ 602 aml_append(ifctx1, aml_return(ret)); 603 } 604 aml_append(ifctx, ifctx1); 605 606 ifctx1 = aml_if(aml_lless(rev, aml_int(2))); 607 { 608 /* call is for unsupported REV, bail out */ 609 aml_append(ifctx1, aml_return(ret)); 610 } 611 aml_append(ifctx, ifctx1); 612 613 aml_append(ifctx, 614 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 615 /* 616 * advertise function 7 if device has acpi-index 617 * acpi_index values: 618 * 0: not present (default value) 619 * FFFFFFFF: not supported (old QEMU without PIDX reg) 620 * other: device's acpi-index 621 */ 622 ifctx1 = aml_if(aml_lnot( 623 aml_or(aml_equal(acpi_index, zero), 624 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 625 )); 626 { 627 /* have supported functions */ 628 aml_append(ifctx1, aml_or(caps, one, caps)); 629 /* support for function 7 */ 630 aml_append(ifctx1, 631 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 632 } 633 aml_append(ifctx, ifctx1); 634 635 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 636 aml_append(ifctx, aml_return(ret)); 637 } 638 aml_append(method, ifctx); 639 640 /* handle specific functions requests */ 641 /* 642 * PCI Firmware Specification 3.1 643 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 644 * Operating Systems 645 */ 646 ifctx = aml_if(aml_equal(func, aml_int(7))); 647 { 648 Aml *pkg = aml_package(2); 649 650 aml_append(pkg, zero); 651 /* 652 * optional, if not impl. should return null string 653 */ 654 aml_append(pkg, aml_string("%s", "")); 655 aml_append(ifctx, aml_store(pkg, ret)); 656 657 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 658 /* 659 * update acpi-index to actual value 660 */ 661 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); 662 aml_append(ifctx, aml_return(ret)); 663 } 664 665 aml_append(method, ifctx); 666 return method; 667 } 668 669 /** 670 * build_prt_entry: 671 * @link_name: link name for PCI route entry 672 * 673 * build AML package containing a PCI route entry for @link_name 674 */ 675 static Aml *build_prt_entry(const char *link_name) 676 { 677 Aml *a_zero = aml_int(0); 678 Aml *pkg = aml_package(4); 679 aml_append(pkg, a_zero); 680 aml_append(pkg, a_zero); 681 aml_append(pkg, aml_name("%s", link_name)); 682 aml_append(pkg, a_zero); 683 return pkg; 684 } 685 686 /* 687 * initialize_route - Initialize the interrupt routing rule 688 * through a specific LINK: 689 * if (lnk_idx == idx) 690 * route using link 'link_name' 691 */ 692 static Aml *initialize_route(Aml *route, const char *link_name, 693 Aml *lnk_idx, int idx) 694 { 695 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 696 Aml *pkg = build_prt_entry(link_name); 697 698 aml_append(if_ctx, aml_store(pkg, route)); 699 700 return if_ctx; 701 } 702 703 /* 704 * build_prt - Define interrupt rounting rules 705 * 706 * Returns an array of 128 routes, one for each device, 707 * based on device location. 708 * The main goal is to equaly distribute the interrupts 709 * over the 4 existing ACPI links (works only for i440fx). 710 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 711 * 712 */ 713 static Aml *build_prt(bool is_pci0_prt) 714 { 715 Aml *method, *while_ctx, *pin, *res; 716 717 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 718 res = aml_local(0); 719 pin = aml_local(1); 720 aml_append(method, aml_store(aml_package(128), res)); 721 aml_append(method, aml_store(aml_int(0), pin)); 722 723 /* while (pin < 128) */ 724 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 725 { 726 Aml *slot = aml_local(2); 727 Aml *lnk_idx = aml_local(3); 728 Aml *route = aml_local(4); 729 730 /* slot = pin >> 2 */ 731 aml_append(while_ctx, 732 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 733 /* lnk_idx = (slot + pin) & 3 */ 734 aml_append(while_ctx, 735 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 736 lnk_idx)); 737 738 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 739 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 740 if (is_pci0_prt) { 741 Aml *if_device_1, *if_pin_4, *else_pin_4; 742 743 /* device 1 is the power-management device, needs SCI */ 744 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 745 { 746 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 747 { 748 aml_append(if_pin_4, 749 aml_store(build_prt_entry("LNKS"), route)); 750 } 751 aml_append(if_device_1, if_pin_4); 752 else_pin_4 = aml_else(); 753 { 754 aml_append(else_pin_4, 755 aml_store(build_prt_entry("LNKA"), route)); 756 } 757 aml_append(if_device_1, else_pin_4); 758 } 759 aml_append(while_ctx, if_device_1); 760 } else { 761 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 762 } 763 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 764 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 765 766 /* route[0] = 0x[slot]FFFF */ 767 aml_append(while_ctx, 768 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 769 NULL), 770 aml_index(route, aml_int(0)))); 771 /* route[1] = pin & 3 */ 772 aml_append(while_ctx, 773 aml_store(aml_and(pin, aml_int(3), NULL), 774 aml_index(route, aml_int(1)))); 775 /* res[pin] = route */ 776 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 777 /* pin++ */ 778 aml_append(while_ctx, aml_increment(pin)); 779 } 780 aml_append(method, while_ctx); 781 /* return res*/ 782 aml_append(method, aml_return(res)); 783 784 return method; 785 } 786 787 static void build_hpet_aml(Aml *table) 788 { 789 Aml *crs; 790 Aml *field; 791 Aml *method; 792 Aml *if_ctx; 793 Aml *scope = aml_scope("_SB"); 794 Aml *dev = aml_device("HPET"); 795 Aml *zero = aml_int(0); 796 Aml *id = aml_local(0); 797 Aml *period = aml_local(1); 798 799 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 800 aml_append(dev, aml_name_decl("_UID", zero)); 801 802 aml_append(dev, 803 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 804 HPET_LEN)); 805 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 806 aml_append(field, aml_named_field("VEND", 32)); 807 aml_append(field, aml_named_field("PRD", 32)); 808 aml_append(dev, field); 809 810 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 811 aml_append(method, aml_store(aml_name("VEND"), id)); 812 aml_append(method, aml_store(aml_name("PRD"), period)); 813 aml_append(method, aml_shiftright(id, aml_int(16), id)); 814 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 815 aml_equal(id, aml_int(0xffff)))); 816 { 817 aml_append(if_ctx, aml_return(zero)); 818 } 819 aml_append(method, if_ctx); 820 821 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 822 aml_lgreater(period, aml_int(100000000)))); 823 { 824 aml_append(if_ctx, aml_return(zero)); 825 } 826 aml_append(method, if_ctx); 827 828 aml_append(method, aml_return(aml_int(0x0F))); 829 aml_append(dev, method); 830 831 crs = aml_resource_template(); 832 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 833 aml_append(dev, aml_name_decl("_CRS", crs)); 834 835 aml_append(scope, dev); 836 aml_append(table, scope); 837 } 838 839 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 840 { 841 Aml *dev; 842 Aml *method; 843 Aml *crs; 844 845 dev = aml_device("VMBS"); 846 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 847 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 848 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 849 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 850 851 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 852 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 853 aml_name("STA"))); 854 aml_append(dev, method); 855 856 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 857 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 858 aml_name("STA"))); 859 aml_append(dev, method); 860 861 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 862 aml_append(method, aml_return(aml_name("STA"))); 863 aml_append(dev, method); 864 865 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 866 867 crs = aml_resource_template(); 868 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 869 aml_append(dev, aml_name_decl("_CRS", crs)); 870 871 return dev; 872 } 873 874 static void build_dbg_aml(Aml *table) 875 { 876 Aml *field; 877 Aml *method; 878 Aml *while_ctx; 879 Aml *scope = aml_scope("\\"); 880 Aml *buf = aml_local(0); 881 Aml *len = aml_local(1); 882 Aml *idx = aml_local(2); 883 884 aml_append(scope, 885 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 886 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 887 aml_append(field, aml_named_field("DBGB", 8)); 888 aml_append(scope, field); 889 890 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 891 892 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 893 aml_append(method, aml_to_buffer(buf, buf)); 894 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 895 aml_append(method, aml_store(aml_int(0), idx)); 896 897 while_ctx = aml_while(aml_lless(idx, len)); 898 aml_append(while_ctx, 899 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 900 aml_append(while_ctx, aml_increment(idx)); 901 aml_append(method, while_ctx); 902 903 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 904 aml_append(scope, method); 905 906 aml_append(table, scope); 907 } 908 909 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 910 { 911 Aml *dev; 912 Aml *crs; 913 Aml *method; 914 uint32_t irqs[] = {5, 10, 11}; 915 916 dev = aml_device("%s", name); 917 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 918 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 919 920 crs = aml_resource_template(); 921 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 922 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 923 aml_append(dev, aml_name_decl("_PRS", crs)); 924 925 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 926 aml_append(method, aml_return(aml_call1("IQST", reg))); 927 aml_append(dev, method); 928 929 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 930 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 931 aml_append(dev, method); 932 933 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 934 aml_append(method, aml_return(aml_call1("IQCR", reg))); 935 aml_append(dev, method); 936 937 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 938 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 939 aml_append(method, aml_store(aml_name("PRRI"), reg)); 940 aml_append(dev, method); 941 942 return dev; 943 } 944 945 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 946 { 947 Aml *dev; 948 Aml *crs; 949 Aml *method; 950 uint32_t irqs; 951 952 dev = aml_device("%s", name); 953 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 954 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 955 956 crs = aml_resource_template(); 957 irqs = gsi; 958 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 959 AML_SHARED, &irqs, 1)); 960 aml_append(dev, aml_name_decl("_PRS", crs)); 961 962 aml_append(dev, aml_name_decl("_CRS", crs)); 963 964 /* 965 * _DIS can be no-op because the interrupt cannot be disabled. 966 */ 967 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 968 aml_append(dev, method); 969 970 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 971 aml_append(dev, method); 972 973 return dev; 974 } 975 976 /* _CRS method - get current settings */ 977 static Aml *build_iqcr_method(bool is_piix4) 978 { 979 Aml *if_ctx; 980 uint32_t irqs; 981 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 982 Aml *crs = aml_resource_template(); 983 984 irqs = 0; 985 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 986 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 987 aml_append(method, aml_name_decl("PRR0", crs)); 988 989 aml_append(method, 990 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 991 992 if (is_piix4) { 993 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 994 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 995 aml_append(method, if_ctx); 996 } else { 997 aml_append(method, 998 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 999 aml_name("PRRI"))); 1000 } 1001 1002 aml_append(method, aml_return(aml_name("PRR0"))); 1003 return method; 1004 } 1005 1006 /* _STA method - get status */ 1007 static Aml *build_irq_status_method(void) 1008 { 1009 Aml *if_ctx; 1010 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1011 1012 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1013 aml_append(if_ctx, aml_return(aml_int(0x09))); 1014 aml_append(method, if_ctx); 1015 aml_append(method, aml_return(aml_int(0x0B))); 1016 return method; 1017 } 1018 1019 static void build_piix4_pci0_int(Aml *table) 1020 { 1021 Aml *dev; 1022 Aml *crs; 1023 Aml *method; 1024 uint32_t irqs; 1025 Aml *sb_scope = aml_scope("_SB"); 1026 Aml *pci0_scope = aml_scope("PCI0"); 1027 1028 aml_append(pci0_scope, build_prt(true)); 1029 aml_append(sb_scope, pci0_scope); 1030 1031 aml_append(sb_scope, build_irq_status_method()); 1032 aml_append(sb_scope, build_iqcr_method(true)); 1033 1034 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1035 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1036 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1037 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1038 1039 dev = aml_device("LNKS"); 1040 { 1041 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1042 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1043 1044 crs = aml_resource_template(); 1045 irqs = 9; 1046 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1047 AML_ACTIVE_HIGH, AML_SHARED, 1048 &irqs, 1)); 1049 aml_append(dev, aml_name_decl("_PRS", crs)); 1050 1051 /* The SCI cannot be disabled and is always attached to GSI 9, 1052 * so these are no-ops. We only need this link to override the 1053 * polarity to active high and match the content of the MADT. 1054 */ 1055 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1056 aml_append(method, aml_return(aml_int(0x0b))); 1057 aml_append(dev, method); 1058 1059 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1060 aml_append(dev, method); 1061 1062 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1063 aml_append(method, aml_return(aml_name("_PRS"))); 1064 aml_append(dev, method); 1065 1066 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1067 aml_append(dev, method); 1068 } 1069 aml_append(sb_scope, dev); 1070 1071 aml_append(table, sb_scope); 1072 } 1073 1074 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1075 { 1076 int i; 1077 int head; 1078 Aml *pkg; 1079 char base = name[3] < 'E' ? 'A' : 'E'; 1080 char *s = g_strdup(name); 1081 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1082 1083 assert(strlen(s) == 4); 1084 1085 head = name[3] - base; 1086 for (i = 0; i < 4; i++) { 1087 if (head + i > 3) { 1088 head = i * -1; 1089 } 1090 s[3] = base + head + i; 1091 pkg = aml_package(4); 1092 aml_append(pkg, a_nr); 1093 aml_append(pkg, aml_int(i)); 1094 aml_append(pkg, aml_name("%s", s)); 1095 aml_append(pkg, aml_int(0)); 1096 aml_append(ctx, pkg); 1097 } 1098 g_free(s); 1099 } 1100 1101 static Aml *build_q35_routing_table(const char *str) 1102 { 1103 int i; 1104 Aml *pkg; 1105 char *name = g_strdup_printf("%s ", str); 1106 1107 pkg = aml_package(128); 1108 for (i = 0; i < 0x18; i++) { 1109 name[3] = 'E' + (i & 0x3); 1110 append_q35_prt_entry(pkg, i, name); 1111 } 1112 1113 name[3] = 'E'; 1114 append_q35_prt_entry(pkg, 0x18, name); 1115 1116 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1117 for (i = 0x0019; i < 0x1e; i++) { 1118 name[3] = 'A'; 1119 append_q35_prt_entry(pkg, i, name); 1120 } 1121 1122 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1123 name[3] = 'E'; 1124 append_q35_prt_entry(pkg, 0x1e, name); 1125 name[3] = 'A'; 1126 append_q35_prt_entry(pkg, 0x1f, name); 1127 1128 g_free(name); 1129 return pkg; 1130 } 1131 1132 static void build_q35_pci0_int(Aml *table) 1133 { 1134 Aml *method; 1135 Aml *sb_scope = aml_scope("_SB"); 1136 Aml *pci0_scope = aml_scope("PCI0"); 1137 1138 /* Zero => PIC mode, One => APIC Mode */ 1139 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1140 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1141 { 1142 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1143 } 1144 aml_append(table, method); 1145 1146 aml_append(pci0_scope, 1147 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1148 aml_append(pci0_scope, 1149 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1150 1151 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1152 { 1153 Aml *if_ctx; 1154 Aml *else_ctx; 1155 1156 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1157 section 6.2.8.1 */ 1158 /* Note: we provide the same info as the PCI routing 1159 table of the Bochs BIOS */ 1160 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1161 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1162 aml_append(method, if_ctx); 1163 else_ctx = aml_else(); 1164 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1165 aml_append(method, else_ctx); 1166 } 1167 aml_append(pci0_scope, method); 1168 aml_append(sb_scope, pci0_scope); 1169 1170 aml_append(sb_scope, build_irq_status_method()); 1171 aml_append(sb_scope, build_iqcr_method(false)); 1172 1173 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1174 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1175 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1176 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1177 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1178 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1179 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1180 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1181 1182 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1183 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1184 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1185 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1186 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1187 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1188 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1189 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1190 1191 aml_append(table, sb_scope); 1192 } 1193 1194 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1195 { 1196 Aml *dev; 1197 Aml *resource_template; 1198 1199 /* DRAM controller */ 1200 dev = aml_device("DRAC"); 1201 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1202 1203 resource_template = aml_resource_template(); 1204 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1205 aml_append(resource_template, 1206 aml_qword_memory(AML_POS_DECODE, 1207 AML_MIN_FIXED, 1208 AML_MAX_FIXED, 1209 AML_NON_CACHEABLE, 1210 AML_READ_WRITE, 1211 0x0000000000000000, 1212 mcfg->base, 1213 mcfg->base + mcfg->size - 1, 1214 0x0000000000000000, 1215 mcfg->size)); 1216 } else { 1217 aml_append(resource_template, 1218 aml_dword_memory(AML_POS_DECODE, 1219 AML_MIN_FIXED, 1220 AML_MAX_FIXED, 1221 AML_NON_CACHEABLE, 1222 AML_READ_WRITE, 1223 0x0000000000000000, 1224 mcfg->base, 1225 mcfg->base + mcfg->size - 1, 1226 0x0000000000000000, 1227 mcfg->size)); 1228 } 1229 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1230 1231 return dev; 1232 } 1233 1234 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1235 { 1236 Aml *scope; 1237 Aml *field; 1238 Aml *method; 1239 1240 scope = aml_scope("_SB.PCI0"); 1241 1242 aml_append(scope, 1243 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1244 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1245 aml_append(field, aml_named_field("PCIU", 32)); 1246 aml_append(field, aml_named_field("PCID", 32)); 1247 aml_append(scope, field); 1248 1249 aml_append(scope, 1250 aml_operation_region("SEJ", AML_SYSTEM_IO, 1251 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1252 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1253 aml_append(field, aml_named_field("B0EJ", 32)); 1254 aml_append(scope, field); 1255 1256 aml_append(scope, 1257 aml_operation_region("BNMR", AML_SYSTEM_IO, 1258 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1259 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1260 aml_append(field, aml_named_field("BNUM", 32)); 1261 aml_append(field, aml_named_field("PIDX", 32)); 1262 aml_append(scope, field); 1263 1264 aml_append(scope, aml_mutex("BLCK", 0)); 1265 1266 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1267 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1268 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1269 aml_append(method, 1270 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1271 aml_append(method, aml_release(aml_name("BLCK"))); 1272 aml_append(method, aml_return(aml_int(0))); 1273 aml_append(scope, method); 1274 1275 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1276 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1277 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1278 aml_append(method, 1279 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1280 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1281 aml_append(method, aml_release(aml_name("BLCK"))); 1282 aml_append(method, aml_return(aml_local(0))); 1283 aml_append(scope, method); 1284 1285 aml_append(scope, aml_pci_pdsm()); 1286 1287 aml_append(table, scope); 1288 } 1289 1290 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1291 { 1292 Aml *if_ctx; 1293 Aml *if_ctx2; 1294 Aml *else_ctx; 1295 Aml *method; 1296 Aml *a_cwd1 = aml_name("CDW1"); 1297 Aml *a_ctrl = aml_local(0); 1298 1299 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1300 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1301 1302 if_ctx = aml_if(aml_equal( 1303 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1304 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1305 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1306 1307 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1308 1309 /* 1310 * Always allow native PME, AER (no dependencies) 1311 * Allow SHPC (PCI bridges can have SHPC controller) 1312 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1313 */ 1314 aml_append(if_ctx, aml_and(a_ctrl, 1315 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1316 1317 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1318 /* Unknown revision */ 1319 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1320 aml_append(if_ctx, if_ctx2); 1321 1322 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1323 /* Capabilities bits were masked */ 1324 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1325 aml_append(if_ctx, if_ctx2); 1326 1327 /* Update DWORD3 in the buffer */ 1328 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1329 aml_append(method, if_ctx); 1330 1331 else_ctx = aml_else(); 1332 /* Unrecognized UUID */ 1333 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1334 aml_append(method, else_ctx); 1335 1336 aml_append(method, aml_return(aml_arg(3))); 1337 return method; 1338 } 1339 1340 static void build_acpi0017(Aml *table) 1341 { 1342 Aml *dev, *scope, *method; 1343 1344 scope = aml_scope("_SB"); 1345 dev = aml_device("CXLM"); 1346 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1347 1348 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1349 aml_append(method, aml_return(aml_int(0x01))); 1350 aml_append(dev, method); 1351 1352 aml_append(scope, dev); 1353 aml_append(table, scope); 1354 } 1355 1356 static void 1357 build_dsdt(GArray *table_data, BIOSLinker *linker, 1358 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1359 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1360 { 1361 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); 1362 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); 1363 CrsRangeEntry *entry; 1364 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1365 CrsRangeSet crs_range_set; 1366 PCMachineState *pcms = PC_MACHINE(machine); 1367 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1368 X86MachineState *x86ms = X86_MACHINE(machine); 1369 AcpiMcfgInfo mcfg; 1370 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1371 uint32_t nr_mem = machine->ram_slots; 1372 int root_bus_limit = 0xFF; 1373 PCIBus *bus = NULL; 1374 #ifdef CONFIG_TPM 1375 TPMIf *tpm = tpm_find(); 1376 #endif 1377 bool cxl_present = false; 1378 int i; 1379 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1380 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1381 .oem_table_id = x86ms->oem_table_id }; 1382 1383 assert(!!i440fx != !!q35); 1384 1385 acpi_table_begin(&table, table_data); 1386 dsdt = init_aml_allocator(); 1387 1388 build_dbg_aml(dsdt); 1389 if (i440fx) { 1390 sb_scope = aml_scope("_SB"); 1391 dev = aml_device("PCI0"); 1392 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1393 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1394 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1395 aml_append(sb_scope, dev); 1396 aml_append(dsdt, sb_scope); 1397 1398 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1399 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1400 } 1401 build_piix4_pci0_int(dsdt); 1402 } else if (q35) { 1403 sb_scope = aml_scope("_SB"); 1404 dev = aml_device("PCI0"); 1405 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1406 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1407 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1408 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1409 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1410 aml_append(sb_scope, dev); 1411 if (mcfg_valid) { 1412 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1413 } 1414 1415 if (pm->smi_on_cpuhp) { 1416 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1417 dev = aml_device("PCI0.SMI0"); 1418 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1419 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1420 crs = aml_resource_template(); 1421 aml_append(crs, 1422 aml_io( 1423 AML_DECODE16, 1424 ACPI_PORT_SMI_CMD, 1425 ACPI_PORT_SMI_CMD, 1426 1, 1427 2) 1428 ); 1429 aml_append(dev, aml_name_decl("_CRS", crs)); 1430 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1431 aml_int(ACPI_PORT_SMI_CMD), 2)); 1432 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1433 AML_WRITE_AS_ZEROS); 1434 aml_append(field, aml_named_field("SMIC", 8)); 1435 aml_append(field, aml_reserved_field(8)); 1436 aml_append(dev, field); 1437 aml_append(sb_scope, dev); 1438 } 1439 1440 aml_append(dsdt, sb_scope); 1441 1442 if (pm->pcihp_bridge_en) { 1443 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1444 } 1445 build_q35_pci0_int(dsdt); 1446 } 1447 1448 if (misc->has_hpet) { 1449 build_hpet_aml(dsdt); 1450 } 1451 1452 if (vmbus_bridge) { 1453 sb_scope = aml_scope("_SB"); 1454 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1455 aml_append(dsdt, sb_scope); 1456 } 1457 1458 scope = aml_scope("_GPE"); 1459 { 1460 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1461 if (machine->nvdimms_state->is_enabled) { 1462 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1463 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1464 aml_int(0x80))); 1465 aml_append(scope, method); 1466 } 1467 } 1468 aml_append(dsdt, scope); 1469 1470 if (pcmc->legacy_cpu_hotplug) { 1471 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1472 } else { 1473 CPUHotplugFeatures opts = { 1474 .acpi_1_compatible = true, .has_legacy_cphp = true, 1475 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1476 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1477 }; 1478 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1479 "\\_SB.PCI0", "\\_GPE._E02"); 1480 } 1481 1482 if (pcms->memhp_io_base && nr_mem) { 1483 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1484 "\\_GPE._E03", AML_SYSTEM_IO, 1485 pcms->memhp_io_base); 1486 } 1487 1488 crs_range_set_init(&crs_range_set); 1489 bus = PC_MACHINE(machine)->bus; 1490 if (bus) { 1491 QLIST_FOREACH(bus, &bus->child, sibling) { 1492 uint8_t bus_num = pci_bus_num(bus); 1493 uint8_t numa_node = pci_bus_numa_node(bus); 1494 1495 /* look only for expander root buses */ 1496 if (!pci_bus_is_root(bus)) { 1497 continue; 1498 } 1499 1500 if (bus_num < root_bus_limit) { 1501 root_bus_limit = bus_num - 1; 1502 } 1503 1504 scope = aml_scope("\\_SB"); 1505 1506 if (pci_bus_is_cxl(bus)) { 1507 dev = aml_device("CL%.02X", bus_num); 1508 } else { 1509 dev = aml_device("PC%.02X", bus_num); 1510 } 1511 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1512 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1513 if (pci_bus_is_cxl(bus)) { 1514 struct Aml *pkg = aml_package(2); 1515 1516 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1517 aml_append(pkg, aml_eisaid("PNP0A08")); 1518 aml_append(pkg, aml_eisaid("PNP0A03")); 1519 aml_append(dev, aml_name_decl("_CID", pkg)); 1520 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1521 build_cxl_osc_method(dev); 1522 } else if (pci_bus_is_express(bus)) { 1523 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1524 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1525 1526 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1527 aml_append(dev, build_q35_osc_method(true)); 1528 } else { 1529 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1530 } 1531 1532 if (numa_node != NUMA_NODE_UNASSIGNED) { 1533 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1534 } 1535 1536 aml_append(dev, build_prt(false)); 1537 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1538 0, 0, 0, 0); 1539 aml_append(dev, aml_name_decl("_CRS", crs)); 1540 aml_append(scope, dev); 1541 aml_append(dsdt, scope); 1542 1543 /* Handle the ranges for the PXB expanders */ 1544 if (pci_bus_is_cxl(bus)) { 1545 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1546 uint64_t base = mr->addr; 1547 1548 cxl_present = true; 1549 crs_range_insert(crs_range_set.mem_ranges, base, 1550 base + memory_region_size(mr) - 1); 1551 } 1552 } 1553 } 1554 1555 if (cxl_present) { 1556 build_acpi0017(dsdt); 1557 } 1558 1559 /* 1560 * At this point crs_range_set has all the ranges used by pci 1561 * busses *other* than PCI0. These ranges will be excluded from 1562 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1563 * too. 1564 */ 1565 if (mcfg_valid) { 1566 crs_range_insert(crs_range_set.mem_ranges, 1567 mcfg.base, mcfg.base + mcfg.size - 1); 1568 } 1569 1570 scope = aml_scope("\\_SB.PCI0"); 1571 /* build PCI0._CRS */ 1572 crs = aml_resource_template(); 1573 aml_append(crs, 1574 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1575 0x0000, 0x0, root_bus_limit, 1576 0x0000, root_bus_limit + 1)); 1577 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1578 1579 aml_append(crs, 1580 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1581 AML_POS_DECODE, AML_ENTIRE_RANGE, 1582 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1583 1584 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1585 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1586 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1587 aml_append(crs, 1588 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1589 AML_POS_DECODE, AML_ENTIRE_RANGE, 1590 0x0000, entry->base, entry->limit, 1591 0x0000, entry->limit - entry->base + 1)); 1592 } 1593 1594 aml_append(crs, 1595 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1596 AML_CACHEABLE, AML_READ_WRITE, 1597 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1598 1599 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1600 range_lob(pci_hole), 1601 range_upb(pci_hole)); 1602 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1603 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1604 aml_append(crs, 1605 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1606 AML_NON_CACHEABLE, AML_READ_WRITE, 1607 0, entry->base, entry->limit, 1608 0, entry->limit - entry->base + 1)); 1609 } 1610 1611 if (!range_is_empty(pci_hole64)) { 1612 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1613 range_lob(pci_hole64), 1614 range_upb(pci_hole64)); 1615 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1616 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1617 aml_append(crs, 1618 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1619 AML_MAX_FIXED, 1620 AML_CACHEABLE, AML_READ_WRITE, 1621 0, entry->base, entry->limit, 1622 0, entry->limit - entry->base + 1)); 1623 } 1624 } 1625 1626 #ifdef CONFIG_TPM 1627 if (TPM_IS_TIS_ISA(tpm_find())) { 1628 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1629 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1630 } 1631 #endif 1632 aml_append(scope, aml_name_decl("_CRS", crs)); 1633 1634 /* reserve GPE0 block resources */ 1635 dev = aml_device("GPE0"); 1636 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1637 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1638 /* device present, functioning, decoding, not shown in UI */ 1639 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1640 crs = aml_resource_template(); 1641 aml_append(crs, 1642 aml_io( 1643 AML_DECODE16, 1644 pm->fadt.gpe0_blk.address, 1645 pm->fadt.gpe0_blk.address, 1646 1, 1647 pm->fadt.gpe0_blk.bit_width / 8) 1648 ); 1649 aml_append(dev, aml_name_decl("_CRS", crs)); 1650 aml_append(scope, dev); 1651 1652 crs_range_set_free(&crs_range_set); 1653 1654 /* reserve PCIHP resources */ 1655 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1656 dev = aml_device("PHPR"); 1657 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1658 aml_append(dev, 1659 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1660 /* device present, functioning, decoding, not shown in UI */ 1661 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1662 crs = aml_resource_template(); 1663 aml_append(crs, 1664 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1665 pm->pcihp_io_len) 1666 ); 1667 aml_append(dev, aml_name_decl("_CRS", crs)); 1668 aml_append(scope, dev); 1669 } 1670 aml_append(dsdt, scope); 1671 1672 /* create S3_ / S4_ / S5_ packages if necessary */ 1673 scope = aml_scope("\\"); 1674 if (!pm->s3_disabled) { 1675 pkg = aml_package(4); 1676 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1677 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1678 aml_append(pkg, aml_int(0)); /* reserved */ 1679 aml_append(pkg, aml_int(0)); /* reserved */ 1680 aml_append(scope, aml_name_decl("_S3", pkg)); 1681 } 1682 1683 if (!pm->s4_disabled) { 1684 pkg = aml_package(4); 1685 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1686 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1687 aml_append(pkg, aml_int(pm->s4_val)); 1688 aml_append(pkg, aml_int(0)); /* reserved */ 1689 aml_append(pkg, aml_int(0)); /* reserved */ 1690 aml_append(scope, aml_name_decl("_S4", pkg)); 1691 } 1692 1693 pkg = aml_package(4); 1694 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1695 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1696 aml_append(pkg, aml_int(0)); /* reserved */ 1697 aml_append(pkg, aml_int(0)); /* reserved */ 1698 aml_append(scope, aml_name_decl("_S5", pkg)); 1699 aml_append(dsdt, scope); 1700 1701 /* create fw_cfg node, unconditionally */ 1702 { 1703 scope = aml_scope("\\_SB.PCI0"); 1704 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1705 aml_append(dsdt, scope); 1706 } 1707 1708 sb_scope = aml_scope("\\_SB"); 1709 { 1710 Object *pci_host = acpi_get_i386_pci_host(); 1711 1712 if (pci_host) { 1713 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1714 Aml *scope = aml_scope("PCI0"); 1715 /* Scan all PCI buses. Generate tables to support hotplug. */ 1716 build_append_pci_bus_devices(scope, bus); 1717 aml_append(sb_scope, scope); 1718 } 1719 } 1720 1721 #ifdef CONFIG_TPM 1722 if (TPM_IS_CRB(tpm)) { 1723 dev = aml_device("TPM"); 1724 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1725 aml_append(dev, aml_name_decl("_STR", 1726 aml_string("TPM 2.0 Device"))); 1727 crs = aml_resource_template(); 1728 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1729 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1730 aml_append(dev, aml_name_decl("_CRS", crs)); 1731 1732 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1733 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1734 1735 tpm_build_ppi_acpi(tpm, dev); 1736 1737 aml_append(sb_scope, dev); 1738 } 1739 #endif 1740 1741 if (pcms->sgx_epc.size != 0) { 1742 uint64_t epc_base = pcms->sgx_epc.base; 1743 uint64_t epc_size = pcms->sgx_epc.size; 1744 1745 dev = aml_device("EPC"); 1746 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1747 aml_append(dev, aml_name_decl("_STR", 1748 aml_unicode("Enclave Page Cache 1.0"))); 1749 crs = aml_resource_template(); 1750 aml_append(crs, 1751 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1752 AML_MAX_FIXED, AML_NON_CACHEABLE, 1753 AML_READ_WRITE, 0, epc_base, 1754 epc_base + epc_size - 1, 0, epc_size)); 1755 aml_append(dev, aml_name_decl("_CRS", crs)); 1756 1757 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1758 aml_append(method, aml_return(aml_int(0x0f))); 1759 aml_append(dev, method); 1760 1761 aml_append(sb_scope, dev); 1762 } 1763 aml_append(dsdt, sb_scope); 1764 1765 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1766 bool has_pcnt; 1767 1768 Object *pci_host = acpi_get_i386_pci_host(); 1769 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1770 1771 scope = aml_scope("\\_SB.PCI0"); 1772 has_pcnt = build_append_notfication_callback(scope, bus); 1773 if (has_pcnt) { 1774 aml_append(dsdt, scope); 1775 } 1776 1777 scope = aml_scope("_GPE"); 1778 { 1779 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1780 if (has_pcnt) { 1781 aml_append(method, 1782 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1783 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1784 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1785 } 1786 aml_append(scope, method); 1787 } 1788 aml_append(dsdt, scope); 1789 } 1790 1791 /* copy AML table into ACPI tables blob and patch header there */ 1792 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1793 acpi_table_end(linker, &table); 1794 free_aml_allocator(); 1795 } 1796 1797 /* 1798 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1799 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1800 */ 1801 static void 1802 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1803 const char *oem_table_id) 1804 { 1805 AcpiTable table = { .sig = "HPET", .rev = 1, 1806 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1807 1808 acpi_table_begin(&table, table_data); 1809 /* Note timer_block_id value must be kept in sync with value advertised by 1810 * emulated hpet 1811 */ 1812 /* Event Timer Block ID */ 1813 build_append_int_noprefix(table_data, 0x8086a201, 4); 1814 /* BASE_ADDRESS */ 1815 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1816 /* HPET Number */ 1817 build_append_int_noprefix(table_data, 0, 1); 1818 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1819 build_append_int_noprefix(table_data, 0, 2); 1820 /* Page Protection And OEM Attribute */ 1821 build_append_int_noprefix(table_data, 0, 1); 1822 acpi_table_end(linker, &table); 1823 } 1824 1825 #ifdef CONFIG_TPM 1826 /* 1827 * TCPA Description Table 1828 * 1829 * Following Level 00, Rev 00.37 of specs: 1830 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1831 * 7.1.2 ACPI Table Layout 1832 */ 1833 static void 1834 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1835 const char *oem_id, const char *oem_table_id) 1836 { 1837 unsigned log_addr_offset; 1838 AcpiTable table = { .sig = "TCPA", .rev = 2, 1839 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1840 1841 acpi_table_begin(&table, table_data); 1842 /* Platform Class */ 1843 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1844 /* Log Area Minimum Length (LAML) */ 1845 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1846 /* Log Area Start Address (LASA) */ 1847 log_addr_offset = table_data->len; 1848 build_append_int_noprefix(table_data, 0, 8); 1849 1850 /* allocate/reserve space for TPM log area */ 1851 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1852 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1853 false /* high memory */); 1854 /* log area start address to be filled by Guest linker */ 1855 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1856 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1857 1858 acpi_table_end(linker, &table); 1859 } 1860 #endif 1861 1862 #define HOLE_640K_START (640 * KiB) 1863 #define HOLE_640K_END (1 * MiB) 1864 1865 /* 1866 * ACPI spec, Revision 3.0 1867 * 5.2.15 System Resource Affinity Table (SRAT) 1868 */ 1869 static void 1870 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1871 { 1872 int i; 1873 int numa_mem_start, slots; 1874 uint64_t mem_len, mem_base, next_base; 1875 MachineClass *mc = MACHINE_GET_CLASS(machine); 1876 X86MachineState *x86ms = X86_MACHINE(machine); 1877 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1878 PCMachineState *pcms = PC_MACHINE(machine); 1879 int nb_numa_nodes = machine->numa_state->num_nodes; 1880 NodeInfo *numa_info = machine->numa_state->nodes; 1881 ram_addr_t hotpluggable_address_space_size = 1882 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1883 NULL); 1884 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1885 .oem_table_id = x86ms->oem_table_id }; 1886 1887 acpi_table_begin(&table, table_data); 1888 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1889 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1890 1891 for (i = 0; i < apic_ids->len; i++) { 1892 int node_id = apic_ids->cpus[i].props.node_id; 1893 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1894 1895 if (apic_id < 255) { 1896 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1897 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1898 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1899 /* Proximity Domain [7:0] */ 1900 build_append_int_noprefix(table_data, node_id, 1); 1901 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1902 /* Flags, Table 5-36 */ 1903 build_append_int_noprefix(table_data, 1, 4); 1904 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1905 /* Proximity Domain [31:8] */ 1906 build_append_int_noprefix(table_data, 0, 3); 1907 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1908 } else { 1909 /* 1910 * ACPI spec, Revision 4.0 1911 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1912 */ 1913 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1914 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1915 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1916 /* Proximity Domain */ 1917 build_append_int_noprefix(table_data, node_id, 4); 1918 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1919 /* Flags, Table 5-39 */ 1920 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1921 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1922 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1923 } 1924 } 1925 1926 /* the memory map is a bit tricky, it contains at least one hole 1927 * from 640k-1M and possibly another one from 3.5G-4G. 1928 */ 1929 next_base = 0; 1930 numa_mem_start = table_data->len; 1931 1932 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1933 mem_base = next_base; 1934 mem_len = numa_info[i - 1].node_mem; 1935 next_base = mem_base + mem_len; 1936 1937 /* Cut out the 640K hole */ 1938 if (mem_base <= HOLE_640K_START && 1939 next_base > HOLE_640K_START) { 1940 mem_len -= next_base - HOLE_640K_START; 1941 if (mem_len > 0) { 1942 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1943 MEM_AFFINITY_ENABLED); 1944 } 1945 1946 /* Check for the rare case: 640K < RAM < 1M */ 1947 if (next_base <= HOLE_640K_END) { 1948 next_base = HOLE_640K_END; 1949 continue; 1950 } 1951 mem_base = HOLE_640K_END; 1952 mem_len = next_base - HOLE_640K_END; 1953 } 1954 1955 /* Cut out the ACPI_PCI hole */ 1956 if (mem_base <= x86ms->below_4g_mem_size && 1957 next_base > x86ms->below_4g_mem_size) { 1958 mem_len -= next_base - x86ms->below_4g_mem_size; 1959 if (mem_len > 0) { 1960 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1961 MEM_AFFINITY_ENABLED); 1962 } 1963 mem_base = x86ms->above_4g_mem_start; 1964 mem_len = next_base - x86ms->below_4g_mem_size; 1965 next_base = mem_base + mem_len; 1966 } 1967 1968 if (mem_len > 0) { 1969 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1970 MEM_AFFINITY_ENABLED); 1971 } 1972 } 1973 1974 if (machine->nvdimms_state->is_enabled) { 1975 nvdimm_build_srat(table_data); 1976 } 1977 1978 sgx_epc_build_srat(table_data); 1979 1980 /* 1981 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1982 * without these entries. But I recall there were issues the last time I 1983 * tried to remove it with some ancient guest OS, however I can't remember 1984 * what that was so keep this around for now 1985 */ 1986 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1987 for (; slots < nb_numa_nodes + 2; slots++) { 1988 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1989 } 1990 1991 /* 1992 * Entry is required for Windows to enable memory hotplug in OS 1993 * and for Linux to enable SWIOTLB when booted with less than 1994 * 4G of RAM. Windows works better if the entry sets proximity 1995 * to the highest NUMA node in the machine. 1996 * Memory devices may override proximity set by this entry, 1997 * providing _PXM method if necessary. 1998 */ 1999 if (hotpluggable_address_space_size) { 2000 build_srat_memory(table_data, machine->device_memory->base, 2001 hotpluggable_address_space_size, nb_numa_nodes - 1, 2002 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2003 } 2004 2005 acpi_table_end(linker, &table); 2006 } 2007 2008 /* 2009 * Insert DMAR scope for PCI bridges and endpoint devcie 2010 */ 2011 static void 2012 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2013 { 2014 const size_t device_scope_size = 6 /* device scope structure */ + 2015 2 /* 1 path entry */; 2016 GArray *scope_blob = opaque; 2017 2018 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2019 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2020 build_append_int_noprefix(scope_blob, 0x02, 1); 2021 } else { 2022 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2023 build_append_int_noprefix(scope_blob, 0x01, 1); 2024 } 2025 2026 /* length */ 2027 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2028 /* reserved */ 2029 build_append_int_noprefix(scope_blob, 0, 2); 2030 /* enumeration_id */ 2031 build_append_int_noprefix(scope_blob, 0, 1); 2032 /* bus */ 2033 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2034 /* device */ 2035 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2036 /* function */ 2037 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2038 } 2039 2040 /* For a given PCI host bridge, walk and insert DMAR scope */ 2041 static int 2042 dmar_host_bridges(Object *obj, void *opaque) 2043 { 2044 GArray *scope_blob = opaque; 2045 2046 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2047 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2048 2049 if (bus && !pci_bus_bypass_iommu(bus)) { 2050 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2051 } 2052 } 2053 2054 return 0; 2055 } 2056 2057 /* 2058 * Intel ® Virtualization Technology for Directed I/O 2059 * Architecture Specification. Revision 3.3 2060 * 8.1 DMA Remapping Reporting Structure 2061 */ 2062 static void 2063 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2064 const char *oem_table_id) 2065 { 2066 uint8_t dmar_flags = 0; 2067 uint8_t rsvd10[10] = {}; 2068 /* Root complex IOAPIC uses one path only */ 2069 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2070 2 /* 1 path entry */; 2071 X86IOMMUState *iommu = x86_iommu_get_default(); 2072 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2073 GArray *scope_blob = g_array_new(false, true, 1); 2074 2075 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2076 .oem_table_id = oem_table_id }; 2077 2078 /* 2079 * A PCI bus walk, for each PCI host bridge. 2080 * Insert scope for each PCI bridge and endpoint device which 2081 * is attached to a bus with iommu enabled. 2082 */ 2083 object_child_foreach_recursive(object_get_root(), 2084 dmar_host_bridges, scope_blob); 2085 2086 assert(iommu); 2087 if (x86_iommu_ir_supported(iommu)) { 2088 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2089 } 2090 2091 acpi_table_begin(&table, table_data); 2092 /* Host Address Width */ 2093 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2094 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2095 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2096 2097 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2098 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2099 /* Length */ 2100 build_append_int_noprefix(table_data, 2101 16 + ioapic_scope_size + scope_blob->len, 2); 2102 /* Flags */ 2103 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2104 1); 2105 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2106 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2107 /* Register Base Address */ 2108 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2109 2110 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2111 * 8.3.1 (version Oct. 2014 or later). */ 2112 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2113 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2114 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2115 /* Enumeration ID */ 2116 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2117 /* Start Bus Number */ 2118 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2119 /* Path, {Device, Function} pair */ 2120 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2121 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2122 2123 /* Add scope found above */ 2124 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2125 g_array_free(scope_blob, true); 2126 2127 if (iommu->dt_supported) { 2128 /* 8.5 Root Port ATS Capability Reporting Structure */ 2129 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2130 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2131 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2132 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2133 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2134 } 2135 2136 acpi_table_end(linker, &table); 2137 } 2138 2139 /* 2140 * Windows ACPI Emulated Devices Table 2141 * (Version 1.0 - April 6, 2009) 2142 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2143 * 2144 * Helpful to speedup Windows guests and ignored by others. 2145 */ 2146 static void 2147 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2148 const char *oem_table_id) 2149 { 2150 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2151 .oem_table_id = oem_table_id }; 2152 2153 acpi_table_begin(&table, table_data); 2154 /* 2155 * Set "ACPI PM timer good" flag. 2156 * 2157 * Tells Windows guests that our ACPI PM timer is reliable in the 2158 * sense that guest can read it only once to obtain a reliable value. 2159 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2160 */ 2161 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2162 acpi_table_end(linker, &table); 2163 } 2164 2165 /* 2166 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2167 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2168 */ 2169 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2170 2171 /* 2172 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2173 * necessary for the PCI topology. 2174 */ 2175 static void 2176 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2177 { 2178 GArray *table_data = opaque; 2179 uint32_t entry; 2180 2181 /* "Select" IVHD entry, type 0x2 */ 2182 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2183 build_append_int_noprefix(table_data, entry, 4); 2184 2185 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2186 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2187 uint8_t sec = pci_bus_num(sec_bus); 2188 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2189 2190 if (pci_bus_is_express(sec_bus)) { 2191 /* 2192 * Walk the bus if there are subordinates, otherwise use a range 2193 * to cover an entire leaf bus. We could potentially also use a 2194 * range for traversed buses, but we'd need to take care not to 2195 * create both Select and Range entries covering the same device. 2196 * This is easier and potentially more compact. 2197 * 2198 * An example bare metal system seems to use Select entries for 2199 * root ports without a slot (ie. built-ins) and Range entries 2200 * when there is a slot. The same system also only hard-codes 2201 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2202 * making no effort to support nested bridges. We attempt to 2203 * be more thorough here. 2204 */ 2205 if (sec == sub) { /* leaf bus */ 2206 /* "Start of Range" IVHD entry, type 0x3 */ 2207 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2208 build_append_int_noprefix(table_data, entry, 4); 2209 /* "End of Range" IVHD entry, type 0x4 */ 2210 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2211 build_append_int_noprefix(table_data, entry, 4); 2212 } else { 2213 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2214 } 2215 } else { 2216 /* 2217 * If the secondary bus is conventional, then we need to create an 2218 * Alias range for everything downstream. The range covers the 2219 * first devfn on the secondary bus to the last devfn on the 2220 * subordinate bus. The alias target depends on legacy versus 2221 * express bridges, just as in pci_device_iommu_address_space(). 2222 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2223 */ 2224 uint16_t dev_id_a, dev_id_b; 2225 2226 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2227 2228 if (pci_is_express(dev) && 2229 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2230 dev_id_b = dev_id_a; 2231 } else { 2232 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2233 } 2234 2235 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2236 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2237 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2238 2239 /* "End of Range" IVHD entry, type 0x4 */ 2240 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2241 build_append_int_noprefix(table_data, entry, 4); 2242 } 2243 } 2244 } 2245 2246 /* For all PCI host bridges, walk and insert IVHD entries */ 2247 static int 2248 ivrs_host_bridges(Object *obj, void *opaque) 2249 { 2250 GArray *ivhd_blob = opaque; 2251 2252 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2253 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2254 2255 if (bus && !pci_bus_bypass_iommu(bus)) { 2256 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2257 } 2258 } 2259 2260 return 0; 2261 } 2262 2263 static void 2264 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2265 const char *oem_table_id) 2266 { 2267 int ivhd_table_len = 24; 2268 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2269 GArray *ivhd_blob = g_array_new(false, true, 1); 2270 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2271 .oem_table_id = oem_table_id }; 2272 2273 acpi_table_begin(&table, table_data); 2274 /* IVinfo - IO virtualization information common to all 2275 * IOMMU units in a system 2276 */ 2277 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2278 /* reserved */ 2279 build_append_int_noprefix(table_data, 0, 8); 2280 2281 /* IVHD definition - type 10h */ 2282 build_append_int_noprefix(table_data, 0x10, 1); 2283 /* virtualization flags */ 2284 build_append_int_noprefix(table_data, 2285 (1UL << 0) | /* HtTunEn */ 2286 (1UL << 4) | /* iotblSup */ 2287 (1UL << 6) | /* PrefSup */ 2288 (1UL << 7), /* PPRSup */ 2289 1); 2290 2291 /* 2292 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2293 * complete set of IVHD entries. Do this into a separate blob so that we 2294 * can calculate the total IVRS table length here and then append the new 2295 * blob further below. Fall back to an entry covering all devices, which 2296 * is sufficient when no aliases are present. 2297 */ 2298 object_child_foreach_recursive(object_get_root(), 2299 ivrs_host_bridges, ivhd_blob); 2300 2301 if (!ivhd_blob->len) { 2302 /* 2303 * Type 1 device entry reporting all devices 2304 * These are 4-byte device entries currently reporting the range of 2305 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2306 */ 2307 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2308 } 2309 2310 ivhd_table_len += ivhd_blob->len; 2311 2312 /* 2313 * When interrupt remapping is supported, we add a special IVHD device 2314 * for type IO-APIC. 2315 */ 2316 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2317 ivhd_table_len += 8; 2318 } 2319 2320 /* IVHD length */ 2321 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2322 /* DeviceID */ 2323 build_append_int_noprefix(table_data, s->devid, 2); 2324 /* Capability offset */ 2325 build_append_int_noprefix(table_data, s->capab_offset, 2); 2326 /* IOMMU base address */ 2327 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2328 /* PCI Segment Group */ 2329 build_append_int_noprefix(table_data, 0, 2); 2330 /* IOMMU info */ 2331 build_append_int_noprefix(table_data, 0, 2); 2332 /* IOMMU Feature Reporting */ 2333 build_append_int_noprefix(table_data, 2334 (48UL << 30) | /* HATS */ 2335 (48UL << 28) | /* GATS */ 2336 (1UL << 2) | /* GTSup */ 2337 (1UL << 6), /* GASup */ 2338 4); 2339 2340 /* IVHD entries as found above */ 2341 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2342 g_array_free(ivhd_blob, TRUE); 2343 2344 /* 2345 * Add a special IVHD device type. 2346 * Refer to spec - Table 95: IVHD device entry type codes 2347 * 2348 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2349 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2350 */ 2351 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2352 build_append_int_noprefix(table_data, 2353 (0x1ull << 56) | /* type IOAPIC */ 2354 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2355 0x48, /* special device */ 2356 8); 2357 } 2358 acpi_table_end(linker, &table); 2359 } 2360 2361 typedef 2362 struct AcpiBuildState { 2363 /* Copy of table in RAM (for patching). */ 2364 MemoryRegion *table_mr; 2365 /* Is table patched? */ 2366 uint8_t patched; 2367 void *rsdp; 2368 MemoryRegion *rsdp_mr; 2369 MemoryRegion *linker_mr; 2370 } AcpiBuildState; 2371 2372 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2373 { 2374 Object *pci_host; 2375 QObject *o; 2376 2377 pci_host = acpi_get_i386_pci_host(); 2378 if (!pci_host) { 2379 return false; 2380 } 2381 2382 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2383 if (!o) { 2384 return false; 2385 } 2386 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2387 qobject_unref(o); 2388 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2389 return false; 2390 } 2391 2392 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2393 assert(o); 2394 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2395 qobject_unref(o); 2396 return true; 2397 } 2398 2399 static 2400 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2401 { 2402 PCMachineState *pcms = PC_MACHINE(machine); 2403 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2404 X86MachineState *x86ms = X86_MACHINE(machine); 2405 DeviceState *iommu = pcms->iommu; 2406 GArray *table_offsets; 2407 unsigned facs, dsdt, rsdt, fadt; 2408 AcpiPmInfo pm; 2409 AcpiMiscInfo misc; 2410 AcpiMcfgInfo mcfg; 2411 Range pci_hole = {}, pci_hole64 = {}; 2412 uint8_t *u; 2413 size_t aml_len = 0; 2414 GArray *tables_blob = tables->table_data; 2415 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2416 Object *vmgenid_dev; 2417 char *oem_id; 2418 char *oem_table_id; 2419 2420 acpi_get_pm_info(machine, &pm); 2421 acpi_get_misc_info(&misc); 2422 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2423 acpi_get_slic_oem(&slic_oem); 2424 2425 if (slic_oem.id) { 2426 oem_id = slic_oem.id; 2427 } else { 2428 oem_id = x86ms->oem_id; 2429 } 2430 2431 if (slic_oem.table_id) { 2432 oem_table_id = slic_oem.table_id; 2433 } else { 2434 oem_table_id = x86ms->oem_table_id; 2435 } 2436 2437 table_offsets = g_array_new(false, true /* clear */, 2438 sizeof(uint32_t)); 2439 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2440 2441 bios_linker_loader_alloc(tables->linker, 2442 ACPI_BUILD_TABLE_FILE, tables_blob, 2443 64 /* Ensure FACS is aligned */, 2444 false /* high memory */); 2445 2446 /* 2447 * FACS is pointed to by FADT. 2448 * We place it first since it's the only table that has alignment 2449 * requirements. 2450 */ 2451 facs = tables_blob->len; 2452 build_facs(tables_blob); 2453 2454 /* DSDT is pointed to by FADT */ 2455 dsdt = tables_blob->len; 2456 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2457 &pci_hole, &pci_hole64, machine); 2458 2459 /* Count the size of the DSDT and SSDT, we will need it for legacy 2460 * sizing of ACPI tables. 2461 */ 2462 aml_len += tables_blob->len - dsdt; 2463 2464 /* ACPI tables pointed to by RSDT */ 2465 fadt = tables_blob->len; 2466 acpi_add_table(table_offsets, tables_blob); 2467 pm.fadt.facs_tbl_offset = &facs; 2468 pm.fadt.dsdt_tbl_offset = &dsdt; 2469 pm.fadt.xdsdt_tbl_offset = &dsdt; 2470 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2471 aml_len += tables_blob->len - fadt; 2472 2473 acpi_add_table(table_offsets, tables_blob); 2474 acpi_build_madt(tables_blob, tables->linker, x86ms, 2475 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2476 x86ms->oem_table_id); 2477 2478 #ifdef CONFIG_ACPI_ERST 2479 { 2480 Object *erst_dev; 2481 erst_dev = find_erst_dev(); 2482 if (erst_dev) { 2483 acpi_add_table(table_offsets, tables_blob); 2484 build_erst(tables_blob, tables->linker, erst_dev, 2485 x86ms->oem_id, x86ms->oem_table_id); 2486 } 2487 } 2488 #endif 2489 2490 vmgenid_dev = find_vmgenid_dev(); 2491 if (vmgenid_dev) { 2492 acpi_add_table(table_offsets, tables_blob); 2493 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2494 tables->vmgenid, tables->linker, x86ms->oem_id); 2495 } 2496 2497 if (misc.has_hpet) { 2498 acpi_add_table(table_offsets, tables_blob); 2499 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2500 x86ms->oem_table_id); 2501 } 2502 #ifdef CONFIG_TPM 2503 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2504 if (misc.tpm_version == TPM_VERSION_1_2) { 2505 acpi_add_table(table_offsets, tables_blob); 2506 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2507 x86ms->oem_id, x86ms->oem_table_id); 2508 } else { /* TPM_VERSION_2_0 */ 2509 acpi_add_table(table_offsets, tables_blob); 2510 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2511 x86ms->oem_id, x86ms->oem_table_id); 2512 } 2513 } 2514 #endif 2515 if (machine->numa_state->num_nodes) { 2516 acpi_add_table(table_offsets, tables_blob); 2517 build_srat(tables_blob, tables->linker, machine); 2518 if (machine->numa_state->have_numa_distance) { 2519 acpi_add_table(table_offsets, tables_blob); 2520 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2521 x86ms->oem_table_id); 2522 } 2523 if (machine->numa_state->hmat_enabled) { 2524 acpi_add_table(table_offsets, tables_blob); 2525 build_hmat(tables_blob, tables->linker, machine->numa_state, 2526 x86ms->oem_id, x86ms->oem_table_id); 2527 } 2528 } 2529 if (acpi_get_mcfg(&mcfg)) { 2530 acpi_add_table(table_offsets, tables_blob); 2531 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2532 x86ms->oem_table_id); 2533 } 2534 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2535 acpi_add_table(table_offsets, tables_blob); 2536 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2537 x86ms->oem_table_id); 2538 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2539 acpi_add_table(table_offsets, tables_blob); 2540 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2541 x86ms->oem_table_id); 2542 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2543 PCIDevice *pdev = PCI_DEVICE(iommu); 2544 2545 acpi_add_table(table_offsets, tables_blob); 2546 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2547 x86ms->oem_id, x86ms->oem_table_id); 2548 } 2549 if (machine->nvdimms_state->is_enabled) { 2550 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2551 machine->nvdimms_state, machine->ram_slots, 2552 x86ms->oem_id, x86ms->oem_table_id); 2553 } 2554 if (pcms->cxl_devices_state.is_enabled) { 2555 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2556 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2557 } 2558 2559 acpi_add_table(table_offsets, tables_blob); 2560 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2561 2562 /* Add tables supplied by user (if any) */ 2563 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2564 unsigned len = acpi_table_len(u); 2565 2566 acpi_add_table(table_offsets, tables_blob); 2567 g_array_append_vals(tables_blob, u, len); 2568 } 2569 2570 /* RSDT is pointed to by RSDP */ 2571 rsdt = tables_blob->len; 2572 build_rsdt(tables_blob, tables->linker, table_offsets, 2573 oem_id, oem_table_id); 2574 2575 /* RSDP is in FSEG memory, so allocate it separately */ 2576 { 2577 AcpiRsdpData rsdp_data = { 2578 .revision = 0, 2579 .oem_id = x86ms->oem_id, 2580 .xsdt_tbl_offset = NULL, 2581 .rsdt_tbl_offset = &rsdt, 2582 }; 2583 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2584 if (!pcmc->rsdp_in_ram) { 2585 /* We used to allocate some extra space for RSDP revision 2 but 2586 * only used the RSDP revision 0 space. The extra bytes were 2587 * zeroed out and not used. 2588 * Here we continue wasting those extra 16 bytes to make sure we 2589 * don't break migration for machine types 2.2 and older due to 2590 * RSDP blob size mismatch. 2591 */ 2592 build_append_int_noprefix(tables->rsdp, 0, 16); 2593 } 2594 } 2595 2596 /* We'll expose it all to Guest so we want to reduce 2597 * chance of size changes. 2598 * 2599 * We used to align the tables to 4k, but of course this would 2600 * too simple to be enough. 4k turned out to be too small an 2601 * alignment very soon, and in fact it is almost impossible to 2602 * keep the table size stable for all (max_cpus, max_memory_slots) 2603 * combinations. So the table size is always 64k for pc-i440fx-2.1 2604 * and we give an error if the table grows beyond that limit. 2605 * 2606 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2607 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2608 * than 2.0 and we can always pad the smaller tables with zeros. We can 2609 * then use the exact size of the 2.0 tables. 2610 * 2611 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2612 */ 2613 if (pcmc->legacy_acpi_table_size) { 2614 /* Subtracting aml_len gives the size of fixed tables. Then add the 2615 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2616 */ 2617 int legacy_aml_len = 2618 pcmc->legacy_acpi_table_size + 2619 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2620 int legacy_table_size = 2621 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2622 ACPI_BUILD_ALIGN_SIZE); 2623 if (tables_blob->len > legacy_table_size) { 2624 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2625 warn_report("ACPI table size %u exceeds %d bytes," 2626 " migration may not work", 2627 tables_blob->len, legacy_table_size); 2628 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2629 " or PCI bridges."); 2630 } 2631 g_array_set_size(tables_blob, legacy_table_size); 2632 } else { 2633 /* Make sure we have a buffer in case we need to resize the tables. */ 2634 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2635 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2636 warn_report("ACPI table size %u exceeds %d bytes," 2637 " migration may not work", 2638 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2639 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2640 " or PCI bridges."); 2641 } 2642 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2643 } 2644 2645 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2646 2647 /* Cleanup memory that's no longer used. */ 2648 g_array_free(table_offsets, true); 2649 g_free(slic_oem.id); 2650 g_free(slic_oem.table_id); 2651 } 2652 2653 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2654 { 2655 uint32_t size = acpi_data_len(data); 2656 2657 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2658 memory_region_ram_resize(mr, size, &error_abort); 2659 2660 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2661 memory_region_set_dirty(mr, 0, size); 2662 } 2663 2664 static void acpi_build_update(void *build_opaque) 2665 { 2666 AcpiBuildState *build_state = build_opaque; 2667 AcpiBuildTables tables; 2668 2669 /* No state to update or already patched? Nothing to do. */ 2670 if (!build_state || build_state->patched) { 2671 return; 2672 } 2673 build_state->patched = 1; 2674 2675 acpi_build_tables_init(&tables); 2676 2677 acpi_build(&tables, MACHINE(qdev_get_machine())); 2678 2679 acpi_ram_update(build_state->table_mr, tables.table_data); 2680 2681 if (build_state->rsdp) { 2682 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2683 } else { 2684 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2685 } 2686 2687 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2688 acpi_build_tables_cleanup(&tables, true); 2689 } 2690 2691 static void acpi_build_reset(void *build_opaque) 2692 { 2693 AcpiBuildState *build_state = build_opaque; 2694 build_state->patched = 0; 2695 } 2696 2697 static const VMStateDescription vmstate_acpi_build = { 2698 .name = "acpi_build", 2699 .version_id = 1, 2700 .minimum_version_id = 1, 2701 .fields = (VMStateField[]) { 2702 VMSTATE_UINT8(patched, AcpiBuildState), 2703 VMSTATE_END_OF_LIST() 2704 }, 2705 }; 2706 2707 void acpi_setup(void) 2708 { 2709 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2710 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2711 X86MachineState *x86ms = X86_MACHINE(pcms); 2712 AcpiBuildTables tables; 2713 AcpiBuildState *build_state; 2714 Object *vmgenid_dev; 2715 #ifdef CONFIG_TPM 2716 TPMIf *tpm; 2717 static FwCfgTPMConfig tpm_config; 2718 #endif 2719 2720 if (!x86ms->fw_cfg) { 2721 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2722 return; 2723 } 2724 2725 if (!pcms->acpi_build_enabled) { 2726 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2727 return; 2728 } 2729 2730 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2731 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2732 return; 2733 } 2734 2735 build_state = g_malloc0(sizeof *build_state); 2736 2737 acpi_build_tables_init(&tables); 2738 acpi_build(&tables, MACHINE(pcms)); 2739 2740 /* Now expose it all to Guest */ 2741 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2742 build_state, tables.table_data, 2743 ACPI_BUILD_TABLE_FILE); 2744 assert(build_state->table_mr != NULL); 2745 2746 build_state->linker_mr = 2747 acpi_add_rom_blob(acpi_build_update, build_state, 2748 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2749 2750 #ifdef CONFIG_TPM 2751 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2752 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2753 2754 tpm = tpm_find(); 2755 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2756 tpm_config = (FwCfgTPMConfig) { 2757 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2758 .tpm_version = tpm_get_version(tpm), 2759 .tpmppi_version = TPM_PPI_VERSION_1_30 2760 }; 2761 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2762 &tpm_config, sizeof tpm_config); 2763 } 2764 #endif 2765 2766 vmgenid_dev = find_vmgenid_dev(); 2767 if (vmgenid_dev) { 2768 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2769 tables.vmgenid); 2770 } 2771 2772 if (!pcmc->rsdp_in_ram) { 2773 /* 2774 * Keep for compatibility with old machine types. 2775 * Though RSDP is small, its contents isn't immutable, so 2776 * we'll update it along with the rest of tables on guest access. 2777 */ 2778 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2779 2780 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2781 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2782 acpi_build_update, NULL, build_state, 2783 build_state->rsdp, rsdp_size, true); 2784 build_state->rsdp_mr = NULL; 2785 } else { 2786 build_state->rsdp = NULL; 2787 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2788 build_state, tables.rsdp, 2789 ACPI_BUILD_RSDP_FILE); 2790 } 2791 2792 qemu_register_reset(acpi_build_reset, build_state); 2793 acpi_build_reset(build_state); 2794 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2795 2796 /* Cleanup tables but don't free the memory: we track it 2797 * in build_state. 2798 */ 2799 acpi_build_tables_cleanup(&tables, false); 2800 } 2801