1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/core/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/boards.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/rtc/mc146818rtc_regs.h" 49 #include "migration/vmstate.h" 50 #include "hw/mem/memory-device.h" 51 #include "hw/mem/nvdimm.h" 52 #include "sysemu/numa.h" 53 #include "sysemu/reset.h" 54 #include "hw/hyperv/vmbus-bridge.h" 55 56 /* Supported chipsets: */ 57 #include "hw/southbridge/piix.h" 58 #include "hw/acpi/pcihp.h" 59 #include "hw/i386/fw_cfg.h" 60 #include "hw/i386/ich9.h" 61 #include "hw/pci/pci_bus.h" 62 #include "hw/pci-host/q35.h" 63 #include "hw/i386/x86-iommu.h" 64 65 #include "hw/acpi/aml-build.h" 66 #include "hw/acpi/utils.h" 67 #include "hw/acpi/pci.h" 68 69 #include "qom/qom-qobject.h" 70 #include "hw/i386/amd_iommu.h" 71 #include "hw/i386/intel_iommu.h" 72 73 #include "hw/acpi/ipmi.h" 74 #include "hw/acpi/hmat.h" 75 76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 78 * a little bit, there should be plenty of free space since the DSDT 79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 80 */ 81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 82 #define ACPI_BUILD_ALIGN_SIZE 0x1000 83 84 #define ACPI_BUILD_TABLE_SIZE 0x20000 85 86 /* #define DEBUG_ACPI_BUILD */ 87 #ifdef DEBUG_ACPI_BUILD 88 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 90 #else 91 #define ACPI_BUILD_DPRINTF(fmt, ...) 92 #endif 93 94 typedef struct AcpiPmInfo { 95 bool s3_disabled; 96 bool s4_disabled; 97 bool pcihp_bridge_en; 98 bool smi_on_cpuhp; 99 bool pcihp_root_en; 100 uint8_t s4_val; 101 AcpiFadtData fadt; 102 uint16_t cpu_hp_io_base; 103 uint16_t pcihp_io_base; 104 uint16_t pcihp_io_len; 105 } AcpiPmInfo; 106 107 typedef struct AcpiMiscInfo { 108 bool is_piix4; 109 bool has_hpet; 110 TPMVersion tpm_version; 111 const unsigned char *dsdt_code; 112 unsigned dsdt_size; 113 uint16_t pvpanic_port; 114 uint16_t applesmc_io_base; 115 } AcpiMiscInfo; 116 117 typedef struct AcpiBuildPciBusHotplugState { 118 GArray *device_table; 119 GArray *notify_table; 120 struct AcpiBuildPciBusHotplugState *parent; 121 bool pcihp_bridge_en; 122 } AcpiBuildPciBusHotplugState; 123 124 typedef struct FwCfgTPMConfig { 125 uint32_t tpmppi_address; 126 uint8_t tpm_version; 127 uint8_t tpmppi_version; 128 } QEMU_PACKED FwCfgTPMConfig; 129 130 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 131 132 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 133 .space_id = AML_AS_SYSTEM_IO, 134 .address = NVDIMM_ACPI_IO_BASE, 135 .bit_width = NVDIMM_ACPI_IO_LEN << 3 136 }; 137 138 static void init_common_fadt_data(MachineState *ms, Object *o, 139 AcpiFadtData *data) 140 { 141 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 142 AmlAddressSpace as = AML_AS_SYSTEM_IO; 143 AcpiFadtData fadt = { 144 .rev = 3, 145 .flags = 146 (1 << ACPI_FADT_F_WBINVD) | 147 (1 << ACPI_FADT_F_PROC_C1) | 148 (1 << ACPI_FADT_F_SLP_BUTTON) | 149 (1 << ACPI_FADT_F_RTC_S4) | 150 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 151 /* APIC destination mode ("Flat Logical") has an upper limit of 8 152 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 153 * used 154 */ 155 ((ms->smp.max_cpus > 8) ? 156 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 157 .int_model = 1 /* Multiple APIC */, 158 .rtc_century = RTC_CENTURY, 159 .plvl2_lat = 0xfff /* C2 state not supported */, 160 .plvl3_lat = 0xfff /* C3 state not supported */, 161 .smi_cmd = ACPI_PORT_SMI_CMD, 162 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 163 .acpi_enable_cmd = 164 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 165 .acpi_disable_cmd = 166 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 167 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 168 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 169 .address = io + 0x04 }, 170 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 171 .gpe0_blk = { .space_id = as, .bit_width = 172 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 173 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 174 }, 175 }; 176 *data = fadt; 177 } 178 179 static Object *object_resolve_type_unambiguous(const char *typename) 180 { 181 bool ambig; 182 Object *o = object_resolve_path_type("", typename, &ambig); 183 184 if (ambig || !o) { 185 return NULL; 186 } 187 return o; 188 } 189 190 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 191 { 192 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 193 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 194 Object *obj = piix ? piix : lpc; 195 QObject *o; 196 pm->cpu_hp_io_base = 0; 197 pm->pcihp_io_base = 0; 198 pm->pcihp_io_len = 0; 199 pm->smi_on_cpuhp = false; 200 201 assert(obj); 202 init_common_fadt_data(machine, obj, &pm->fadt); 203 if (piix) { 204 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 205 pm->fadt.rev = 1; 206 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 207 pm->pcihp_io_base = 208 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 209 pm->pcihp_io_len = 210 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 211 } 212 if (lpc) { 213 uint64_t smi_features = object_property_get_uint(lpc, 214 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 215 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 216 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 217 pm->fadt.reset_reg = r; 218 pm->fadt.reset_val = 0xf; 219 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 220 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 221 pm->smi_on_cpuhp = 222 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 223 } 224 225 /* The above need not be conditional on machine type because the reset port 226 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 227 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 228 229 /* Fill in optional s3/s4 related properties */ 230 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 231 if (o) { 232 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 233 } else { 234 pm->s3_disabled = false; 235 } 236 qobject_unref(o); 237 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 238 if (o) { 239 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 240 } else { 241 pm->s4_disabled = false; 242 } 243 qobject_unref(o); 244 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 245 if (o) { 246 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 247 } else { 248 pm->s4_val = false; 249 } 250 qobject_unref(o); 251 252 pm->pcihp_bridge_en = 253 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 254 NULL); 255 pm->pcihp_root_en = 256 object_property_get_bool(obj, "acpi-root-pci-hotplug", 257 NULL); 258 } 259 260 static void acpi_get_misc_info(AcpiMiscInfo *info) 261 { 262 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 263 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 264 assert(!!piix != !!lpc); 265 266 if (piix) { 267 info->is_piix4 = true; 268 } 269 if (lpc) { 270 info->is_piix4 = false; 271 } 272 273 info->has_hpet = hpet_find(); 274 info->tpm_version = tpm_get_version(tpm_find()); 275 info->pvpanic_port = pvpanic_port(); 276 info->applesmc_io_base = applesmc_port(); 277 } 278 279 /* 280 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 281 * On i386 arch we only have two pci hosts, so we can look only for them. 282 */ 283 static Object *acpi_get_i386_pci_host(void) 284 { 285 PCIHostState *host; 286 287 host = OBJECT_CHECK(PCIHostState, 288 object_resolve_path("/machine/i440fx", NULL), 289 TYPE_PCI_HOST_BRIDGE); 290 if (!host) { 291 host = OBJECT_CHECK(PCIHostState, 292 object_resolve_path("/machine/q35", NULL), 293 TYPE_PCI_HOST_BRIDGE); 294 } 295 296 return OBJECT(host); 297 } 298 299 static void acpi_get_pci_holes(Range *hole, Range *hole64) 300 { 301 Object *pci_host; 302 303 pci_host = acpi_get_i386_pci_host(); 304 g_assert(pci_host); 305 306 range_set_bounds1(hole, 307 object_property_get_uint(pci_host, 308 PCI_HOST_PROP_PCI_HOLE_START, 309 NULL), 310 object_property_get_uint(pci_host, 311 PCI_HOST_PROP_PCI_HOLE_END, 312 NULL)); 313 range_set_bounds1(hole64, 314 object_property_get_uint(pci_host, 315 PCI_HOST_PROP_PCI_HOLE64_START, 316 NULL), 317 object_property_get_uint(pci_host, 318 PCI_HOST_PROP_PCI_HOLE64_END, 319 NULL)); 320 } 321 322 static void acpi_align_size(GArray *blob, unsigned align) 323 { 324 /* Align size to multiple of given size. This reduces the chance 325 * we need to change size in the future (breaking cross version migration). 326 */ 327 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 328 } 329 330 /* FACS */ 331 static void 332 build_facs(GArray *table_data) 333 { 334 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 335 memcpy(&facs->signature, "FACS", 4); 336 facs->length = cpu_to_le32(sizeof(*facs)); 337 } 338 339 static void build_append_pcihp_notify_entry(Aml *method, int slot) 340 { 341 Aml *if_ctx; 342 int32_t devfn = PCI_DEVFN(slot, 0); 343 344 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 345 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 346 aml_append(method, if_ctx); 347 } 348 349 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 350 bool pcihp_bridge_en) 351 { 352 Aml *dev, *notify_method = NULL, *method; 353 QObject *bsel; 354 PCIBus *sec; 355 int i; 356 357 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 358 if (bsel) { 359 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 360 361 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 362 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 363 } 364 365 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 366 DeviceClass *dc; 367 PCIDeviceClass *pc; 368 PCIDevice *pdev = bus->devices[i]; 369 int slot = PCI_SLOT(i); 370 bool hotplug_enabled_dev; 371 bool bridge_in_acpi; 372 bool cold_plugged_bridge; 373 374 if (!pdev) { 375 if (bsel) { /* add hotplug slots for non present devices */ 376 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 377 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 378 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 379 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 380 aml_append(method, 381 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 382 ); 383 aml_append(dev, method); 384 aml_append(parent_scope, dev); 385 386 build_append_pcihp_notify_entry(notify_method, slot); 387 } 388 continue; 389 } 390 391 pc = PCI_DEVICE_GET_CLASS(pdev); 392 dc = DEVICE_GET_CLASS(pdev); 393 394 /* 395 * Cold plugged bridges aren't themselves hot-pluggable. 396 * Hotplugged bridges *are* hot-pluggable. 397 */ 398 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 399 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 400 401 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 402 403 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 404 continue; 405 } 406 407 /* start to compose PCI slot descriptor */ 408 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 409 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 410 411 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 412 /* add VGA specific AML methods */ 413 int s3d; 414 415 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 416 s3d = 3; 417 } else { 418 s3d = 0; 419 } 420 421 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 422 aml_append(method, aml_return(aml_int(0))); 423 aml_append(dev, method); 424 425 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 426 aml_append(method, aml_return(aml_int(0))); 427 aml_append(dev, method); 428 429 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 430 aml_append(method, aml_return(aml_int(s3d))); 431 aml_append(dev, method); 432 } else if (hotplug_enabled_dev) { 433 /* add _SUN/_EJ0 to make slot hotpluggable */ 434 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 435 436 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 437 aml_append(method, 438 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 439 ); 440 aml_append(dev, method); 441 442 if (bsel) { 443 build_append_pcihp_notify_entry(notify_method, slot); 444 } 445 } else if (bridge_in_acpi) { 446 /* 447 * device is coldplugged bridge, 448 * add child device descriptions into its scope 449 */ 450 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 451 452 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 453 } 454 /* slot descriptor has been composed, add it into parent context */ 455 aml_append(parent_scope, dev); 456 } 457 458 if (bsel) { 459 aml_append(parent_scope, notify_method); 460 } 461 462 /* Append PCNT method to notify about events on local and child buses. 463 * Add this method for root bus only when hotplug is enabled since DSDT 464 * expects it. 465 */ 466 if (bsel || pcihp_bridge_en) { 467 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 468 469 /* If bus supports hotplug select it and notify about local events */ 470 if (bsel) { 471 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 472 473 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 474 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 475 aml_int(1))); /* Device Check */ 476 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 477 aml_int(3))); /* Eject Request */ 478 } 479 480 /* Notify about child bus events in any case */ 481 if (pcihp_bridge_en) { 482 QLIST_FOREACH(sec, &bus->child, sibling) { 483 int32_t devfn = sec->parent_dev->devfn; 484 485 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 486 continue; 487 } 488 489 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 490 } 491 } 492 493 aml_append(parent_scope, method); 494 } 495 qobject_unref(bsel); 496 } 497 498 /** 499 * build_prt_entry: 500 * @link_name: link name for PCI route entry 501 * 502 * build AML package containing a PCI route entry for @link_name 503 */ 504 static Aml *build_prt_entry(const char *link_name) 505 { 506 Aml *a_zero = aml_int(0); 507 Aml *pkg = aml_package(4); 508 aml_append(pkg, a_zero); 509 aml_append(pkg, a_zero); 510 aml_append(pkg, aml_name("%s", link_name)); 511 aml_append(pkg, a_zero); 512 return pkg; 513 } 514 515 /* 516 * initialize_route - Initialize the interrupt routing rule 517 * through a specific LINK: 518 * if (lnk_idx == idx) 519 * route using link 'link_name' 520 */ 521 static Aml *initialize_route(Aml *route, const char *link_name, 522 Aml *lnk_idx, int idx) 523 { 524 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 525 Aml *pkg = build_prt_entry(link_name); 526 527 aml_append(if_ctx, aml_store(pkg, route)); 528 529 return if_ctx; 530 } 531 532 /* 533 * build_prt - Define interrupt rounting rules 534 * 535 * Returns an array of 128 routes, one for each device, 536 * based on device location. 537 * The main goal is to equaly distribute the interrupts 538 * over the 4 existing ACPI links (works only for i440fx). 539 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 540 * 541 */ 542 static Aml *build_prt(bool is_pci0_prt) 543 { 544 Aml *method, *while_ctx, *pin, *res; 545 546 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 547 res = aml_local(0); 548 pin = aml_local(1); 549 aml_append(method, aml_store(aml_package(128), res)); 550 aml_append(method, aml_store(aml_int(0), pin)); 551 552 /* while (pin < 128) */ 553 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 554 { 555 Aml *slot = aml_local(2); 556 Aml *lnk_idx = aml_local(3); 557 Aml *route = aml_local(4); 558 559 /* slot = pin >> 2 */ 560 aml_append(while_ctx, 561 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 562 /* lnk_idx = (slot + pin) & 3 */ 563 aml_append(while_ctx, 564 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 565 lnk_idx)); 566 567 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 568 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 569 if (is_pci0_prt) { 570 Aml *if_device_1, *if_pin_4, *else_pin_4; 571 572 /* device 1 is the power-management device, needs SCI */ 573 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 574 { 575 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 576 { 577 aml_append(if_pin_4, 578 aml_store(build_prt_entry("LNKS"), route)); 579 } 580 aml_append(if_device_1, if_pin_4); 581 else_pin_4 = aml_else(); 582 { 583 aml_append(else_pin_4, 584 aml_store(build_prt_entry("LNKA"), route)); 585 } 586 aml_append(if_device_1, else_pin_4); 587 } 588 aml_append(while_ctx, if_device_1); 589 } else { 590 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 591 } 592 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 593 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 594 595 /* route[0] = 0x[slot]FFFF */ 596 aml_append(while_ctx, 597 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 598 NULL), 599 aml_index(route, aml_int(0)))); 600 /* route[1] = pin & 3 */ 601 aml_append(while_ctx, 602 aml_store(aml_and(pin, aml_int(3), NULL), 603 aml_index(route, aml_int(1)))); 604 /* res[pin] = route */ 605 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 606 /* pin++ */ 607 aml_append(while_ctx, aml_increment(pin)); 608 } 609 aml_append(method, while_ctx); 610 /* return res*/ 611 aml_append(method, aml_return(res)); 612 613 return method; 614 } 615 616 typedef struct CrsRangeEntry { 617 uint64_t base; 618 uint64_t limit; 619 } CrsRangeEntry; 620 621 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 622 { 623 CrsRangeEntry *entry; 624 625 entry = g_malloc(sizeof(*entry)); 626 entry->base = base; 627 entry->limit = limit; 628 629 g_ptr_array_add(ranges, entry); 630 } 631 632 static void crs_range_free(gpointer data) 633 { 634 CrsRangeEntry *entry = (CrsRangeEntry *)data; 635 g_free(entry); 636 } 637 638 typedef struct CrsRangeSet { 639 GPtrArray *io_ranges; 640 GPtrArray *mem_ranges; 641 GPtrArray *mem_64bit_ranges; 642 } CrsRangeSet; 643 644 static void crs_range_set_init(CrsRangeSet *range_set) 645 { 646 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 647 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 648 range_set->mem_64bit_ranges = 649 g_ptr_array_new_with_free_func(crs_range_free); 650 } 651 652 static void crs_range_set_free(CrsRangeSet *range_set) 653 { 654 g_ptr_array_free(range_set->io_ranges, true); 655 g_ptr_array_free(range_set->mem_ranges, true); 656 g_ptr_array_free(range_set->mem_64bit_ranges, true); 657 } 658 659 static gint crs_range_compare(gconstpointer a, gconstpointer b) 660 { 661 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 662 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 663 664 if (entry_a->base < entry_b->base) { 665 return -1; 666 } else if (entry_a->base > entry_b->base) { 667 return 1; 668 } else { 669 return 0; 670 } 671 } 672 673 /* 674 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 675 * interval, computes the 'free' ranges from the same interval. 676 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 677 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 678 */ 679 static void crs_replace_with_free_ranges(GPtrArray *ranges, 680 uint64_t start, uint64_t end) 681 { 682 GPtrArray *free_ranges = g_ptr_array_new(); 683 uint64_t free_base = start; 684 int i; 685 686 g_ptr_array_sort(ranges, crs_range_compare); 687 for (i = 0; i < ranges->len; i++) { 688 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 689 690 if (free_base < used->base) { 691 crs_range_insert(free_ranges, free_base, used->base - 1); 692 } 693 694 free_base = used->limit + 1; 695 } 696 697 if (free_base < end) { 698 crs_range_insert(free_ranges, free_base, end); 699 } 700 701 g_ptr_array_set_size(ranges, 0); 702 for (i = 0; i < free_ranges->len; i++) { 703 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 704 } 705 706 g_ptr_array_free(free_ranges, true); 707 } 708 709 /* 710 * crs_range_merge - merges adjacent ranges in the given array. 711 * Array elements are deleted and replaced with the merged ranges. 712 */ 713 static void crs_range_merge(GPtrArray *range) 714 { 715 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 716 CrsRangeEntry *entry; 717 uint64_t range_base, range_limit; 718 int i; 719 720 if (!range->len) { 721 return; 722 } 723 724 g_ptr_array_sort(range, crs_range_compare); 725 726 entry = g_ptr_array_index(range, 0); 727 range_base = entry->base; 728 range_limit = entry->limit; 729 for (i = 1; i < range->len; i++) { 730 entry = g_ptr_array_index(range, i); 731 if (entry->base - 1 == range_limit) { 732 range_limit = entry->limit; 733 } else { 734 crs_range_insert(tmp, range_base, range_limit); 735 range_base = entry->base; 736 range_limit = entry->limit; 737 } 738 } 739 crs_range_insert(tmp, range_base, range_limit); 740 741 g_ptr_array_set_size(range, 0); 742 for (i = 0; i < tmp->len; i++) { 743 entry = g_ptr_array_index(tmp, i); 744 crs_range_insert(range, entry->base, entry->limit); 745 } 746 g_ptr_array_free(tmp, true); 747 } 748 749 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 750 { 751 Aml *crs = aml_resource_template(); 752 CrsRangeSet temp_range_set; 753 CrsRangeEntry *entry; 754 uint8_t max_bus = pci_bus_num(host->bus); 755 uint8_t type; 756 int devfn; 757 int i; 758 759 crs_range_set_init(&temp_range_set); 760 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 761 uint64_t range_base, range_limit; 762 PCIDevice *dev = host->bus->devices[devfn]; 763 764 if (!dev) { 765 continue; 766 } 767 768 for (i = 0; i < PCI_NUM_REGIONS; i++) { 769 PCIIORegion *r = &dev->io_regions[i]; 770 771 range_base = r->addr; 772 range_limit = r->addr + r->size - 1; 773 774 /* 775 * Work-around for old bioses 776 * that do not support multiple root buses 777 */ 778 if (!range_base || range_base > range_limit) { 779 continue; 780 } 781 782 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 783 crs_range_insert(temp_range_set.io_ranges, 784 range_base, range_limit); 785 } else { /* "memory" */ 786 uint64_t length = range_limit - range_base + 1; 787 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 788 crs_range_insert(temp_range_set.mem_ranges, range_base, 789 range_limit); 790 } else { 791 crs_range_insert(temp_range_set.mem_64bit_ranges, 792 range_base, range_limit); 793 } 794 } 795 } 796 797 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 798 if (type == PCI_HEADER_TYPE_BRIDGE) { 799 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 800 if (subordinate > max_bus) { 801 max_bus = subordinate; 802 } 803 804 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 805 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 806 807 /* 808 * Work-around for old bioses 809 * that do not support multiple root buses 810 */ 811 if (range_base && range_base <= range_limit) { 812 crs_range_insert(temp_range_set.io_ranges, 813 range_base, range_limit); 814 } 815 816 range_base = 817 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 818 range_limit = 819 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 820 821 /* 822 * Work-around for old bioses 823 * that do not support multiple root buses 824 */ 825 if (range_base && range_base <= range_limit) { 826 uint64_t length = range_limit - range_base + 1; 827 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 828 crs_range_insert(temp_range_set.mem_ranges, 829 range_base, range_limit); 830 } else { 831 crs_range_insert(temp_range_set.mem_64bit_ranges, 832 range_base, range_limit); 833 } 834 } 835 836 range_base = 837 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 838 range_limit = 839 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 840 841 /* 842 * Work-around for old bioses 843 * that do not support multiple root buses 844 */ 845 if (range_base && range_base <= range_limit) { 846 uint64_t length = range_limit - range_base + 1; 847 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 848 crs_range_insert(temp_range_set.mem_ranges, 849 range_base, range_limit); 850 } else { 851 crs_range_insert(temp_range_set.mem_64bit_ranges, 852 range_base, range_limit); 853 } 854 } 855 } 856 } 857 858 crs_range_merge(temp_range_set.io_ranges); 859 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 860 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 861 aml_append(crs, 862 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 863 AML_POS_DECODE, AML_ENTIRE_RANGE, 864 0, entry->base, entry->limit, 0, 865 entry->limit - entry->base + 1)); 866 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 867 } 868 869 crs_range_merge(temp_range_set.mem_ranges); 870 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 871 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 872 assert(entry->limit <= UINT32_MAX && 873 (entry->limit - entry->base + 1) <= UINT32_MAX); 874 aml_append(crs, 875 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 876 AML_MAX_FIXED, AML_NON_CACHEABLE, 877 AML_READ_WRITE, 878 0, entry->base, entry->limit, 0, 879 entry->limit - entry->base + 1)); 880 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 881 } 882 883 crs_range_merge(temp_range_set.mem_64bit_ranges); 884 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 885 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 886 aml_append(crs, 887 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 888 AML_MAX_FIXED, AML_NON_CACHEABLE, 889 AML_READ_WRITE, 890 0, entry->base, entry->limit, 0, 891 entry->limit - entry->base + 1)); 892 crs_range_insert(range_set->mem_64bit_ranges, 893 entry->base, entry->limit); 894 } 895 896 crs_range_set_free(&temp_range_set); 897 898 aml_append(crs, 899 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 900 0, 901 pci_bus_num(host->bus), 902 max_bus, 903 0, 904 max_bus - pci_bus_num(host->bus) + 1)); 905 906 return crs; 907 } 908 909 static void build_hpet_aml(Aml *table) 910 { 911 Aml *crs; 912 Aml *field; 913 Aml *method; 914 Aml *if_ctx; 915 Aml *scope = aml_scope("_SB"); 916 Aml *dev = aml_device("HPET"); 917 Aml *zero = aml_int(0); 918 Aml *id = aml_local(0); 919 Aml *period = aml_local(1); 920 921 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 922 aml_append(dev, aml_name_decl("_UID", zero)); 923 924 aml_append(dev, 925 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 926 HPET_LEN)); 927 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 928 aml_append(field, aml_named_field("VEND", 32)); 929 aml_append(field, aml_named_field("PRD", 32)); 930 aml_append(dev, field); 931 932 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 933 aml_append(method, aml_store(aml_name("VEND"), id)); 934 aml_append(method, aml_store(aml_name("PRD"), period)); 935 aml_append(method, aml_shiftright(id, aml_int(16), id)); 936 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 937 aml_equal(id, aml_int(0xffff)))); 938 { 939 aml_append(if_ctx, aml_return(zero)); 940 } 941 aml_append(method, if_ctx); 942 943 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 944 aml_lgreater(period, aml_int(100000000)))); 945 { 946 aml_append(if_ctx, aml_return(zero)); 947 } 948 aml_append(method, if_ctx); 949 950 aml_append(method, aml_return(aml_int(0x0F))); 951 aml_append(dev, method); 952 953 crs = aml_resource_template(); 954 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 955 aml_append(dev, aml_name_decl("_CRS", crs)); 956 957 aml_append(scope, dev); 958 aml_append(table, scope); 959 } 960 961 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 962 { 963 Aml *dev; 964 Aml *method; 965 Aml *crs; 966 967 dev = aml_device("VMBS"); 968 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 969 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 970 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 971 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 972 973 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 974 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 975 aml_name("STA"))); 976 aml_append(dev, method); 977 978 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 979 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 980 aml_name("STA"))); 981 aml_append(dev, method); 982 983 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 984 aml_append(method, aml_return(aml_name("STA"))); 985 aml_append(dev, method); 986 987 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 988 989 crs = aml_resource_template(); 990 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 991 aml_append(dev, aml_name_decl("_CRS", crs)); 992 993 return dev; 994 } 995 996 static void build_isa_devices_aml(Aml *table) 997 { 998 bool ambiguous; 999 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 1000 Aml *scope; 1001 1002 assert(obj && !ambiguous); 1003 1004 scope = aml_scope("_SB.PCI0.ISA"); 1005 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 1006 isa_build_aml(ISA_BUS(obj), scope); 1007 1008 aml_append(table, scope); 1009 } 1010 1011 static void build_dbg_aml(Aml *table) 1012 { 1013 Aml *field; 1014 Aml *method; 1015 Aml *while_ctx; 1016 Aml *scope = aml_scope("\\"); 1017 Aml *buf = aml_local(0); 1018 Aml *len = aml_local(1); 1019 Aml *idx = aml_local(2); 1020 1021 aml_append(scope, 1022 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1023 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1024 aml_append(field, aml_named_field("DBGB", 8)); 1025 aml_append(scope, field); 1026 1027 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1028 1029 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1030 aml_append(method, aml_to_buffer(buf, buf)); 1031 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1032 aml_append(method, aml_store(aml_int(0), idx)); 1033 1034 while_ctx = aml_while(aml_lless(idx, len)); 1035 aml_append(while_ctx, 1036 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1037 aml_append(while_ctx, aml_increment(idx)); 1038 aml_append(method, while_ctx); 1039 1040 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1041 aml_append(scope, method); 1042 1043 aml_append(table, scope); 1044 } 1045 1046 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1047 { 1048 Aml *dev; 1049 Aml *crs; 1050 Aml *method; 1051 uint32_t irqs[] = {5, 10, 11}; 1052 1053 dev = aml_device("%s", name); 1054 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1055 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1056 1057 crs = aml_resource_template(); 1058 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1059 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1060 aml_append(dev, aml_name_decl("_PRS", crs)); 1061 1062 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1063 aml_append(method, aml_return(aml_call1("IQST", reg))); 1064 aml_append(dev, method); 1065 1066 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1067 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1068 aml_append(dev, method); 1069 1070 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1071 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1072 aml_append(dev, method); 1073 1074 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1075 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1076 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1077 aml_append(dev, method); 1078 1079 return dev; 1080 } 1081 1082 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1083 { 1084 Aml *dev; 1085 Aml *crs; 1086 Aml *method; 1087 uint32_t irqs; 1088 1089 dev = aml_device("%s", name); 1090 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1091 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1092 1093 crs = aml_resource_template(); 1094 irqs = gsi; 1095 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1096 AML_SHARED, &irqs, 1)); 1097 aml_append(dev, aml_name_decl("_PRS", crs)); 1098 1099 aml_append(dev, aml_name_decl("_CRS", crs)); 1100 1101 /* 1102 * _DIS can be no-op because the interrupt cannot be disabled. 1103 */ 1104 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1105 aml_append(dev, method); 1106 1107 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1108 aml_append(dev, method); 1109 1110 return dev; 1111 } 1112 1113 /* _CRS method - get current settings */ 1114 static Aml *build_iqcr_method(bool is_piix4) 1115 { 1116 Aml *if_ctx; 1117 uint32_t irqs; 1118 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1119 Aml *crs = aml_resource_template(); 1120 1121 irqs = 0; 1122 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1123 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1124 aml_append(method, aml_name_decl("PRR0", crs)); 1125 1126 aml_append(method, 1127 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1128 1129 if (is_piix4) { 1130 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1131 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1132 aml_append(method, if_ctx); 1133 } else { 1134 aml_append(method, 1135 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1136 aml_name("PRRI"))); 1137 } 1138 1139 aml_append(method, aml_return(aml_name("PRR0"))); 1140 return method; 1141 } 1142 1143 /* _STA method - get status */ 1144 static Aml *build_irq_status_method(void) 1145 { 1146 Aml *if_ctx; 1147 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1148 1149 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1150 aml_append(if_ctx, aml_return(aml_int(0x09))); 1151 aml_append(method, if_ctx); 1152 aml_append(method, aml_return(aml_int(0x0B))); 1153 return method; 1154 } 1155 1156 static void build_piix4_pci0_int(Aml *table) 1157 { 1158 Aml *dev; 1159 Aml *crs; 1160 Aml *field; 1161 Aml *method; 1162 uint32_t irqs; 1163 Aml *sb_scope = aml_scope("_SB"); 1164 Aml *pci0_scope = aml_scope("PCI0"); 1165 1166 aml_append(pci0_scope, build_prt(true)); 1167 aml_append(sb_scope, pci0_scope); 1168 1169 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1170 aml_append(field, aml_named_field("PRQ0", 8)); 1171 aml_append(field, aml_named_field("PRQ1", 8)); 1172 aml_append(field, aml_named_field("PRQ2", 8)); 1173 aml_append(field, aml_named_field("PRQ3", 8)); 1174 aml_append(sb_scope, field); 1175 1176 aml_append(sb_scope, build_irq_status_method()); 1177 aml_append(sb_scope, build_iqcr_method(true)); 1178 1179 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1180 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1181 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1182 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1183 1184 dev = aml_device("LNKS"); 1185 { 1186 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1187 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1188 1189 crs = aml_resource_template(); 1190 irqs = 9; 1191 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1192 AML_ACTIVE_HIGH, AML_SHARED, 1193 &irqs, 1)); 1194 aml_append(dev, aml_name_decl("_PRS", crs)); 1195 1196 /* The SCI cannot be disabled and is always attached to GSI 9, 1197 * so these are no-ops. We only need this link to override the 1198 * polarity to active high and match the content of the MADT. 1199 */ 1200 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1201 aml_append(method, aml_return(aml_int(0x0b))); 1202 aml_append(dev, method); 1203 1204 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1205 aml_append(dev, method); 1206 1207 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1208 aml_append(method, aml_return(aml_name("_PRS"))); 1209 aml_append(dev, method); 1210 1211 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1212 aml_append(dev, method); 1213 } 1214 aml_append(sb_scope, dev); 1215 1216 aml_append(table, sb_scope); 1217 } 1218 1219 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1220 { 1221 int i; 1222 int head; 1223 Aml *pkg; 1224 char base = name[3] < 'E' ? 'A' : 'E'; 1225 char *s = g_strdup(name); 1226 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1227 1228 assert(strlen(s) == 4); 1229 1230 head = name[3] - base; 1231 for (i = 0; i < 4; i++) { 1232 if (head + i > 3) { 1233 head = i * -1; 1234 } 1235 s[3] = base + head + i; 1236 pkg = aml_package(4); 1237 aml_append(pkg, a_nr); 1238 aml_append(pkg, aml_int(i)); 1239 aml_append(pkg, aml_name("%s", s)); 1240 aml_append(pkg, aml_int(0)); 1241 aml_append(ctx, pkg); 1242 } 1243 g_free(s); 1244 } 1245 1246 static Aml *build_q35_routing_table(const char *str) 1247 { 1248 int i; 1249 Aml *pkg; 1250 char *name = g_strdup_printf("%s ", str); 1251 1252 pkg = aml_package(128); 1253 for (i = 0; i < 0x18; i++) { 1254 name[3] = 'E' + (i & 0x3); 1255 append_q35_prt_entry(pkg, i, name); 1256 } 1257 1258 name[3] = 'E'; 1259 append_q35_prt_entry(pkg, 0x18, name); 1260 1261 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1262 for (i = 0x0019; i < 0x1e; i++) { 1263 name[3] = 'A'; 1264 append_q35_prt_entry(pkg, i, name); 1265 } 1266 1267 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1268 name[3] = 'E'; 1269 append_q35_prt_entry(pkg, 0x1e, name); 1270 name[3] = 'A'; 1271 append_q35_prt_entry(pkg, 0x1f, name); 1272 1273 g_free(name); 1274 return pkg; 1275 } 1276 1277 static void build_q35_pci0_int(Aml *table) 1278 { 1279 Aml *field; 1280 Aml *method; 1281 Aml *sb_scope = aml_scope("_SB"); 1282 Aml *pci0_scope = aml_scope("PCI0"); 1283 1284 /* Zero => PIC mode, One => APIC Mode */ 1285 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1286 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1287 { 1288 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1289 } 1290 aml_append(table, method); 1291 1292 aml_append(pci0_scope, 1293 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1294 aml_append(pci0_scope, 1295 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1296 1297 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1298 { 1299 Aml *if_ctx; 1300 Aml *else_ctx; 1301 1302 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1303 section 6.2.8.1 */ 1304 /* Note: we provide the same info as the PCI routing 1305 table of the Bochs BIOS */ 1306 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1307 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1308 aml_append(method, if_ctx); 1309 else_ctx = aml_else(); 1310 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1311 aml_append(method, else_ctx); 1312 } 1313 aml_append(pci0_scope, method); 1314 aml_append(sb_scope, pci0_scope); 1315 1316 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1317 aml_append(field, aml_named_field("PRQA", 8)); 1318 aml_append(field, aml_named_field("PRQB", 8)); 1319 aml_append(field, aml_named_field("PRQC", 8)); 1320 aml_append(field, aml_named_field("PRQD", 8)); 1321 aml_append(field, aml_reserved_field(0x20)); 1322 aml_append(field, aml_named_field("PRQE", 8)); 1323 aml_append(field, aml_named_field("PRQF", 8)); 1324 aml_append(field, aml_named_field("PRQG", 8)); 1325 aml_append(field, aml_named_field("PRQH", 8)); 1326 aml_append(sb_scope, field); 1327 1328 aml_append(sb_scope, build_irq_status_method()); 1329 aml_append(sb_scope, build_iqcr_method(false)); 1330 1331 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1332 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1333 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1334 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1335 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1336 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1337 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1338 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1339 1340 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1341 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1342 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1343 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1344 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1345 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1346 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1347 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1348 1349 aml_append(table, sb_scope); 1350 } 1351 1352 static void build_q35_isa_bridge(Aml *table) 1353 { 1354 Aml *dev; 1355 Aml *scope; 1356 1357 scope = aml_scope("_SB.PCI0"); 1358 dev = aml_device("ISA"); 1359 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1360 1361 /* ICH9 PCI to ISA irq remapping */ 1362 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1363 aml_int(0x60), 0x0C)); 1364 1365 aml_append(scope, dev); 1366 aml_append(table, scope); 1367 } 1368 1369 static void build_piix4_isa_bridge(Aml *table) 1370 { 1371 Aml *dev; 1372 Aml *scope; 1373 1374 scope = aml_scope("_SB.PCI0"); 1375 dev = aml_device("ISA"); 1376 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1377 1378 /* PIIX PCI to ISA irq remapping */ 1379 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1380 aml_int(0x60), 0x04)); 1381 1382 aml_append(scope, dev); 1383 aml_append(table, scope); 1384 } 1385 1386 static void build_piix4_pci_hotplug(Aml *table) 1387 { 1388 Aml *scope; 1389 Aml *field; 1390 Aml *method; 1391 1392 scope = aml_scope("_SB.PCI0"); 1393 1394 aml_append(scope, 1395 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1396 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1397 aml_append(field, aml_named_field("PCIU", 32)); 1398 aml_append(field, aml_named_field("PCID", 32)); 1399 aml_append(scope, field); 1400 1401 aml_append(scope, 1402 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1403 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1404 aml_append(field, aml_named_field("B0EJ", 32)); 1405 aml_append(scope, field); 1406 1407 aml_append(scope, 1408 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1409 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1410 aml_append(field, aml_named_field("BNUM", 32)); 1411 aml_append(scope, field); 1412 1413 aml_append(scope, aml_mutex("BLCK", 0)); 1414 1415 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1416 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1417 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1418 aml_append(method, 1419 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1420 aml_append(method, aml_release(aml_name("BLCK"))); 1421 aml_append(method, aml_return(aml_int(0))); 1422 aml_append(scope, method); 1423 1424 aml_append(table, scope); 1425 } 1426 1427 static Aml *build_q35_osc_method(void) 1428 { 1429 Aml *if_ctx; 1430 Aml *if_ctx2; 1431 Aml *else_ctx; 1432 Aml *method; 1433 Aml *a_cwd1 = aml_name("CDW1"); 1434 Aml *a_ctrl = aml_local(0); 1435 1436 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1437 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1438 1439 if_ctx = aml_if(aml_equal( 1440 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1441 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1442 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1443 1444 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1445 1446 /* 1447 * Always allow native PME, AER (no dependencies) 1448 * Allow SHPC (PCI bridges can have SHPC controller) 1449 */ 1450 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1451 1452 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1453 /* Unknown revision */ 1454 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1455 aml_append(if_ctx, if_ctx2); 1456 1457 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1458 /* Capabilities bits were masked */ 1459 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1460 aml_append(if_ctx, if_ctx2); 1461 1462 /* Update DWORD3 in the buffer */ 1463 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1464 aml_append(method, if_ctx); 1465 1466 else_ctx = aml_else(); 1467 /* Unrecognized UUID */ 1468 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1469 aml_append(method, else_ctx); 1470 1471 aml_append(method, aml_return(aml_arg(3))); 1472 return method; 1473 } 1474 1475 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1476 { 1477 Aml *scope = aml_scope("_SB.PCI0"); 1478 Aml *dev = aml_device("SMB0"); 1479 1480 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1481 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1482 aml_append(scope, dev); 1483 aml_append(table, scope); 1484 } 1485 1486 static void 1487 build_dsdt(GArray *table_data, BIOSLinker *linker, 1488 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1489 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1490 { 1491 CrsRangeEntry *entry; 1492 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1493 CrsRangeSet crs_range_set; 1494 PCMachineState *pcms = PC_MACHINE(machine); 1495 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1496 X86MachineState *x86ms = X86_MACHINE(machine); 1497 AcpiMcfgInfo mcfg; 1498 uint32_t nr_mem = machine->ram_slots; 1499 int root_bus_limit = 0xFF; 1500 PCIBus *bus = NULL; 1501 TPMIf *tpm = tpm_find(); 1502 int i; 1503 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1504 1505 dsdt = init_aml_allocator(); 1506 1507 /* Reserve space for header */ 1508 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1509 1510 build_dbg_aml(dsdt); 1511 if (misc->is_piix4) { 1512 sb_scope = aml_scope("_SB"); 1513 dev = aml_device("PCI0"); 1514 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1515 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1516 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1517 aml_append(sb_scope, dev); 1518 aml_append(dsdt, sb_scope); 1519 1520 build_hpet_aml(dsdt); 1521 build_piix4_isa_bridge(dsdt); 1522 build_isa_devices_aml(dsdt); 1523 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1524 build_piix4_pci_hotplug(dsdt); 1525 } 1526 build_piix4_pci0_int(dsdt); 1527 } else { 1528 sb_scope = aml_scope("_SB"); 1529 dev = aml_device("PCI0"); 1530 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1531 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1532 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1533 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1534 aml_append(dev, build_q35_osc_method()); 1535 aml_append(sb_scope, dev); 1536 1537 if (pm->smi_on_cpuhp) { 1538 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1539 dev = aml_device("PCI0.SMI0"); 1540 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1541 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1542 crs = aml_resource_template(); 1543 aml_append(crs, 1544 aml_io( 1545 AML_DECODE16, 1546 ACPI_PORT_SMI_CMD, 1547 ACPI_PORT_SMI_CMD, 1548 1, 1549 2) 1550 ); 1551 aml_append(dev, aml_name_decl("_CRS", crs)); 1552 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1553 aml_int(ACPI_PORT_SMI_CMD), 2)); 1554 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1555 AML_WRITE_AS_ZEROS); 1556 aml_append(field, aml_named_field("SMIC", 8)); 1557 aml_append(field, aml_reserved_field(8)); 1558 aml_append(dev, field); 1559 aml_append(sb_scope, dev); 1560 } 1561 1562 aml_append(dsdt, sb_scope); 1563 1564 build_hpet_aml(dsdt); 1565 build_q35_isa_bridge(dsdt); 1566 build_isa_devices_aml(dsdt); 1567 build_q35_pci0_int(dsdt); 1568 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1569 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1570 } 1571 } 1572 1573 if (vmbus_bridge) { 1574 sb_scope = aml_scope("_SB"); 1575 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1576 aml_append(dsdt, sb_scope); 1577 } 1578 1579 if (pcmc->legacy_cpu_hotplug) { 1580 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1581 } else { 1582 CPUHotplugFeatures opts = { 1583 .acpi_1_compatible = true, .has_legacy_cphp = true, 1584 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1585 }; 1586 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1587 "\\_SB.PCI0", "\\_GPE._E02"); 1588 } 1589 1590 if (pcms->memhp_io_base && nr_mem) { 1591 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1592 "\\_GPE._E03", AML_SYSTEM_IO, 1593 pcms->memhp_io_base); 1594 } 1595 1596 scope = aml_scope("_GPE"); 1597 { 1598 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1599 1600 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1601 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1602 aml_append(method, 1603 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1604 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1605 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1606 aml_append(scope, method); 1607 } 1608 1609 if (machine->nvdimms_state->is_enabled) { 1610 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1611 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1612 aml_int(0x80))); 1613 aml_append(scope, method); 1614 } 1615 } 1616 aml_append(dsdt, scope); 1617 1618 crs_range_set_init(&crs_range_set); 1619 bus = PC_MACHINE(machine)->bus; 1620 if (bus) { 1621 QLIST_FOREACH(bus, &bus->child, sibling) { 1622 uint8_t bus_num = pci_bus_num(bus); 1623 uint8_t numa_node = pci_bus_numa_node(bus); 1624 1625 /* look only for expander root buses */ 1626 if (!pci_bus_is_root(bus)) { 1627 continue; 1628 } 1629 1630 if (bus_num < root_bus_limit) { 1631 root_bus_limit = bus_num - 1; 1632 } 1633 1634 scope = aml_scope("\\_SB"); 1635 dev = aml_device("PC%.02X", bus_num); 1636 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1637 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1638 if (pci_bus_is_express(bus)) { 1639 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1640 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1641 aml_append(dev, build_q35_osc_method()); 1642 } else { 1643 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1644 } 1645 1646 if (numa_node != NUMA_NODE_UNASSIGNED) { 1647 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1648 } 1649 1650 aml_append(dev, build_prt(false)); 1651 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1652 aml_append(dev, aml_name_decl("_CRS", crs)); 1653 aml_append(scope, dev); 1654 aml_append(dsdt, scope); 1655 } 1656 } 1657 1658 /* 1659 * At this point crs_range_set has all the ranges used by pci 1660 * busses *other* than PCI0. These ranges will be excluded from 1661 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1662 * too. 1663 */ 1664 if (acpi_get_mcfg(&mcfg)) { 1665 crs_range_insert(crs_range_set.mem_ranges, 1666 mcfg.base, mcfg.base + mcfg.size - 1); 1667 } 1668 1669 scope = aml_scope("\\_SB.PCI0"); 1670 /* build PCI0._CRS */ 1671 crs = aml_resource_template(); 1672 aml_append(crs, 1673 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1674 0x0000, 0x0, root_bus_limit, 1675 0x0000, root_bus_limit + 1)); 1676 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1677 1678 aml_append(crs, 1679 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1680 AML_POS_DECODE, AML_ENTIRE_RANGE, 1681 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1682 1683 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1684 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1685 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1686 aml_append(crs, 1687 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1688 AML_POS_DECODE, AML_ENTIRE_RANGE, 1689 0x0000, entry->base, entry->limit, 1690 0x0000, entry->limit - entry->base + 1)); 1691 } 1692 1693 aml_append(crs, 1694 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1695 AML_CACHEABLE, AML_READ_WRITE, 1696 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1697 1698 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1699 range_lob(pci_hole), 1700 range_upb(pci_hole)); 1701 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1702 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1703 aml_append(crs, 1704 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1705 AML_NON_CACHEABLE, AML_READ_WRITE, 1706 0, entry->base, entry->limit, 1707 0, entry->limit - entry->base + 1)); 1708 } 1709 1710 if (!range_is_empty(pci_hole64)) { 1711 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1712 range_lob(pci_hole64), 1713 range_upb(pci_hole64)); 1714 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1715 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1716 aml_append(crs, 1717 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1718 AML_MAX_FIXED, 1719 AML_CACHEABLE, AML_READ_WRITE, 1720 0, entry->base, entry->limit, 1721 0, entry->limit - entry->base + 1)); 1722 } 1723 } 1724 1725 if (TPM_IS_TIS_ISA(tpm_find())) { 1726 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1727 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1728 } 1729 aml_append(scope, aml_name_decl("_CRS", crs)); 1730 1731 /* reserve GPE0 block resources */ 1732 dev = aml_device("GPE0"); 1733 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1734 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1735 /* device present, functioning, decoding, not shown in UI */ 1736 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1737 crs = aml_resource_template(); 1738 aml_append(crs, 1739 aml_io( 1740 AML_DECODE16, 1741 pm->fadt.gpe0_blk.address, 1742 pm->fadt.gpe0_blk.address, 1743 1, 1744 pm->fadt.gpe0_blk.bit_width / 8) 1745 ); 1746 aml_append(dev, aml_name_decl("_CRS", crs)); 1747 aml_append(scope, dev); 1748 1749 crs_range_set_free(&crs_range_set); 1750 1751 /* reserve PCIHP resources */ 1752 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1753 dev = aml_device("PHPR"); 1754 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1755 aml_append(dev, 1756 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1757 /* device present, functioning, decoding, not shown in UI */ 1758 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1759 crs = aml_resource_template(); 1760 aml_append(crs, 1761 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1762 pm->pcihp_io_len) 1763 ); 1764 aml_append(dev, aml_name_decl("_CRS", crs)); 1765 aml_append(scope, dev); 1766 } 1767 aml_append(dsdt, scope); 1768 1769 /* create S3_ / S4_ / S5_ packages if necessary */ 1770 scope = aml_scope("\\"); 1771 if (!pm->s3_disabled) { 1772 pkg = aml_package(4); 1773 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1774 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1775 aml_append(pkg, aml_int(0)); /* reserved */ 1776 aml_append(pkg, aml_int(0)); /* reserved */ 1777 aml_append(scope, aml_name_decl("_S3", pkg)); 1778 } 1779 1780 if (!pm->s4_disabled) { 1781 pkg = aml_package(4); 1782 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1783 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1784 aml_append(pkg, aml_int(pm->s4_val)); 1785 aml_append(pkg, aml_int(0)); /* reserved */ 1786 aml_append(pkg, aml_int(0)); /* reserved */ 1787 aml_append(scope, aml_name_decl("_S4", pkg)); 1788 } 1789 1790 pkg = aml_package(4); 1791 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1792 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1793 aml_append(pkg, aml_int(0)); /* reserved */ 1794 aml_append(pkg, aml_int(0)); /* reserved */ 1795 aml_append(scope, aml_name_decl("_S5", pkg)); 1796 aml_append(dsdt, scope); 1797 1798 /* create fw_cfg node, unconditionally */ 1799 { 1800 scope = aml_scope("\\_SB.PCI0"); 1801 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1802 aml_append(dsdt, scope); 1803 } 1804 1805 if (misc->applesmc_io_base) { 1806 scope = aml_scope("\\_SB.PCI0.ISA"); 1807 dev = aml_device("SMC"); 1808 1809 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1810 /* device present, functioning, decoding, not shown in UI */ 1811 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1812 1813 crs = aml_resource_template(); 1814 aml_append(crs, 1815 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1816 0x01, APPLESMC_MAX_DATA_LENGTH) 1817 ); 1818 aml_append(crs, aml_irq_no_flags(6)); 1819 aml_append(dev, aml_name_decl("_CRS", crs)); 1820 1821 aml_append(scope, dev); 1822 aml_append(dsdt, scope); 1823 } 1824 1825 if (misc->pvpanic_port) { 1826 scope = aml_scope("\\_SB.PCI0.ISA"); 1827 1828 dev = aml_device("PEVT"); 1829 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1830 1831 crs = aml_resource_template(); 1832 aml_append(crs, 1833 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1834 ); 1835 aml_append(dev, aml_name_decl("_CRS", crs)); 1836 1837 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1838 aml_int(misc->pvpanic_port), 1)); 1839 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1840 aml_append(field, aml_named_field("PEPT", 8)); 1841 aml_append(dev, field); 1842 1843 /* device present, functioning, decoding, shown in UI */ 1844 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1845 1846 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1847 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1848 aml_append(method, aml_return(aml_local(0))); 1849 aml_append(dev, method); 1850 1851 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1852 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1853 aml_append(dev, method); 1854 1855 aml_append(scope, dev); 1856 aml_append(dsdt, scope); 1857 } 1858 1859 sb_scope = aml_scope("\\_SB"); 1860 { 1861 Object *pci_host; 1862 PCIBus *bus = NULL; 1863 1864 pci_host = acpi_get_i386_pci_host(); 1865 if (pci_host) { 1866 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1867 } 1868 1869 if (bus) { 1870 Aml *scope = aml_scope("PCI0"); 1871 /* Scan all PCI buses. Generate tables to support hotplug. */ 1872 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1873 1874 if (TPM_IS_TIS_ISA(tpm)) { 1875 if (misc->tpm_version == TPM_VERSION_2_0) { 1876 dev = aml_device("TPM"); 1877 aml_append(dev, aml_name_decl("_HID", 1878 aml_string("MSFT0101"))); 1879 } else { 1880 dev = aml_device("ISA.TPM"); 1881 aml_append(dev, aml_name_decl("_HID", 1882 aml_eisaid("PNP0C31"))); 1883 } 1884 1885 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1886 crs = aml_resource_template(); 1887 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1888 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1889 /* 1890 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1891 Rewrite to take IRQ from TPM device model and 1892 fix default IRQ value there to use some unused IRQ 1893 */ 1894 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1895 aml_append(dev, aml_name_decl("_CRS", crs)); 1896 1897 tpm_build_ppi_acpi(tpm, dev); 1898 1899 aml_append(scope, dev); 1900 } 1901 1902 aml_append(sb_scope, scope); 1903 } 1904 } 1905 1906 if (TPM_IS_CRB(tpm)) { 1907 dev = aml_device("TPM"); 1908 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1909 crs = aml_resource_template(); 1910 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1911 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1912 aml_append(dev, aml_name_decl("_CRS", crs)); 1913 1914 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1915 1916 tpm_build_ppi_acpi(tpm, dev); 1917 1918 aml_append(sb_scope, dev); 1919 } 1920 1921 aml_append(dsdt, sb_scope); 1922 1923 /* copy AML table into ACPI tables blob and patch header there */ 1924 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1925 build_header(linker, table_data, 1926 (void *)(table_data->data + table_data->len - dsdt->buf->len), 1927 "DSDT", dsdt->buf->len, 1, NULL, NULL); 1928 free_aml_allocator(); 1929 } 1930 1931 static void 1932 build_hpet(GArray *table_data, BIOSLinker *linker) 1933 { 1934 Acpi20Hpet *hpet; 1935 1936 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1937 /* Note timer_block_id value must be kept in sync with value advertised by 1938 * emulated hpet 1939 */ 1940 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1941 hpet->addr.address = cpu_to_le64(HPET_BASE); 1942 build_header(linker, table_data, 1943 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 1944 } 1945 1946 static void 1947 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 1948 { 1949 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1950 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 1951 unsigned log_addr_offset = 1952 (char *)&tcpa->log_area_start_address - table_data->data; 1953 1954 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1955 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1956 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 1957 1958 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1959 false /* high memory */); 1960 1961 /* log area start address to be filled by Guest linker */ 1962 bios_linker_loader_add_pointer(linker, 1963 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 1964 ACPI_BUILD_TPMLOG_FILE, 0); 1965 1966 build_header(linker, table_data, 1967 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 1968 } 1969 1970 #define HOLE_640K_START (640 * KiB) 1971 #define HOLE_640K_END (1 * MiB) 1972 1973 static void 1974 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1975 { 1976 AcpiSystemResourceAffinityTable *srat; 1977 AcpiSratMemoryAffinity *numamem; 1978 1979 int i; 1980 int srat_start, numa_start, slots; 1981 uint64_t mem_len, mem_base, next_base; 1982 MachineClass *mc = MACHINE_GET_CLASS(machine); 1983 X86MachineState *x86ms = X86_MACHINE(machine); 1984 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1985 PCMachineState *pcms = PC_MACHINE(machine); 1986 ram_addr_t hotplugabble_address_space_size = 1987 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1988 NULL); 1989 1990 srat_start = table_data->len; 1991 1992 srat = acpi_data_push(table_data, sizeof *srat); 1993 srat->reserved1 = cpu_to_le32(1); 1994 1995 for (i = 0; i < apic_ids->len; i++) { 1996 int node_id = apic_ids->cpus[i].props.node_id; 1997 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1998 1999 if (apic_id < 255) { 2000 AcpiSratProcessorAffinity *core; 2001 2002 core = acpi_data_push(table_data, sizeof *core); 2003 core->type = ACPI_SRAT_PROCESSOR_APIC; 2004 core->length = sizeof(*core); 2005 core->local_apic_id = apic_id; 2006 core->proximity_lo = node_id; 2007 memset(core->proximity_hi, 0, 3); 2008 core->local_sapic_eid = 0; 2009 core->flags = cpu_to_le32(1); 2010 } else { 2011 AcpiSratProcessorX2ApicAffinity *core; 2012 2013 core = acpi_data_push(table_data, sizeof *core); 2014 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2015 core->length = sizeof(*core); 2016 core->x2apic_id = cpu_to_le32(apic_id); 2017 core->proximity_domain = cpu_to_le32(node_id); 2018 core->flags = cpu_to_le32(1); 2019 } 2020 } 2021 2022 2023 /* the memory map is a bit tricky, it contains at least one hole 2024 * from 640k-1M and possibly another one from 3.5G-4G. 2025 */ 2026 next_base = 0; 2027 numa_start = table_data->len; 2028 2029 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2030 mem_base = next_base; 2031 mem_len = pcms->node_mem[i - 1]; 2032 next_base = mem_base + mem_len; 2033 2034 /* Cut out the 640K hole */ 2035 if (mem_base <= HOLE_640K_START && 2036 next_base > HOLE_640K_START) { 2037 mem_len -= next_base - HOLE_640K_START; 2038 if (mem_len > 0) { 2039 numamem = acpi_data_push(table_data, sizeof *numamem); 2040 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2041 MEM_AFFINITY_ENABLED); 2042 } 2043 2044 /* Check for the rare case: 640K < RAM < 1M */ 2045 if (next_base <= HOLE_640K_END) { 2046 next_base = HOLE_640K_END; 2047 continue; 2048 } 2049 mem_base = HOLE_640K_END; 2050 mem_len = next_base - HOLE_640K_END; 2051 } 2052 2053 /* Cut out the ACPI_PCI hole */ 2054 if (mem_base <= x86ms->below_4g_mem_size && 2055 next_base > x86ms->below_4g_mem_size) { 2056 mem_len -= next_base - x86ms->below_4g_mem_size; 2057 if (mem_len > 0) { 2058 numamem = acpi_data_push(table_data, sizeof *numamem); 2059 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2060 MEM_AFFINITY_ENABLED); 2061 } 2062 mem_base = 1ULL << 32; 2063 mem_len = next_base - x86ms->below_4g_mem_size; 2064 next_base = mem_base + mem_len; 2065 } 2066 2067 if (mem_len > 0) { 2068 numamem = acpi_data_push(table_data, sizeof *numamem); 2069 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2070 MEM_AFFINITY_ENABLED); 2071 } 2072 } 2073 2074 if (machine->nvdimms_state->is_enabled) { 2075 nvdimm_build_srat(table_data); 2076 } 2077 2078 slots = (table_data->len - numa_start) / sizeof *numamem; 2079 for (; slots < pcms->numa_nodes + 2; slots++) { 2080 numamem = acpi_data_push(table_data, sizeof *numamem); 2081 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2082 } 2083 2084 /* 2085 * Entry is required for Windows to enable memory hotplug in OS 2086 * and for Linux to enable SWIOTLB when booted with less than 2087 * 4G of RAM. Windows works better if the entry sets proximity 2088 * to the highest NUMA node in the machine. 2089 * Memory devices may override proximity set by this entry, 2090 * providing _PXM method if necessary. 2091 */ 2092 if (hotplugabble_address_space_size) { 2093 numamem = acpi_data_push(table_data, sizeof *numamem); 2094 build_srat_memory(numamem, machine->device_memory->base, 2095 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2096 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2097 } 2098 2099 build_header(linker, table_data, 2100 (void *)(table_data->data + srat_start), 2101 "SRAT", 2102 table_data->len - srat_start, 1, NULL, NULL); 2103 } 2104 2105 /* 2106 * VT-d spec 8.1 DMA Remapping Reporting Structure 2107 * (version Oct. 2014 or later) 2108 */ 2109 static void 2110 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2111 { 2112 int dmar_start = table_data->len; 2113 2114 AcpiTableDmar *dmar; 2115 AcpiDmarHardwareUnit *drhd; 2116 AcpiDmarRootPortATS *atsr; 2117 uint8_t dmar_flags = 0; 2118 X86IOMMUState *iommu = x86_iommu_get_default(); 2119 AcpiDmarDeviceScope *scope = NULL; 2120 /* Root complex IOAPIC use one path[0] only */ 2121 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2122 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2123 2124 assert(iommu); 2125 if (x86_iommu_ir_supported(iommu)) { 2126 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2127 } 2128 2129 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2130 dmar->host_address_width = intel_iommu->aw_bits - 1; 2131 dmar->flags = dmar_flags; 2132 2133 /* DMAR Remapping Hardware Unit Definition structure */ 2134 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2135 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2136 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2137 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2138 drhd->pci_segment = cpu_to_le16(0); 2139 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2140 2141 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2142 * 8.3.1 (version Oct. 2014 or later). */ 2143 scope = &drhd->scope[0]; 2144 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2145 scope->length = ioapic_scope_size; 2146 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2147 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2148 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2149 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2150 2151 if (iommu->dt_supported) { 2152 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2153 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2154 atsr->length = cpu_to_le16(sizeof(*atsr)); 2155 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2156 atsr->pci_segment = cpu_to_le16(0); 2157 } 2158 2159 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2160 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2161 } 2162 2163 /* 2164 * Windows ACPI Emulated Devices Table 2165 * (Version 1.0 - April 6, 2009) 2166 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2167 * 2168 * Helpful to speedup Windows guests and ignored by others. 2169 */ 2170 static void 2171 build_waet(GArray *table_data, BIOSLinker *linker) 2172 { 2173 int waet_start = table_data->len; 2174 2175 /* WAET header */ 2176 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2177 /* 2178 * Set "ACPI PM timer good" flag. 2179 * 2180 * Tells Windows guests that our ACPI PM timer is reliable in the 2181 * sense that guest can read it only once to obtain a reliable value. 2182 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2183 */ 2184 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2185 2186 build_header(linker, table_data, (void *)(table_data->data + waet_start), 2187 "WAET", table_data->len - waet_start, 1, NULL, NULL); 2188 } 2189 2190 /* 2191 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2192 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2193 */ 2194 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2195 2196 /* 2197 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2198 * necessary for the PCI topology. 2199 */ 2200 static void 2201 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2202 { 2203 GArray *table_data = opaque; 2204 uint32_t entry; 2205 2206 /* "Select" IVHD entry, type 0x2 */ 2207 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2208 build_append_int_noprefix(table_data, entry, 4); 2209 2210 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2211 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2212 uint8_t sec = pci_bus_num(sec_bus); 2213 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2214 2215 if (pci_bus_is_express(sec_bus)) { 2216 /* 2217 * Walk the bus if there are subordinates, otherwise use a range 2218 * to cover an entire leaf bus. We could potentially also use a 2219 * range for traversed buses, but we'd need to take care not to 2220 * create both Select and Range entries covering the same device. 2221 * This is easier and potentially more compact. 2222 * 2223 * An example bare metal system seems to use Select entries for 2224 * root ports without a slot (ie. built-ins) and Range entries 2225 * when there is a slot. The same system also only hard-codes 2226 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2227 * making no effort to support nested bridges. We attempt to 2228 * be more thorough here. 2229 */ 2230 if (sec == sub) { /* leaf bus */ 2231 /* "Start of Range" IVHD entry, type 0x3 */ 2232 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2233 build_append_int_noprefix(table_data, entry, 4); 2234 /* "End of Range" IVHD entry, type 0x4 */ 2235 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2236 build_append_int_noprefix(table_data, entry, 4); 2237 } else { 2238 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2239 } 2240 } else { 2241 /* 2242 * If the secondary bus is conventional, then we need to create an 2243 * Alias range for everything downstream. The range covers the 2244 * first devfn on the secondary bus to the last devfn on the 2245 * subordinate bus. The alias target depends on legacy versus 2246 * express bridges, just as in pci_device_iommu_address_space(). 2247 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2248 */ 2249 uint16_t dev_id_a, dev_id_b; 2250 2251 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2252 2253 if (pci_is_express(dev) && 2254 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2255 dev_id_b = dev_id_a; 2256 } else { 2257 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2258 } 2259 2260 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2261 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2262 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2263 2264 /* "End of Range" IVHD entry, type 0x4 */ 2265 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2266 build_append_int_noprefix(table_data, entry, 4); 2267 } 2268 } 2269 } 2270 2271 /* For all PCI host bridges, walk and insert IVHD entries */ 2272 static int 2273 ivrs_host_bridges(Object *obj, void *opaque) 2274 { 2275 GArray *ivhd_blob = opaque; 2276 2277 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2278 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2279 2280 if (bus) { 2281 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); 2282 } 2283 } 2284 2285 return 0; 2286 } 2287 2288 static void 2289 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2290 { 2291 int ivhd_table_len = 24; 2292 int iommu_start = table_data->len; 2293 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2294 GArray *ivhd_blob = g_array_new(false, true, 1); 2295 2296 /* IVRS header */ 2297 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2298 /* IVinfo - IO virtualization information common to all 2299 * IOMMU units in a system 2300 */ 2301 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2302 /* reserved */ 2303 build_append_int_noprefix(table_data, 0, 8); 2304 2305 /* IVHD definition - type 10h */ 2306 build_append_int_noprefix(table_data, 0x10, 1); 2307 /* virtualization flags */ 2308 build_append_int_noprefix(table_data, 2309 (1UL << 0) | /* HtTunEn */ 2310 (1UL << 4) | /* iotblSup */ 2311 (1UL << 6) | /* PrefSup */ 2312 (1UL << 7), /* PPRSup */ 2313 1); 2314 2315 /* 2316 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2317 * complete set of IVHD entries. Do this into a separate blob so that we 2318 * can calculate the total IVRS table length here and then append the new 2319 * blob further below. Fall back to an entry covering all devices, which 2320 * is sufficient when no aliases are present. 2321 */ 2322 object_child_foreach_recursive(object_get_root(), 2323 ivrs_host_bridges, ivhd_blob); 2324 2325 if (!ivhd_blob->len) { 2326 /* 2327 * Type 1 device entry reporting all devices 2328 * These are 4-byte device entries currently reporting the range of 2329 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2330 */ 2331 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2332 } 2333 2334 ivhd_table_len += ivhd_blob->len; 2335 2336 /* 2337 * When interrupt remapping is supported, we add a special IVHD device 2338 * for type IO-APIC. 2339 */ 2340 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2341 ivhd_table_len += 8; 2342 } 2343 2344 /* IVHD length */ 2345 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2346 /* DeviceID */ 2347 build_append_int_noprefix(table_data, s->devid, 2); 2348 /* Capability offset */ 2349 build_append_int_noprefix(table_data, s->capab_offset, 2); 2350 /* IOMMU base address */ 2351 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2352 /* PCI Segment Group */ 2353 build_append_int_noprefix(table_data, 0, 2); 2354 /* IOMMU info */ 2355 build_append_int_noprefix(table_data, 0, 2); 2356 /* IOMMU Feature Reporting */ 2357 build_append_int_noprefix(table_data, 2358 (48UL << 30) | /* HATS */ 2359 (48UL << 28) | /* GATS */ 2360 (1UL << 2) | /* GTSup */ 2361 (1UL << 6), /* GASup */ 2362 4); 2363 2364 /* IVHD entries as found above */ 2365 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2366 g_array_free(ivhd_blob, TRUE); 2367 2368 /* 2369 * Add a special IVHD device type. 2370 * Refer to spec - Table 95: IVHD device entry type codes 2371 * 2372 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2373 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2374 */ 2375 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2376 build_append_int_noprefix(table_data, 2377 (0x1ull << 56) | /* type IOAPIC */ 2378 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2379 0x48, /* special device */ 2380 8); 2381 } 2382 2383 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2384 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2385 } 2386 2387 typedef 2388 struct AcpiBuildState { 2389 /* Copy of table in RAM (for patching). */ 2390 MemoryRegion *table_mr; 2391 /* Is table patched? */ 2392 uint8_t patched; 2393 void *rsdp; 2394 MemoryRegion *rsdp_mr; 2395 MemoryRegion *linker_mr; 2396 } AcpiBuildState; 2397 2398 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2399 { 2400 Object *pci_host; 2401 QObject *o; 2402 2403 pci_host = acpi_get_i386_pci_host(); 2404 g_assert(pci_host); 2405 2406 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2407 if (!o) { 2408 return false; 2409 } 2410 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2411 qobject_unref(o); 2412 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2413 return false; 2414 } 2415 2416 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2417 assert(o); 2418 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2419 qobject_unref(o); 2420 return true; 2421 } 2422 2423 static 2424 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2425 { 2426 PCMachineState *pcms = PC_MACHINE(machine); 2427 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2428 X86MachineState *x86ms = X86_MACHINE(machine); 2429 GArray *table_offsets; 2430 unsigned facs, dsdt, rsdt, fadt; 2431 AcpiPmInfo pm; 2432 AcpiMiscInfo misc; 2433 AcpiMcfgInfo mcfg; 2434 Range pci_hole, pci_hole64; 2435 uint8_t *u; 2436 size_t aml_len = 0; 2437 GArray *tables_blob = tables->table_data; 2438 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2439 Object *vmgenid_dev; 2440 2441 acpi_get_pm_info(machine, &pm); 2442 acpi_get_misc_info(&misc); 2443 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2444 acpi_get_slic_oem(&slic_oem); 2445 2446 table_offsets = g_array_new(false, true /* clear */, 2447 sizeof(uint32_t)); 2448 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2449 2450 bios_linker_loader_alloc(tables->linker, 2451 ACPI_BUILD_TABLE_FILE, tables_blob, 2452 64 /* Ensure FACS is aligned */, 2453 false /* high memory */); 2454 2455 /* 2456 * FACS is pointed to by FADT. 2457 * We place it first since it's the only table that has alignment 2458 * requirements. 2459 */ 2460 facs = tables_blob->len; 2461 build_facs(tables_blob); 2462 2463 /* DSDT is pointed to by FADT */ 2464 dsdt = tables_blob->len; 2465 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2466 &pci_hole, &pci_hole64, machine); 2467 2468 /* Count the size of the DSDT and SSDT, we will need it for legacy 2469 * sizing of ACPI tables. 2470 */ 2471 aml_len += tables_blob->len - dsdt; 2472 2473 /* ACPI tables pointed to by RSDT */ 2474 fadt = tables_blob->len; 2475 acpi_add_table(table_offsets, tables_blob); 2476 pm.fadt.facs_tbl_offset = &facs; 2477 pm.fadt.dsdt_tbl_offset = &dsdt; 2478 pm.fadt.xdsdt_tbl_offset = &dsdt; 2479 build_fadt(tables_blob, tables->linker, &pm.fadt, 2480 slic_oem.id, slic_oem.table_id); 2481 aml_len += tables_blob->len - fadt; 2482 2483 acpi_add_table(table_offsets, tables_blob); 2484 acpi_build_madt(tables_blob, tables->linker, x86ms, 2485 ACPI_DEVICE_IF(x86ms->acpi_dev)); 2486 2487 vmgenid_dev = find_vmgenid_dev(); 2488 if (vmgenid_dev) { 2489 acpi_add_table(table_offsets, tables_blob); 2490 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2491 tables->vmgenid, tables->linker); 2492 } 2493 2494 if (misc.has_hpet) { 2495 acpi_add_table(table_offsets, tables_blob); 2496 build_hpet(tables_blob, tables->linker); 2497 } 2498 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2499 if (misc.tpm_version == TPM_VERSION_1_2) { 2500 acpi_add_table(table_offsets, tables_blob); 2501 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2502 } else { /* TPM_VERSION_2_0 */ 2503 acpi_add_table(table_offsets, tables_blob); 2504 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2505 } 2506 } 2507 if (pcms->numa_nodes) { 2508 acpi_add_table(table_offsets, tables_blob); 2509 build_srat(tables_blob, tables->linker, machine); 2510 if (machine->numa_state->have_numa_distance) { 2511 acpi_add_table(table_offsets, tables_blob); 2512 build_slit(tables_blob, tables->linker, machine); 2513 } 2514 if (machine->numa_state->hmat_enabled) { 2515 acpi_add_table(table_offsets, tables_blob); 2516 build_hmat(tables_blob, tables->linker, machine->numa_state); 2517 } 2518 } 2519 if (acpi_get_mcfg(&mcfg)) { 2520 acpi_add_table(table_offsets, tables_blob); 2521 build_mcfg(tables_blob, tables->linker, &mcfg); 2522 } 2523 if (x86_iommu_get_default()) { 2524 IommuType IOMMUType = x86_iommu_get_type(); 2525 if (IOMMUType == TYPE_AMD) { 2526 acpi_add_table(table_offsets, tables_blob); 2527 build_amd_iommu(tables_blob, tables->linker); 2528 } else if (IOMMUType == TYPE_INTEL) { 2529 acpi_add_table(table_offsets, tables_blob); 2530 build_dmar_q35(tables_blob, tables->linker); 2531 } 2532 } 2533 if (machine->nvdimms_state->is_enabled) { 2534 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2535 machine->nvdimms_state, machine->ram_slots); 2536 } 2537 2538 acpi_add_table(table_offsets, tables_blob); 2539 build_waet(tables_blob, tables->linker); 2540 2541 /* Add tables supplied by user (if any) */ 2542 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2543 unsigned len = acpi_table_len(u); 2544 2545 acpi_add_table(table_offsets, tables_blob); 2546 g_array_append_vals(tables_blob, u, len); 2547 } 2548 2549 /* RSDT is pointed to by RSDP */ 2550 rsdt = tables_blob->len; 2551 build_rsdt(tables_blob, tables->linker, table_offsets, 2552 slic_oem.id, slic_oem.table_id); 2553 2554 /* RSDP is in FSEG memory, so allocate it separately */ 2555 { 2556 AcpiRsdpData rsdp_data = { 2557 .revision = 0, 2558 .oem_id = ACPI_BUILD_APPNAME6, 2559 .xsdt_tbl_offset = NULL, 2560 .rsdt_tbl_offset = &rsdt, 2561 }; 2562 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2563 if (!pcmc->rsdp_in_ram) { 2564 /* We used to allocate some extra space for RSDP revision 2 but 2565 * only used the RSDP revision 0 space. The extra bytes were 2566 * zeroed out and not used. 2567 * Here we continue wasting those extra 16 bytes to make sure we 2568 * don't break migration for machine types 2.2 and older due to 2569 * RSDP blob size mismatch. 2570 */ 2571 build_append_int_noprefix(tables->rsdp, 0, 16); 2572 } 2573 } 2574 2575 /* We'll expose it all to Guest so we want to reduce 2576 * chance of size changes. 2577 * 2578 * We used to align the tables to 4k, but of course this would 2579 * too simple to be enough. 4k turned out to be too small an 2580 * alignment very soon, and in fact it is almost impossible to 2581 * keep the table size stable for all (max_cpus, max_memory_slots) 2582 * combinations. So the table size is always 64k for pc-i440fx-2.1 2583 * and we give an error if the table grows beyond that limit. 2584 * 2585 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2586 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2587 * than 2.0 and we can always pad the smaller tables with zeros. We can 2588 * then use the exact size of the 2.0 tables. 2589 * 2590 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2591 */ 2592 if (pcmc->legacy_acpi_table_size) { 2593 /* Subtracting aml_len gives the size of fixed tables. Then add the 2594 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2595 */ 2596 int legacy_aml_len = 2597 pcmc->legacy_acpi_table_size + 2598 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2599 int legacy_table_size = 2600 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2601 ACPI_BUILD_ALIGN_SIZE); 2602 if (tables_blob->len > legacy_table_size) { 2603 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2604 warn_report("ACPI table size %u exceeds %d bytes," 2605 " migration may not work", 2606 tables_blob->len, legacy_table_size); 2607 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2608 " or PCI bridges."); 2609 } 2610 g_array_set_size(tables_blob, legacy_table_size); 2611 } else { 2612 /* Make sure we have a buffer in case we need to resize the tables. */ 2613 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2614 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2615 warn_report("ACPI table size %u exceeds %d bytes," 2616 " migration may not work", 2617 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2618 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2619 " or PCI bridges."); 2620 } 2621 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2622 } 2623 2624 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2625 2626 /* Cleanup memory that's no longer used. */ 2627 g_array_free(table_offsets, true); 2628 } 2629 2630 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2631 { 2632 uint32_t size = acpi_data_len(data); 2633 2634 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2635 memory_region_ram_resize(mr, size, &error_abort); 2636 2637 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2638 memory_region_set_dirty(mr, 0, size); 2639 } 2640 2641 static void acpi_build_update(void *build_opaque) 2642 { 2643 AcpiBuildState *build_state = build_opaque; 2644 AcpiBuildTables tables; 2645 2646 /* No state to update or already patched? Nothing to do. */ 2647 if (!build_state || build_state->patched) { 2648 return; 2649 } 2650 build_state->patched = 1; 2651 2652 acpi_build_tables_init(&tables); 2653 2654 acpi_build(&tables, MACHINE(qdev_get_machine())); 2655 2656 acpi_ram_update(build_state->table_mr, tables.table_data); 2657 2658 if (build_state->rsdp) { 2659 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2660 } else { 2661 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2662 } 2663 2664 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2665 acpi_build_tables_cleanup(&tables, true); 2666 } 2667 2668 static void acpi_build_reset(void *build_opaque) 2669 { 2670 AcpiBuildState *build_state = build_opaque; 2671 build_state->patched = 0; 2672 } 2673 2674 static const VMStateDescription vmstate_acpi_build = { 2675 .name = "acpi_build", 2676 .version_id = 1, 2677 .minimum_version_id = 1, 2678 .fields = (VMStateField[]) { 2679 VMSTATE_UINT8(patched, AcpiBuildState), 2680 VMSTATE_END_OF_LIST() 2681 }, 2682 }; 2683 2684 void acpi_setup(void) 2685 { 2686 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2687 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2688 X86MachineState *x86ms = X86_MACHINE(pcms); 2689 AcpiBuildTables tables; 2690 AcpiBuildState *build_state; 2691 Object *vmgenid_dev; 2692 TPMIf *tpm; 2693 static FwCfgTPMConfig tpm_config; 2694 2695 if (!x86ms->fw_cfg) { 2696 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2697 return; 2698 } 2699 2700 if (!pcms->acpi_build_enabled) { 2701 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2702 return; 2703 } 2704 2705 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2706 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2707 return; 2708 } 2709 2710 build_state = g_malloc0(sizeof *build_state); 2711 2712 acpi_build_tables_init(&tables); 2713 acpi_build(&tables, MACHINE(pcms)); 2714 2715 /* Now expose it all to Guest */ 2716 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2717 build_state, tables.table_data, 2718 ACPI_BUILD_TABLE_FILE, 2719 ACPI_BUILD_TABLE_MAX_SIZE); 2720 assert(build_state->table_mr != NULL); 2721 2722 build_state->linker_mr = 2723 acpi_add_rom_blob(acpi_build_update, build_state, 2724 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 2725 2726 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2727 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2728 2729 tpm = tpm_find(); 2730 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2731 tpm_config = (FwCfgTPMConfig) { 2732 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2733 .tpm_version = tpm_get_version(tpm), 2734 .tpmppi_version = TPM_PPI_VERSION_1_30 2735 }; 2736 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2737 &tpm_config, sizeof tpm_config); 2738 } 2739 2740 vmgenid_dev = find_vmgenid_dev(); 2741 if (vmgenid_dev) { 2742 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2743 tables.vmgenid); 2744 } 2745 2746 if (!pcmc->rsdp_in_ram) { 2747 /* 2748 * Keep for compatibility with old machine types. 2749 * Though RSDP is small, its contents isn't immutable, so 2750 * we'll update it along with the rest of tables on guest access. 2751 */ 2752 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2753 2754 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2755 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2756 acpi_build_update, NULL, build_state, 2757 build_state->rsdp, rsdp_size, true); 2758 build_state->rsdp_mr = NULL; 2759 } else { 2760 build_state->rsdp = NULL; 2761 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2762 build_state, tables.rsdp, 2763 ACPI_BUILD_RSDP_FILE, 0); 2764 } 2765 2766 qemu_register_reset(acpi_build_reset, build_state); 2767 acpi_build_reset(build_state); 2768 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2769 2770 /* Cleanup tables but don't free the memory: we track it 2771 * in build_state. 2772 */ 2773 acpi_build_tables_cleanup(&tables, false); 2774 } 2775