1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/core/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/block/fdc.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/boards.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/rtc/mc146818rtc_regs.h" 49 #include "migration/vmstate.h" 50 #include "hw/mem/memory-device.h" 51 #include "hw/mem/nvdimm.h" 52 #include "sysemu/numa.h" 53 #include "sysemu/reset.h" 54 #include "hw/hyperv/vmbus-bridge.h" 55 56 /* Supported chipsets: */ 57 #include "hw/southbridge/piix.h" 58 #include "hw/acpi/pcihp.h" 59 #include "hw/i386/fw_cfg.h" 60 #include "hw/i386/ich9.h" 61 #include "hw/pci/pci_bus.h" 62 #include "hw/pci-host/q35.h" 63 #include "hw/i386/x86-iommu.h" 64 65 #include "hw/acpi/aml-build.h" 66 #include "hw/acpi/utils.h" 67 #include "hw/acpi/pci.h" 68 69 #include "qom/qom-qobject.h" 70 #include "hw/i386/amd_iommu.h" 71 #include "hw/i386/intel_iommu.h" 72 73 #include "hw/acpi/ipmi.h" 74 #include "hw/acpi/hmat.h" 75 76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 78 * a little bit, there should be plenty of free space since the DSDT 79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 80 */ 81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 82 #define ACPI_BUILD_ALIGN_SIZE 0x1000 83 84 #define ACPI_BUILD_TABLE_SIZE 0x20000 85 86 /* #define DEBUG_ACPI_BUILD */ 87 #ifdef DEBUG_ACPI_BUILD 88 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 90 #else 91 #define ACPI_BUILD_DPRINTF(fmt, ...) 92 #endif 93 94 typedef struct AcpiPmInfo { 95 bool s3_disabled; 96 bool s4_disabled; 97 bool pcihp_bridge_en; 98 bool smi_on_cpuhp; 99 bool pcihp_root_en; 100 uint8_t s4_val; 101 AcpiFadtData fadt; 102 uint16_t cpu_hp_io_base; 103 uint16_t pcihp_io_base; 104 uint16_t pcihp_io_len; 105 } AcpiPmInfo; 106 107 typedef struct AcpiMiscInfo { 108 bool is_piix4; 109 bool has_hpet; 110 TPMVersion tpm_version; 111 const unsigned char *dsdt_code; 112 unsigned dsdt_size; 113 uint16_t pvpanic_port; 114 uint16_t applesmc_io_base; 115 } AcpiMiscInfo; 116 117 typedef struct AcpiBuildPciBusHotplugState { 118 GArray *device_table; 119 GArray *notify_table; 120 struct AcpiBuildPciBusHotplugState *parent; 121 bool pcihp_bridge_en; 122 } AcpiBuildPciBusHotplugState; 123 124 typedef struct FwCfgTPMConfig { 125 uint32_t tpmppi_address; 126 uint8_t tpm_version; 127 uint8_t tpmppi_version; 128 } QEMU_PACKED FwCfgTPMConfig; 129 130 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 131 132 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 133 .space_id = AML_AS_SYSTEM_IO, 134 .address = NVDIMM_ACPI_IO_BASE, 135 .bit_width = NVDIMM_ACPI_IO_LEN << 3 136 }; 137 138 static void init_common_fadt_data(MachineState *ms, Object *o, 139 AcpiFadtData *data) 140 { 141 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 142 AmlAddressSpace as = AML_AS_SYSTEM_IO; 143 AcpiFadtData fadt = { 144 .rev = 3, 145 .flags = 146 (1 << ACPI_FADT_F_WBINVD) | 147 (1 << ACPI_FADT_F_PROC_C1) | 148 (1 << ACPI_FADT_F_SLP_BUTTON) | 149 (1 << ACPI_FADT_F_RTC_S4) | 150 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 151 /* APIC destination mode ("Flat Logical") has an upper limit of 8 152 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 153 * used 154 */ 155 ((ms->smp.max_cpus > 8) ? 156 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 157 .int_model = 1 /* Multiple APIC */, 158 .rtc_century = RTC_CENTURY, 159 .plvl2_lat = 0xfff /* C2 state not supported */, 160 .plvl3_lat = 0xfff /* C3 state not supported */, 161 .smi_cmd = ACPI_PORT_SMI_CMD, 162 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 163 .acpi_enable_cmd = 164 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 165 .acpi_disable_cmd = 166 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 167 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 168 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 169 .address = io + 0x04 }, 170 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 171 .gpe0_blk = { .space_id = as, .bit_width = 172 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 173 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 174 }, 175 }; 176 *data = fadt; 177 } 178 179 static Object *object_resolve_type_unambiguous(const char *typename) 180 { 181 bool ambig; 182 Object *o = object_resolve_path_type("", typename, &ambig); 183 184 if (ambig || !o) { 185 return NULL; 186 } 187 return o; 188 } 189 190 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 191 { 192 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 193 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 194 Object *obj = piix ? piix : lpc; 195 QObject *o; 196 pm->cpu_hp_io_base = 0; 197 pm->pcihp_io_base = 0; 198 pm->pcihp_io_len = 0; 199 pm->smi_on_cpuhp = false; 200 201 assert(obj); 202 init_common_fadt_data(machine, obj, &pm->fadt); 203 if (piix) { 204 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 205 pm->fadt.rev = 1; 206 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 207 pm->pcihp_io_base = 208 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 209 pm->pcihp_io_len = 210 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 211 } 212 if (lpc) { 213 uint64_t smi_features = object_property_get_uint(lpc, 214 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 215 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 216 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 217 pm->fadt.reset_reg = r; 218 pm->fadt.reset_val = 0xf; 219 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 220 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 221 pm->smi_on_cpuhp = 222 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 223 } 224 225 /* The above need not be conditional on machine type because the reset port 226 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 227 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 228 229 /* Fill in optional s3/s4 related properties */ 230 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 231 if (o) { 232 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 233 } else { 234 pm->s3_disabled = false; 235 } 236 qobject_unref(o); 237 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 238 if (o) { 239 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 240 } else { 241 pm->s4_disabled = false; 242 } 243 qobject_unref(o); 244 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 245 if (o) { 246 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 247 } else { 248 pm->s4_val = false; 249 } 250 qobject_unref(o); 251 252 pm->pcihp_bridge_en = 253 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 254 NULL); 255 pm->pcihp_root_en = 256 object_property_get_bool(obj, "acpi-root-pci-hotplug", 257 NULL); 258 } 259 260 static void acpi_get_misc_info(AcpiMiscInfo *info) 261 { 262 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 263 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 264 assert(!!piix != !!lpc); 265 266 if (piix) { 267 info->is_piix4 = true; 268 } 269 if (lpc) { 270 info->is_piix4 = false; 271 } 272 273 info->has_hpet = hpet_find(); 274 info->tpm_version = tpm_get_version(tpm_find()); 275 info->pvpanic_port = pvpanic_port(); 276 info->applesmc_io_base = applesmc_port(); 277 } 278 279 /* 280 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 281 * On i386 arch we only have two pci hosts, so we can look only for them. 282 */ 283 static Object *acpi_get_i386_pci_host(void) 284 { 285 PCIHostState *host; 286 287 host = OBJECT_CHECK(PCIHostState, 288 object_resolve_path("/machine/i440fx", NULL), 289 TYPE_PCI_HOST_BRIDGE); 290 if (!host) { 291 host = OBJECT_CHECK(PCIHostState, 292 object_resolve_path("/machine/q35", NULL), 293 TYPE_PCI_HOST_BRIDGE); 294 } 295 296 return OBJECT(host); 297 } 298 299 static void acpi_get_pci_holes(Range *hole, Range *hole64) 300 { 301 Object *pci_host; 302 303 pci_host = acpi_get_i386_pci_host(); 304 g_assert(pci_host); 305 306 range_set_bounds1(hole, 307 object_property_get_uint(pci_host, 308 PCI_HOST_PROP_PCI_HOLE_START, 309 NULL), 310 object_property_get_uint(pci_host, 311 PCI_HOST_PROP_PCI_HOLE_END, 312 NULL)); 313 range_set_bounds1(hole64, 314 object_property_get_uint(pci_host, 315 PCI_HOST_PROP_PCI_HOLE64_START, 316 NULL), 317 object_property_get_uint(pci_host, 318 PCI_HOST_PROP_PCI_HOLE64_END, 319 NULL)); 320 } 321 322 static void acpi_align_size(GArray *blob, unsigned align) 323 { 324 /* Align size to multiple of given size. This reduces the chance 325 * we need to change size in the future (breaking cross version migration). 326 */ 327 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 328 } 329 330 /* FACS */ 331 static void 332 build_facs(GArray *table_data) 333 { 334 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 335 memcpy(&facs->signature, "FACS", 4); 336 facs->length = cpu_to_le32(sizeof(*facs)); 337 } 338 339 static void build_append_pcihp_notify_entry(Aml *method, int slot) 340 { 341 Aml *if_ctx; 342 int32_t devfn = PCI_DEVFN(slot, 0); 343 344 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 345 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 346 aml_append(method, if_ctx); 347 } 348 349 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 350 bool pcihp_bridge_en) 351 { 352 Aml *dev, *notify_method = NULL, *method; 353 QObject *bsel; 354 PCIBus *sec; 355 int i; 356 357 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 358 if (bsel) { 359 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 360 361 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 362 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 363 } 364 365 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 366 DeviceClass *dc; 367 PCIDeviceClass *pc; 368 PCIDevice *pdev = bus->devices[i]; 369 int slot = PCI_SLOT(i); 370 bool hotplug_enabled_dev; 371 bool bridge_in_acpi; 372 bool cold_plugged_bridge; 373 374 if (!pdev) { 375 if (bsel) { /* add hotplug slots for non present devices */ 376 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 377 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 378 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 379 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 380 aml_append(method, 381 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 382 ); 383 aml_append(dev, method); 384 aml_append(parent_scope, dev); 385 386 build_append_pcihp_notify_entry(notify_method, slot); 387 } 388 continue; 389 } 390 391 pc = PCI_DEVICE_GET_CLASS(pdev); 392 dc = DEVICE_GET_CLASS(pdev); 393 394 /* 395 * Cold plugged bridges aren't themselves hot-pluggable. 396 * Hotplugged bridges *are* hot-pluggable. 397 */ 398 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 399 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 400 401 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 402 403 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 404 continue; 405 } 406 407 /* start to compose PCI slot descriptor */ 408 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 409 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 410 411 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 412 /* add VGA specific AML methods */ 413 int s3d; 414 415 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 416 s3d = 3; 417 } else { 418 s3d = 0; 419 } 420 421 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 422 aml_append(method, aml_return(aml_int(0))); 423 aml_append(dev, method); 424 425 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 426 aml_append(method, aml_return(aml_int(0))); 427 aml_append(dev, method); 428 429 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 430 aml_append(method, aml_return(aml_int(s3d))); 431 aml_append(dev, method); 432 } else if (hotplug_enabled_dev) { 433 /* add _SUN/_EJ0 to make slot hotpluggable */ 434 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 435 436 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 437 aml_append(method, 438 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 439 ); 440 aml_append(dev, method); 441 442 if (bsel) { 443 build_append_pcihp_notify_entry(notify_method, slot); 444 } 445 } else if (bridge_in_acpi) { 446 /* 447 * device is coldplugged bridge, 448 * add child device descriptions into its scope 449 */ 450 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 451 452 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 453 } 454 /* slot descriptor has been composed, add it into parent context */ 455 aml_append(parent_scope, dev); 456 } 457 458 if (bsel) { 459 aml_append(parent_scope, notify_method); 460 } 461 462 /* Append PCNT method to notify about events on local and child buses. 463 * Add this method for root bus only when hotplug is enabled since DSDT 464 * expects it. 465 */ 466 if (bsel || pcihp_bridge_en) { 467 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 468 } 469 /* If bus supports hotplug select it and notify about local events */ 470 if (bsel) { 471 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 472 473 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 474 aml_append(method, 475 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 476 ); 477 aml_append(method, 478 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 479 ); 480 } 481 482 /* Notify about child bus events in any case */ 483 if (pcihp_bridge_en) { 484 QLIST_FOREACH(sec, &bus->child, sibling) { 485 int32_t devfn = sec->parent_dev->devfn; 486 487 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 488 continue; 489 } 490 491 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 492 } 493 } 494 495 if (bsel || pcihp_bridge_en) { 496 aml_append(parent_scope, method); 497 } 498 qobject_unref(bsel); 499 } 500 501 /** 502 * build_prt_entry: 503 * @link_name: link name for PCI route entry 504 * 505 * build AML package containing a PCI route entry for @link_name 506 */ 507 static Aml *build_prt_entry(const char *link_name) 508 { 509 Aml *a_zero = aml_int(0); 510 Aml *pkg = aml_package(4); 511 aml_append(pkg, a_zero); 512 aml_append(pkg, a_zero); 513 aml_append(pkg, aml_name("%s", link_name)); 514 aml_append(pkg, a_zero); 515 return pkg; 516 } 517 518 /* 519 * initialize_route - Initialize the interrupt routing rule 520 * through a specific LINK: 521 * if (lnk_idx == idx) 522 * route using link 'link_name' 523 */ 524 static Aml *initialize_route(Aml *route, const char *link_name, 525 Aml *lnk_idx, int idx) 526 { 527 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 528 Aml *pkg = build_prt_entry(link_name); 529 530 aml_append(if_ctx, aml_store(pkg, route)); 531 532 return if_ctx; 533 } 534 535 /* 536 * build_prt - Define interrupt rounting rules 537 * 538 * Returns an array of 128 routes, one for each device, 539 * based on device location. 540 * The main goal is to equaly distribute the interrupts 541 * over the 4 existing ACPI links (works only for i440fx). 542 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 543 * 544 */ 545 static Aml *build_prt(bool is_pci0_prt) 546 { 547 Aml *method, *while_ctx, *pin, *res; 548 549 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 550 res = aml_local(0); 551 pin = aml_local(1); 552 aml_append(method, aml_store(aml_package(128), res)); 553 aml_append(method, aml_store(aml_int(0), pin)); 554 555 /* while (pin < 128) */ 556 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 557 { 558 Aml *slot = aml_local(2); 559 Aml *lnk_idx = aml_local(3); 560 Aml *route = aml_local(4); 561 562 /* slot = pin >> 2 */ 563 aml_append(while_ctx, 564 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 565 /* lnk_idx = (slot + pin) & 3 */ 566 aml_append(while_ctx, 567 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 568 lnk_idx)); 569 570 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 571 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 572 if (is_pci0_prt) { 573 Aml *if_device_1, *if_pin_4, *else_pin_4; 574 575 /* device 1 is the power-management device, needs SCI */ 576 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 577 { 578 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 579 { 580 aml_append(if_pin_4, 581 aml_store(build_prt_entry("LNKS"), route)); 582 } 583 aml_append(if_device_1, if_pin_4); 584 else_pin_4 = aml_else(); 585 { 586 aml_append(else_pin_4, 587 aml_store(build_prt_entry("LNKA"), route)); 588 } 589 aml_append(if_device_1, else_pin_4); 590 } 591 aml_append(while_ctx, if_device_1); 592 } else { 593 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 594 } 595 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 596 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 597 598 /* route[0] = 0x[slot]FFFF */ 599 aml_append(while_ctx, 600 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 601 NULL), 602 aml_index(route, aml_int(0)))); 603 /* route[1] = pin & 3 */ 604 aml_append(while_ctx, 605 aml_store(aml_and(pin, aml_int(3), NULL), 606 aml_index(route, aml_int(1)))); 607 /* res[pin] = route */ 608 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 609 /* pin++ */ 610 aml_append(while_ctx, aml_increment(pin)); 611 } 612 aml_append(method, while_ctx); 613 /* return res*/ 614 aml_append(method, aml_return(res)); 615 616 return method; 617 } 618 619 typedef struct CrsRangeEntry { 620 uint64_t base; 621 uint64_t limit; 622 } CrsRangeEntry; 623 624 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 625 { 626 CrsRangeEntry *entry; 627 628 entry = g_malloc(sizeof(*entry)); 629 entry->base = base; 630 entry->limit = limit; 631 632 g_ptr_array_add(ranges, entry); 633 } 634 635 static void crs_range_free(gpointer data) 636 { 637 CrsRangeEntry *entry = (CrsRangeEntry *)data; 638 g_free(entry); 639 } 640 641 typedef struct CrsRangeSet { 642 GPtrArray *io_ranges; 643 GPtrArray *mem_ranges; 644 GPtrArray *mem_64bit_ranges; 645 } CrsRangeSet; 646 647 static void crs_range_set_init(CrsRangeSet *range_set) 648 { 649 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 650 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 651 range_set->mem_64bit_ranges = 652 g_ptr_array_new_with_free_func(crs_range_free); 653 } 654 655 static void crs_range_set_free(CrsRangeSet *range_set) 656 { 657 g_ptr_array_free(range_set->io_ranges, true); 658 g_ptr_array_free(range_set->mem_ranges, true); 659 g_ptr_array_free(range_set->mem_64bit_ranges, true); 660 } 661 662 static gint crs_range_compare(gconstpointer a, gconstpointer b) 663 { 664 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 665 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 666 667 if (entry_a->base < entry_b->base) { 668 return -1; 669 } else if (entry_a->base > entry_b->base) { 670 return 1; 671 } else { 672 return 0; 673 } 674 } 675 676 /* 677 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 678 * interval, computes the 'free' ranges from the same interval. 679 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 680 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 681 */ 682 static void crs_replace_with_free_ranges(GPtrArray *ranges, 683 uint64_t start, uint64_t end) 684 { 685 GPtrArray *free_ranges = g_ptr_array_new(); 686 uint64_t free_base = start; 687 int i; 688 689 g_ptr_array_sort(ranges, crs_range_compare); 690 for (i = 0; i < ranges->len; i++) { 691 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 692 693 if (free_base < used->base) { 694 crs_range_insert(free_ranges, free_base, used->base - 1); 695 } 696 697 free_base = used->limit + 1; 698 } 699 700 if (free_base < end) { 701 crs_range_insert(free_ranges, free_base, end); 702 } 703 704 g_ptr_array_set_size(ranges, 0); 705 for (i = 0; i < free_ranges->len; i++) { 706 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 707 } 708 709 g_ptr_array_free(free_ranges, true); 710 } 711 712 /* 713 * crs_range_merge - merges adjacent ranges in the given array. 714 * Array elements are deleted and replaced with the merged ranges. 715 */ 716 static void crs_range_merge(GPtrArray *range) 717 { 718 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 719 CrsRangeEntry *entry; 720 uint64_t range_base, range_limit; 721 int i; 722 723 if (!range->len) { 724 return; 725 } 726 727 g_ptr_array_sort(range, crs_range_compare); 728 729 entry = g_ptr_array_index(range, 0); 730 range_base = entry->base; 731 range_limit = entry->limit; 732 for (i = 1; i < range->len; i++) { 733 entry = g_ptr_array_index(range, i); 734 if (entry->base - 1 == range_limit) { 735 range_limit = entry->limit; 736 } else { 737 crs_range_insert(tmp, range_base, range_limit); 738 range_base = entry->base; 739 range_limit = entry->limit; 740 } 741 } 742 crs_range_insert(tmp, range_base, range_limit); 743 744 g_ptr_array_set_size(range, 0); 745 for (i = 0; i < tmp->len; i++) { 746 entry = g_ptr_array_index(tmp, i); 747 crs_range_insert(range, entry->base, entry->limit); 748 } 749 g_ptr_array_free(tmp, true); 750 } 751 752 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 753 { 754 Aml *crs = aml_resource_template(); 755 CrsRangeSet temp_range_set; 756 CrsRangeEntry *entry; 757 uint8_t max_bus = pci_bus_num(host->bus); 758 uint8_t type; 759 int devfn; 760 int i; 761 762 crs_range_set_init(&temp_range_set); 763 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 764 uint64_t range_base, range_limit; 765 PCIDevice *dev = host->bus->devices[devfn]; 766 767 if (!dev) { 768 continue; 769 } 770 771 for (i = 0; i < PCI_NUM_REGIONS; i++) { 772 PCIIORegion *r = &dev->io_regions[i]; 773 774 range_base = r->addr; 775 range_limit = r->addr + r->size - 1; 776 777 /* 778 * Work-around for old bioses 779 * that do not support multiple root buses 780 */ 781 if (!range_base || range_base > range_limit) { 782 continue; 783 } 784 785 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 786 crs_range_insert(temp_range_set.io_ranges, 787 range_base, range_limit); 788 } else { /* "memory" */ 789 uint64_t length = range_limit - range_base + 1; 790 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 791 crs_range_insert(temp_range_set.mem_ranges, range_base, 792 range_limit); 793 } else { 794 crs_range_insert(temp_range_set.mem_64bit_ranges, 795 range_base, range_limit); 796 } 797 } 798 } 799 800 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 801 if (type == PCI_HEADER_TYPE_BRIDGE) { 802 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 803 if (subordinate > max_bus) { 804 max_bus = subordinate; 805 } 806 807 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 808 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 809 810 /* 811 * Work-around for old bioses 812 * that do not support multiple root buses 813 */ 814 if (range_base && range_base <= range_limit) { 815 crs_range_insert(temp_range_set.io_ranges, 816 range_base, range_limit); 817 } 818 819 range_base = 820 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 821 range_limit = 822 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 823 824 /* 825 * Work-around for old bioses 826 * that do not support multiple root buses 827 */ 828 if (range_base && range_base <= range_limit) { 829 uint64_t length = range_limit - range_base + 1; 830 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 831 crs_range_insert(temp_range_set.mem_ranges, 832 range_base, range_limit); 833 } else { 834 crs_range_insert(temp_range_set.mem_64bit_ranges, 835 range_base, range_limit); 836 } 837 } 838 839 range_base = 840 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 841 range_limit = 842 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 843 844 /* 845 * Work-around for old bioses 846 * that do not support multiple root buses 847 */ 848 if (range_base && range_base <= range_limit) { 849 uint64_t length = range_limit - range_base + 1; 850 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 851 crs_range_insert(temp_range_set.mem_ranges, 852 range_base, range_limit); 853 } else { 854 crs_range_insert(temp_range_set.mem_64bit_ranges, 855 range_base, range_limit); 856 } 857 } 858 } 859 } 860 861 crs_range_merge(temp_range_set.io_ranges); 862 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 863 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 864 aml_append(crs, 865 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 866 AML_POS_DECODE, AML_ENTIRE_RANGE, 867 0, entry->base, entry->limit, 0, 868 entry->limit - entry->base + 1)); 869 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 870 } 871 872 crs_range_merge(temp_range_set.mem_ranges); 873 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 874 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 875 assert(entry->limit <= UINT32_MAX && 876 (entry->limit - entry->base + 1) <= UINT32_MAX); 877 aml_append(crs, 878 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 879 AML_MAX_FIXED, AML_NON_CACHEABLE, 880 AML_READ_WRITE, 881 0, entry->base, entry->limit, 0, 882 entry->limit - entry->base + 1)); 883 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 884 } 885 886 crs_range_merge(temp_range_set.mem_64bit_ranges); 887 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 888 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 889 aml_append(crs, 890 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 891 AML_MAX_FIXED, AML_NON_CACHEABLE, 892 AML_READ_WRITE, 893 0, entry->base, entry->limit, 0, 894 entry->limit - entry->base + 1)); 895 crs_range_insert(range_set->mem_64bit_ranges, 896 entry->base, entry->limit); 897 } 898 899 crs_range_set_free(&temp_range_set); 900 901 aml_append(crs, 902 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 903 0, 904 pci_bus_num(host->bus), 905 max_bus, 906 0, 907 max_bus - pci_bus_num(host->bus) + 1)); 908 909 return crs; 910 } 911 912 static void build_hpet_aml(Aml *table) 913 { 914 Aml *crs; 915 Aml *field; 916 Aml *method; 917 Aml *if_ctx; 918 Aml *scope = aml_scope("_SB"); 919 Aml *dev = aml_device("HPET"); 920 Aml *zero = aml_int(0); 921 Aml *id = aml_local(0); 922 Aml *period = aml_local(1); 923 924 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 925 aml_append(dev, aml_name_decl("_UID", zero)); 926 927 aml_append(dev, 928 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 929 HPET_LEN)); 930 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 931 aml_append(field, aml_named_field("VEND", 32)); 932 aml_append(field, aml_named_field("PRD", 32)); 933 aml_append(dev, field); 934 935 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 936 aml_append(method, aml_store(aml_name("VEND"), id)); 937 aml_append(method, aml_store(aml_name("PRD"), period)); 938 aml_append(method, aml_shiftright(id, aml_int(16), id)); 939 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 940 aml_equal(id, aml_int(0xffff)))); 941 { 942 aml_append(if_ctx, aml_return(zero)); 943 } 944 aml_append(method, if_ctx); 945 946 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 947 aml_lgreater(period, aml_int(100000000)))); 948 { 949 aml_append(if_ctx, aml_return(zero)); 950 } 951 aml_append(method, if_ctx); 952 953 aml_append(method, aml_return(aml_int(0x0F))); 954 aml_append(dev, method); 955 956 crs = aml_resource_template(); 957 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 958 aml_append(dev, aml_name_decl("_CRS", crs)); 959 960 aml_append(scope, dev); 961 aml_append(table, scope); 962 } 963 964 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 965 { 966 Aml *dev; 967 Aml *method; 968 Aml *crs; 969 970 dev = aml_device("VMBS"); 971 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 972 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 973 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 974 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 975 976 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 977 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 978 aml_name("STA"))); 979 aml_append(dev, method); 980 981 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 982 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 983 aml_name("STA"))); 984 aml_append(dev, method); 985 986 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 987 aml_append(method, aml_return(aml_name("STA"))); 988 aml_append(dev, method); 989 990 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 991 992 crs = aml_resource_template(); 993 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 994 aml_append(dev, aml_name_decl("_CRS", crs)); 995 996 return dev; 997 } 998 999 static void build_isa_devices_aml(Aml *table) 1000 { 1001 bool ambiguous; 1002 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 1003 Aml *scope; 1004 1005 assert(obj && !ambiguous); 1006 1007 scope = aml_scope("_SB.PCI0.ISA"); 1008 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 1009 isa_build_aml(ISA_BUS(obj), scope); 1010 1011 aml_append(table, scope); 1012 } 1013 1014 static void build_dbg_aml(Aml *table) 1015 { 1016 Aml *field; 1017 Aml *method; 1018 Aml *while_ctx; 1019 Aml *scope = aml_scope("\\"); 1020 Aml *buf = aml_local(0); 1021 Aml *len = aml_local(1); 1022 Aml *idx = aml_local(2); 1023 1024 aml_append(scope, 1025 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1026 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1027 aml_append(field, aml_named_field("DBGB", 8)); 1028 aml_append(scope, field); 1029 1030 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1031 1032 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1033 aml_append(method, aml_to_buffer(buf, buf)); 1034 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1035 aml_append(method, aml_store(aml_int(0), idx)); 1036 1037 while_ctx = aml_while(aml_lless(idx, len)); 1038 aml_append(while_ctx, 1039 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1040 aml_append(while_ctx, aml_increment(idx)); 1041 aml_append(method, while_ctx); 1042 1043 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1044 aml_append(scope, method); 1045 1046 aml_append(table, scope); 1047 } 1048 1049 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1050 { 1051 Aml *dev; 1052 Aml *crs; 1053 Aml *method; 1054 uint32_t irqs[] = {5, 10, 11}; 1055 1056 dev = aml_device("%s", name); 1057 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1058 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1059 1060 crs = aml_resource_template(); 1061 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1062 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1063 aml_append(dev, aml_name_decl("_PRS", crs)); 1064 1065 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1066 aml_append(method, aml_return(aml_call1("IQST", reg))); 1067 aml_append(dev, method); 1068 1069 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1070 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1071 aml_append(dev, method); 1072 1073 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1074 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1075 aml_append(dev, method); 1076 1077 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1078 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1079 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1080 aml_append(dev, method); 1081 1082 return dev; 1083 } 1084 1085 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1086 { 1087 Aml *dev; 1088 Aml *crs; 1089 Aml *method; 1090 uint32_t irqs; 1091 1092 dev = aml_device("%s", name); 1093 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1094 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1095 1096 crs = aml_resource_template(); 1097 irqs = gsi; 1098 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1099 AML_SHARED, &irqs, 1)); 1100 aml_append(dev, aml_name_decl("_PRS", crs)); 1101 1102 aml_append(dev, aml_name_decl("_CRS", crs)); 1103 1104 /* 1105 * _DIS can be no-op because the interrupt cannot be disabled. 1106 */ 1107 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1108 aml_append(dev, method); 1109 1110 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1111 aml_append(dev, method); 1112 1113 return dev; 1114 } 1115 1116 /* _CRS method - get current settings */ 1117 static Aml *build_iqcr_method(bool is_piix4) 1118 { 1119 Aml *if_ctx; 1120 uint32_t irqs; 1121 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1122 Aml *crs = aml_resource_template(); 1123 1124 irqs = 0; 1125 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1126 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1127 aml_append(method, aml_name_decl("PRR0", crs)); 1128 1129 aml_append(method, 1130 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1131 1132 if (is_piix4) { 1133 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1134 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1135 aml_append(method, if_ctx); 1136 } else { 1137 aml_append(method, 1138 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1139 aml_name("PRRI"))); 1140 } 1141 1142 aml_append(method, aml_return(aml_name("PRR0"))); 1143 return method; 1144 } 1145 1146 /* _STA method - get status */ 1147 static Aml *build_irq_status_method(void) 1148 { 1149 Aml *if_ctx; 1150 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1151 1152 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1153 aml_append(if_ctx, aml_return(aml_int(0x09))); 1154 aml_append(method, if_ctx); 1155 aml_append(method, aml_return(aml_int(0x0B))); 1156 return method; 1157 } 1158 1159 static void build_piix4_pci0_int(Aml *table) 1160 { 1161 Aml *dev; 1162 Aml *crs; 1163 Aml *field; 1164 Aml *method; 1165 uint32_t irqs; 1166 Aml *sb_scope = aml_scope("_SB"); 1167 Aml *pci0_scope = aml_scope("PCI0"); 1168 1169 aml_append(pci0_scope, build_prt(true)); 1170 aml_append(sb_scope, pci0_scope); 1171 1172 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1173 aml_append(field, aml_named_field("PRQ0", 8)); 1174 aml_append(field, aml_named_field("PRQ1", 8)); 1175 aml_append(field, aml_named_field("PRQ2", 8)); 1176 aml_append(field, aml_named_field("PRQ3", 8)); 1177 aml_append(sb_scope, field); 1178 1179 aml_append(sb_scope, build_irq_status_method()); 1180 aml_append(sb_scope, build_iqcr_method(true)); 1181 1182 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1183 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1184 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1185 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1186 1187 dev = aml_device("LNKS"); 1188 { 1189 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1190 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1191 1192 crs = aml_resource_template(); 1193 irqs = 9; 1194 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1195 AML_ACTIVE_HIGH, AML_SHARED, 1196 &irqs, 1)); 1197 aml_append(dev, aml_name_decl("_PRS", crs)); 1198 1199 /* The SCI cannot be disabled and is always attached to GSI 9, 1200 * so these are no-ops. We only need this link to override the 1201 * polarity to active high and match the content of the MADT. 1202 */ 1203 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1204 aml_append(method, aml_return(aml_int(0x0b))); 1205 aml_append(dev, method); 1206 1207 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1208 aml_append(dev, method); 1209 1210 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1211 aml_append(method, aml_return(aml_name("_PRS"))); 1212 aml_append(dev, method); 1213 1214 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1215 aml_append(dev, method); 1216 } 1217 aml_append(sb_scope, dev); 1218 1219 aml_append(table, sb_scope); 1220 } 1221 1222 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1223 { 1224 int i; 1225 int head; 1226 Aml *pkg; 1227 char base = name[3] < 'E' ? 'A' : 'E'; 1228 char *s = g_strdup(name); 1229 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1230 1231 assert(strlen(s) == 4); 1232 1233 head = name[3] - base; 1234 for (i = 0; i < 4; i++) { 1235 if (head + i > 3) { 1236 head = i * -1; 1237 } 1238 s[3] = base + head + i; 1239 pkg = aml_package(4); 1240 aml_append(pkg, a_nr); 1241 aml_append(pkg, aml_int(i)); 1242 aml_append(pkg, aml_name("%s", s)); 1243 aml_append(pkg, aml_int(0)); 1244 aml_append(ctx, pkg); 1245 } 1246 g_free(s); 1247 } 1248 1249 static Aml *build_q35_routing_table(const char *str) 1250 { 1251 int i; 1252 Aml *pkg; 1253 char *name = g_strdup_printf("%s ", str); 1254 1255 pkg = aml_package(128); 1256 for (i = 0; i < 0x18; i++) { 1257 name[3] = 'E' + (i & 0x3); 1258 append_q35_prt_entry(pkg, i, name); 1259 } 1260 1261 name[3] = 'E'; 1262 append_q35_prt_entry(pkg, 0x18, name); 1263 1264 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1265 for (i = 0x0019; i < 0x1e; i++) { 1266 name[3] = 'A'; 1267 append_q35_prt_entry(pkg, i, name); 1268 } 1269 1270 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1271 name[3] = 'E'; 1272 append_q35_prt_entry(pkg, 0x1e, name); 1273 name[3] = 'A'; 1274 append_q35_prt_entry(pkg, 0x1f, name); 1275 1276 g_free(name); 1277 return pkg; 1278 } 1279 1280 static void build_q35_pci0_int(Aml *table) 1281 { 1282 Aml *field; 1283 Aml *method; 1284 Aml *sb_scope = aml_scope("_SB"); 1285 Aml *pci0_scope = aml_scope("PCI0"); 1286 1287 /* Zero => PIC mode, One => APIC Mode */ 1288 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1289 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1290 { 1291 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1292 } 1293 aml_append(table, method); 1294 1295 aml_append(pci0_scope, 1296 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1297 aml_append(pci0_scope, 1298 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1299 1300 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1301 { 1302 Aml *if_ctx; 1303 Aml *else_ctx; 1304 1305 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1306 section 6.2.8.1 */ 1307 /* Note: we provide the same info as the PCI routing 1308 table of the Bochs BIOS */ 1309 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1310 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1311 aml_append(method, if_ctx); 1312 else_ctx = aml_else(); 1313 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1314 aml_append(method, else_ctx); 1315 } 1316 aml_append(pci0_scope, method); 1317 aml_append(sb_scope, pci0_scope); 1318 1319 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1320 aml_append(field, aml_named_field("PRQA", 8)); 1321 aml_append(field, aml_named_field("PRQB", 8)); 1322 aml_append(field, aml_named_field("PRQC", 8)); 1323 aml_append(field, aml_named_field("PRQD", 8)); 1324 aml_append(field, aml_reserved_field(0x20)); 1325 aml_append(field, aml_named_field("PRQE", 8)); 1326 aml_append(field, aml_named_field("PRQF", 8)); 1327 aml_append(field, aml_named_field("PRQG", 8)); 1328 aml_append(field, aml_named_field("PRQH", 8)); 1329 aml_append(sb_scope, field); 1330 1331 aml_append(sb_scope, build_irq_status_method()); 1332 aml_append(sb_scope, build_iqcr_method(false)); 1333 1334 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1335 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1336 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1337 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1338 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1339 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1340 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1341 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1342 1343 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1344 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1345 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1346 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1347 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1348 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1349 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1350 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1351 1352 aml_append(table, sb_scope); 1353 } 1354 1355 static void build_q35_isa_bridge(Aml *table) 1356 { 1357 Aml *dev; 1358 Aml *scope; 1359 1360 scope = aml_scope("_SB.PCI0"); 1361 dev = aml_device("ISA"); 1362 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1363 1364 /* ICH9 PCI to ISA irq remapping */ 1365 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1366 aml_int(0x60), 0x0C)); 1367 1368 aml_append(scope, dev); 1369 aml_append(table, scope); 1370 } 1371 1372 static void build_piix4_isa_bridge(Aml *table) 1373 { 1374 Aml *dev; 1375 Aml *scope; 1376 1377 scope = aml_scope("_SB.PCI0"); 1378 dev = aml_device("ISA"); 1379 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1380 1381 /* PIIX PCI to ISA irq remapping */ 1382 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1383 aml_int(0x60), 0x04)); 1384 1385 aml_append(scope, dev); 1386 aml_append(table, scope); 1387 } 1388 1389 static void build_piix4_pci_hotplug(Aml *table) 1390 { 1391 Aml *scope; 1392 Aml *field; 1393 Aml *method; 1394 1395 scope = aml_scope("_SB.PCI0"); 1396 1397 aml_append(scope, 1398 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1399 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1400 aml_append(field, aml_named_field("PCIU", 32)); 1401 aml_append(field, aml_named_field("PCID", 32)); 1402 aml_append(scope, field); 1403 1404 aml_append(scope, 1405 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1406 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1407 aml_append(field, aml_named_field("B0EJ", 32)); 1408 aml_append(scope, field); 1409 1410 aml_append(scope, 1411 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1412 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1413 aml_append(field, aml_named_field("BNUM", 32)); 1414 aml_append(scope, field); 1415 1416 aml_append(scope, aml_mutex("BLCK", 0)); 1417 1418 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1419 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1420 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1421 aml_append(method, 1422 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1423 aml_append(method, aml_release(aml_name("BLCK"))); 1424 aml_append(method, aml_return(aml_int(0))); 1425 aml_append(scope, method); 1426 1427 aml_append(table, scope); 1428 } 1429 1430 static Aml *build_q35_osc_method(void) 1431 { 1432 Aml *if_ctx; 1433 Aml *if_ctx2; 1434 Aml *else_ctx; 1435 Aml *method; 1436 Aml *a_cwd1 = aml_name("CDW1"); 1437 Aml *a_ctrl = aml_local(0); 1438 1439 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1440 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1441 1442 if_ctx = aml_if(aml_equal( 1443 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1444 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1445 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1446 1447 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1448 1449 /* 1450 * Always allow native PME, AER (no dependencies) 1451 * Allow SHPC (PCI bridges can have SHPC controller) 1452 */ 1453 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1454 1455 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1456 /* Unknown revision */ 1457 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1458 aml_append(if_ctx, if_ctx2); 1459 1460 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1461 /* Capabilities bits were masked */ 1462 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1463 aml_append(if_ctx, if_ctx2); 1464 1465 /* Update DWORD3 in the buffer */ 1466 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1467 aml_append(method, if_ctx); 1468 1469 else_ctx = aml_else(); 1470 /* Unrecognized UUID */ 1471 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1472 aml_append(method, else_ctx); 1473 1474 aml_append(method, aml_return(aml_arg(3))); 1475 return method; 1476 } 1477 1478 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1479 { 1480 Aml *scope = aml_scope("_SB.PCI0"); 1481 Aml *dev = aml_device("SMB0"); 1482 1483 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1484 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1485 aml_append(scope, dev); 1486 aml_append(table, scope); 1487 } 1488 1489 static void 1490 build_dsdt(GArray *table_data, BIOSLinker *linker, 1491 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1492 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1493 { 1494 CrsRangeEntry *entry; 1495 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1496 CrsRangeSet crs_range_set; 1497 PCMachineState *pcms = PC_MACHINE(machine); 1498 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1499 X86MachineState *x86ms = X86_MACHINE(machine); 1500 AcpiMcfgInfo mcfg; 1501 uint32_t nr_mem = machine->ram_slots; 1502 int root_bus_limit = 0xFF; 1503 PCIBus *bus = NULL; 1504 TPMIf *tpm = tpm_find(); 1505 int i; 1506 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1507 1508 dsdt = init_aml_allocator(); 1509 1510 /* Reserve space for header */ 1511 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1512 1513 build_dbg_aml(dsdt); 1514 if (misc->is_piix4) { 1515 sb_scope = aml_scope("_SB"); 1516 dev = aml_device("PCI0"); 1517 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1518 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1519 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1520 aml_append(sb_scope, dev); 1521 aml_append(dsdt, sb_scope); 1522 1523 build_hpet_aml(dsdt); 1524 build_piix4_isa_bridge(dsdt); 1525 build_isa_devices_aml(dsdt); 1526 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1527 build_piix4_pci_hotplug(dsdt); 1528 } 1529 build_piix4_pci0_int(dsdt); 1530 } else { 1531 sb_scope = aml_scope("_SB"); 1532 dev = aml_device("PCI0"); 1533 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1534 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1535 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1536 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 1537 aml_append(dev, build_q35_osc_method()); 1538 aml_append(sb_scope, dev); 1539 1540 if (pm->smi_on_cpuhp) { 1541 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1542 dev = aml_device("PCI0.SMI0"); 1543 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1544 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1545 crs = aml_resource_template(); 1546 aml_append(crs, 1547 aml_io( 1548 AML_DECODE16, 1549 ACPI_PORT_SMI_CMD, 1550 ACPI_PORT_SMI_CMD, 1551 1, 1552 2) 1553 ); 1554 aml_append(dev, aml_name_decl("_CRS", crs)); 1555 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1556 aml_int(ACPI_PORT_SMI_CMD), 2)); 1557 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1558 AML_WRITE_AS_ZEROS); 1559 aml_append(field, aml_named_field("SMIC", 8)); 1560 aml_append(field, aml_reserved_field(8)); 1561 aml_append(dev, field); 1562 aml_append(sb_scope, dev); 1563 } 1564 1565 aml_append(dsdt, sb_scope); 1566 1567 build_hpet_aml(dsdt); 1568 build_q35_isa_bridge(dsdt); 1569 build_isa_devices_aml(dsdt); 1570 build_q35_pci0_int(dsdt); 1571 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1572 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1573 } 1574 } 1575 1576 if (vmbus_bridge) { 1577 sb_scope = aml_scope("_SB"); 1578 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1579 aml_append(dsdt, sb_scope); 1580 } 1581 1582 if (pcmc->legacy_cpu_hotplug) { 1583 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1584 } else { 1585 CPUHotplugFeatures opts = { 1586 .acpi_1_compatible = true, .has_legacy_cphp = true, 1587 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1588 }; 1589 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1590 "\\_SB.PCI0", "\\_GPE._E02"); 1591 } 1592 1593 if (pcms->memhp_io_base && nr_mem) { 1594 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1595 "\\_GPE._E03", AML_SYSTEM_IO, 1596 pcms->memhp_io_base); 1597 } 1598 1599 scope = aml_scope("_GPE"); 1600 { 1601 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1602 1603 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1604 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1605 aml_append(method, 1606 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1607 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1608 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1609 aml_append(scope, method); 1610 } 1611 1612 if (machine->nvdimms_state->is_enabled) { 1613 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1614 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1615 aml_int(0x80))); 1616 aml_append(scope, method); 1617 } 1618 } 1619 aml_append(dsdt, scope); 1620 1621 crs_range_set_init(&crs_range_set); 1622 bus = PC_MACHINE(machine)->bus; 1623 if (bus) { 1624 QLIST_FOREACH(bus, &bus->child, sibling) { 1625 uint8_t bus_num = pci_bus_num(bus); 1626 uint8_t numa_node = pci_bus_numa_node(bus); 1627 1628 /* look only for expander root buses */ 1629 if (!pci_bus_is_root(bus)) { 1630 continue; 1631 } 1632 1633 if (bus_num < root_bus_limit) { 1634 root_bus_limit = bus_num - 1; 1635 } 1636 1637 scope = aml_scope("\\_SB"); 1638 dev = aml_device("PC%.02X", bus_num); 1639 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1640 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1641 if (pci_bus_is_express(bus)) { 1642 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1643 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1644 aml_append(dev, build_q35_osc_method()); 1645 } else { 1646 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1647 } 1648 1649 if (numa_node != NUMA_NODE_UNASSIGNED) { 1650 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1651 } 1652 1653 aml_append(dev, build_prt(false)); 1654 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1655 aml_append(dev, aml_name_decl("_CRS", crs)); 1656 aml_append(scope, dev); 1657 aml_append(dsdt, scope); 1658 } 1659 } 1660 1661 /* 1662 * At this point crs_range_set has all the ranges used by pci 1663 * busses *other* than PCI0. These ranges will be excluded from 1664 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1665 * too. 1666 */ 1667 if (acpi_get_mcfg(&mcfg)) { 1668 crs_range_insert(crs_range_set.mem_ranges, 1669 mcfg.base, mcfg.base + mcfg.size - 1); 1670 } 1671 1672 scope = aml_scope("\\_SB.PCI0"); 1673 /* build PCI0._CRS */ 1674 crs = aml_resource_template(); 1675 aml_append(crs, 1676 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1677 0x0000, 0x0, root_bus_limit, 1678 0x0000, root_bus_limit + 1)); 1679 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1680 1681 aml_append(crs, 1682 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1683 AML_POS_DECODE, AML_ENTIRE_RANGE, 1684 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1685 1686 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1687 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1688 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1689 aml_append(crs, 1690 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1691 AML_POS_DECODE, AML_ENTIRE_RANGE, 1692 0x0000, entry->base, entry->limit, 1693 0x0000, entry->limit - entry->base + 1)); 1694 } 1695 1696 aml_append(crs, 1697 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1698 AML_CACHEABLE, AML_READ_WRITE, 1699 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1700 1701 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1702 range_lob(pci_hole), 1703 range_upb(pci_hole)); 1704 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1705 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1706 aml_append(crs, 1707 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1708 AML_NON_CACHEABLE, AML_READ_WRITE, 1709 0, entry->base, entry->limit, 1710 0, entry->limit - entry->base + 1)); 1711 } 1712 1713 if (!range_is_empty(pci_hole64)) { 1714 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1715 range_lob(pci_hole64), 1716 range_upb(pci_hole64)); 1717 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1718 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1719 aml_append(crs, 1720 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1721 AML_MAX_FIXED, 1722 AML_CACHEABLE, AML_READ_WRITE, 1723 0, entry->base, entry->limit, 1724 0, entry->limit - entry->base + 1)); 1725 } 1726 } 1727 1728 if (TPM_IS_TIS_ISA(tpm_find())) { 1729 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1730 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1731 } 1732 aml_append(scope, aml_name_decl("_CRS", crs)); 1733 1734 /* reserve GPE0 block resources */ 1735 dev = aml_device("GPE0"); 1736 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1737 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1738 /* device present, functioning, decoding, not shown in UI */ 1739 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1740 crs = aml_resource_template(); 1741 aml_append(crs, 1742 aml_io( 1743 AML_DECODE16, 1744 pm->fadt.gpe0_blk.address, 1745 pm->fadt.gpe0_blk.address, 1746 1, 1747 pm->fadt.gpe0_blk.bit_width / 8) 1748 ); 1749 aml_append(dev, aml_name_decl("_CRS", crs)); 1750 aml_append(scope, dev); 1751 1752 crs_range_set_free(&crs_range_set); 1753 1754 /* reserve PCIHP resources */ 1755 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1756 dev = aml_device("PHPR"); 1757 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1758 aml_append(dev, 1759 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1760 /* device present, functioning, decoding, not shown in UI */ 1761 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1762 crs = aml_resource_template(); 1763 aml_append(crs, 1764 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1765 pm->pcihp_io_len) 1766 ); 1767 aml_append(dev, aml_name_decl("_CRS", crs)); 1768 aml_append(scope, dev); 1769 } 1770 aml_append(dsdt, scope); 1771 1772 /* create S3_ / S4_ / S5_ packages if necessary */ 1773 scope = aml_scope("\\"); 1774 if (!pm->s3_disabled) { 1775 pkg = aml_package(4); 1776 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1777 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1778 aml_append(pkg, aml_int(0)); /* reserved */ 1779 aml_append(pkg, aml_int(0)); /* reserved */ 1780 aml_append(scope, aml_name_decl("_S3", pkg)); 1781 } 1782 1783 if (!pm->s4_disabled) { 1784 pkg = aml_package(4); 1785 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1786 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1787 aml_append(pkg, aml_int(pm->s4_val)); 1788 aml_append(pkg, aml_int(0)); /* reserved */ 1789 aml_append(pkg, aml_int(0)); /* reserved */ 1790 aml_append(scope, aml_name_decl("_S4", pkg)); 1791 } 1792 1793 pkg = aml_package(4); 1794 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1795 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1796 aml_append(pkg, aml_int(0)); /* reserved */ 1797 aml_append(pkg, aml_int(0)); /* reserved */ 1798 aml_append(scope, aml_name_decl("_S5", pkg)); 1799 aml_append(dsdt, scope); 1800 1801 /* create fw_cfg node, unconditionally */ 1802 { 1803 scope = aml_scope("\\_SB.PCI0"); 1804 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1805 aml_append(dsdt, scope); 1806 } 1807 1808 if (misc->applesmc_io_base) { 1809 scope = aml_scope("\\_SB.PCI0.ISA"); 1810 dev = aml_device("SMC"); 1811 1812 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1813 /* device present, functioning, decoding, not shown in UI */ 1814 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1815 1816 crs = aml_resource_template(); 1817 aml_append(crs, 1818 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1819 0x01, APPLESMC_MAX_DATA_LENGTH) 1820 ); 1821 aml_append(crs, aml_irq_no_flags(6)); 1822 aml_append(dev, aml_name_decl("_CRS", crs)); 1823 1824 aml_append(scope, dev); 1825 aml_append(dsdt, scope); 1826 } 1827 1828 if (misc->pvpanic_port) { 1829 scope = aml_scope("\\_SB.PCI0.ISA"); 1830 1831 dev = aml_device("PEVT"); 1832 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1833 1834 crs = aml_resource_template(); 1835 aml_append(crs, 1836 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1837 ); 1838 aml_append(dev, aml_name_decl("_CRS", crs)); 1839 1840 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1841 aml_int(misc->pvpanic_port), 1)); 1842 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1843 aml_append(field, aml_named_field("PEPT", 8)); 1844 aml_append(dev, field); 1845 1846 /* device present, functioning, decoding, shown in UI */ 1847 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1848 1849 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1850 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1851 aml_append(method, aml_return(aml_local(0))); 1852 aml_append(dev, method); 1853 1854 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1855 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1856 aml_append(dev, method); 1857 1858 aml_append(scope, dev); 1859 aml_append(dsdt, scope); 1860 } 1861 1862 sb_scope = aml_scope("\\_SB"); 1863 { 1864 Object *pci_host; 1865 PCIBus *bus = NULL; 1866 1867 pci_host = acpi_get_i386_pci_host(); 1868 if (pci_host) { 1869 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1870 } 1871 1872 if (bus) { 1873 Aml *scope = aml_scope("PCI0"); 1874 /* Scan all PCI buses. Generate tables to support hotplug. */ 1875 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1876 1877 if (TPM_IS_TIS_ISA(tpm)) { 1878 if (misc->tpm_version == TPM_VERSION_2_0) { 1879 dev = aml_device("TPM"); 1880 aml_append(dev, aml_name_decl("_HID", 1881 aml_string("MSFT0101"))); 1882 } else { 1883 dev = aml_device("ISA.TPM"); 1884 aml_append(dev, aml_name_decl("_HID", 1885 aml_eisaid("PNP0C31"))); 1886 } 1887 1888 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1889 crs = aml_resource_template(); 1890 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1891 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1892 /* 1893 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1894 Rewrite to take IRQ from TPM device model and 1895 fix default IRQ value there to use some unused IRQ 1896 */ 1897 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1898 aml_append(dev, aml_name_decl("_CRS", crs)); 1899 1900 tpm_build_ppi_acpi(tpm, dev); 1901 1902 aml_append(scope, dev); 1903 } 1904 1905 aml_append(sb_scope, scope); 1906 } 1907 } 1908 1909 if (TPM_IS_CRB(tpm)) { 1910 dev = aml_device("TPM"); 1911 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1912 crs = aml_resource_template(); 1913 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1914 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1915 aml_append(dev, aml_name_decl("_CRS", crs)); 1916 1917 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1918 1919 tpm_build_ppi_acpi(tpm, dev); 1920 1921 aml_append(sb_scope, dev); 1922 } 1923 1924 aml_append(dsdt, sb_scope); 1925 1926 /* copy AML table into ACPI tables blob and patch header there */ 1927 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1928 build_header(linker, table_data, 1929 (void *)(table_data->data + table_data->len - dsdt->buf->len), 1930 "DSDT", dsdt->buf->len, 1, NULL, NULL); 1931 free_aml_allocator(); 1932 } 1933 1934 static void 1935 build_hpet(GArray *table_data, BIOSLinker *linker) 1936 { 1937 Acpi20Hpet *hpet; 1938 1939 hpet = acpi_data_push(table_data, sizeof(*hpet)); 1940 /* Note timer_block_id value must be kept in sync with value advertised by 1941 * emulated hpet 1942 */ 1943 hpet->timer_block_id = cpu_to_le32(0x8086a201); 1944 hpet->addr.address = cpu_to_le64(HPET_BASE); 1945 build_header(linker, table_data, 1946 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 1947 } 1948 1949 static void 1950 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 1951 { 1952 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 1953 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 1954 unsigned log_addr_offset = 1955 (char *)&tcpa->log_area_start_address - table_data->data; 1956 1957 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 1958 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 1959 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 1960 1961 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1962 false /* high memory */); 1963 1964 /* log area start address to be filled by Guest linker */ 1965 bios_linker_loader_add_pointer(linker, 1966 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 1967 ACPI_BUILD_TPMLOG_FILE, 0); 1968 1969 build_header(linker, table_data, 1970 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 1971 } 1972 1973 #define HOLE_640K_START (640 * KiB) 1974 #define HOLE_640K_END (1 * MiB) 1975 1976 static void 1977 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1978 { 1979 AcpiSystemResourceAffinityTable *srat; 1980 AcpiSratMemoryAffinity *numamem; 1981 1982 int i; 1983 int srat_start, numa_start, slots; 1984 uint64_t mem_len, mem_base, next_base; 1985 MachineClass *mc = MACHINE_GET_CLASS(machine); 1986 X86MachineState *x86ms = X86_MACHINE(machine); 1987 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1988 PCMachineState *pcms = PC_MACHINE(machine); 1989 ram_addr_t hotplugabble_address_space_size = 1990 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1991 NULL); 1992 1993 srat_start = table_data->len; 1994 1995 srat = acpi_data_push(table_data, sizeof *srat); 1996 srat->reserved1 = cpu_to_le32(1); 1997 1998 for (i = 0; i < apic_ids->len; i++) { 1999 int node_id = apic_ids->cpus[i].props.node_id; 2000 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2001 2002 if (apic_id < 255) { 2003 AcpiSratProcessorAffinity *core; 2004 2005 core = acpi_data_push(table_data, sizeof *core); 2006 core->type = ACPI_SRAT_PROCESSOR_APIC; 2007 core->length = sizeof(*core); 2008 core->local_apic_id = apic_id; 2009 core->proximity_lo = node_id; 2010 memset(core->proximity_hi, 0, 3); 2011 core->local_sapic_eid = 0; 2012 core->flags = cpu_to_le32(1); 2013 } else { 2014 AcpiSratProcessorX2ApicAffinity *core; 2015 2016 core = acpi_data_push(table_data, sizeof *core); 2017 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2018 core->length = sizeof(*core); 2019 core->x2apic_id = cpu_to_le32(apic_id); 2020 core->proximity_domain = cpu_to_le32(node_id); 2021 core->flags = cpu_to_le32(1); 2022 } 2023 } 2024 2025 2026 /* the memory map is a bit tricky, it contains at least one hole 2027 * from 640k-1M and possibly another one from 3.5G-4G. 2028 */ 2029 next_base = 0; 2030 numa_start = table_data->len; 2031 2032 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2033 mem_base = next_base; 2034 mem_len = pcms->node_mem[i - 1]; 2035 next_base = mem_base + mem_len; 2036 2037 /* Cut out the 640K hole */ 2038 if (mem_base <= HOLE_640K_START && 2039 next_base > HOLE_640K_START) { 2040 mem_len -= next_base - HOLE_640K_START; 2041 if (mem_len > 0) { 2042 numamem = acpi_data_push(table_data, sizeof *numamem); 2043 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2044 MEM_AFFINITY_ENABLED); 2045 } 2046 2047 /* Check for the rare case: 640K < RAM < 1M */ 2048 if (next_base <= HOLE_640K_END) { 2049 next_base = HOLE_640K_END; 2050 continue; 2051 } 2052 mem_base = HOLE_640K_END; 2053 mem_len = next_base - HOLE_640K_END; 2054 } 2055 2056 /* Cut out the ACPI_PCI hole */ 2057 if (mem_base <= x86ms->below_4g_mem_size && 2058 next_base > x86ms->below_4g_mem_size) { 2059 mem_len -= next_base - x86ms->below_4g_mem_size; 2060 if (mem_len > 0) { 2061 numamem = acpi_data_push(table_data, sizeof *numamem); 2062 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2063 MEM_AFFINITY_ENABLED); 2064 } 2065 mem_base = 1ULL << 32; 2066 mem_len = next_base - x86ms->below_4g_mem_size; 2067 next_base = mem_base + mem_len; 2068 } 2069 2070 if (mem_len > 0) { 2071 numamem = acpi_data_push(table_data, sizeof *numamem); 2072 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2073 MEM_AFFINITY_ENABLED); 2074 } 2075 } 2076 2077 if (machine->nvdimms_state->is_enabled) { 2078 nvdimm_build_srat(table_data); 2079 } 2080 2081 slots = (table_data->len - numa_start) / sizeof *numamem; 2082 for (; slots < pcms->numa_nodes + 2; slots++) { 2083 numamem = acpi_data_push(table_data, sizeof *numamem); 2084 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2085 } 2086 2087 /* 2088 * Entry is required for Windows to enable memory hotplug in OS 2089 * and for Linux to enable SWIOTLB when booted with less than 2090 * 4G of RAM. Windows works better if the entry sets proximity 2091 * to the highest NUMA node in the machine. 2092 * Memory devices may override proximity set by this entry, 2093 * providing _PXM method if necessary. 2094 */ 2095 if (hotplugabble_address_space_size) { 2096 numamem = acpi_data_push(table_data, sizeof *numamem); 2097 build_srat_memory(numamem, machine->device_memory->base, 2098 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2099 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2100 } 2101 2102 build_header(linker, table_data, 2103 (void *)(table_data->data + srat_start), 2104 "SRAT", 2105 table_data->len - srat_start, 1, NULL, NULL); 2106 } 2107 2108 /* 2109 * VT-d spec 8.1 DMA Remapping Reporting Structure 2110 * (version Oct. 2014 or later) 2111 */ 2112 static void 2113 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2114 { 2115 int dmar_start = table_data->len; 2116 2117 AcpiTableDmar *dmar; 2118 AcpiDmarHardwareUnit *drhd; 2119 AcpiDmarRootPortATS *atsr; 2120 uint8_t dmar_flags = 0; 2121 X86IOMMUState *iommu = x86_iommu_get_default(); 2122 AcpiDmarDeviceScope *scope = NULL; 2123 /* Root complex IOAPIC use one path[0] only */ 2124 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2125 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2126 2127 assert(iommu); 2128 if (x86_iommu_ir_supported(iommu)) { 2129 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2130 } 2131 2132 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2133 dmar->host_address_width = intel_iommu->aw_bits - 1; 2134 dmar->flags = dmar_flags; 2135 2136 /* DMAR Remapping Hardware Unit Definition structure */ 2137 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2138 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2139 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2140 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2141 drhd->pci_segment = cpu_to_le16(0); 2142 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2143 2144 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2145 * 8.3.1 (version Oct. 2014 or later). */ 2146 scope = &drhd->scope[0]; 2147 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2148 scope->length = ioapic_scope_size; 2149 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2150 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2151 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2152 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2153 2154 if (iommu->dt_supported) { 2155 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2156 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2157 atsr->length = cpu_to_le16(sizeof(*atsr)); 2158 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2159 atsr->pci_segment = cpu_to_le16(0); 2160 } 2161 2162 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2163 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2164 } 2165 2166 /* 2167 * Windows ACPI Emulated Devices Table 2168 * (Version 1.0 - April 6, 2009) 2169 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2170 * 2171 * Helpful to speedup Windows guests and ignored by others. 2172 */ 2173 static void 2174 build_waet(GArray *table_data, BIOSLinker *linker) 2175 { 2176 int waet_start = table_data->len; 2177 2178 /* WAET header */ 2179 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2180 /* 2181 * Set "ACPI PM timer good" flag. 2182 * 2183 * Tells Windows guests that our ACPI PM timer is reliable in the 2184 * sense that guest can read it only once to obtain a reliable value. 2185 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2186 */ 2187 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2188 2189 build_header(linker, table_data, (void *)(table_data->data + waet_start), 2190 "WAET", table_data->len - waet_start, 1, NULL, NULL); 2191 } 2192 2193 /* 2194 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2195 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2196 */ 2197 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2198 2199 /* 2200 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2201 * necessary for the PCI topology. 2202 */ 2203 static void 2204 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2205 { 2206 GArray *table_data = opaque; 2207 uint32_t entry; 2208 2209 /* "Select" IVHD entry, type 0x2 */ 2210 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2211 build_append_int_noprefix(table_data, entry, 4); 2212 2213 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2214 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2215 uint8_t sec = pci_bus_num(sec_bus); 2216 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2217 2218 if (pci_bus_is_express(sec_bus)) { 2219 /* 2220 * Walk the bus if there are subordinates, otherwise use a range 2221 * to cover an entire leaf bus. We could potentially also use a 2222 * range for traversed buses, but we'd need to take care not to 2223 * create both Select and Range entries covering the same device. 2224 * This is easier and potentially more compact. 2225 * 2226 * An example bare metal system seems to use Select entries for 2227 * root ports without a slot (ie. built-ins) and Range entries 2228 * when there is a slot. The same system also only hard-codes 2229 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2230 * making no effort to support nested bridges. We attempt to 2231 * be more thorough here. 2232 */ 2233 if (sec == sub) { /* leaf bus */ 2234 /* "Start of Range" IVHD entry, type 0x3 */ 2235 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2236 build_append_int_noprefix(table_data, entry, 4); 2237 /* "End of Range" IVHD entry, type 0x4 */ 2238 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2239 build_append_int_noprefix(table_data, entry, 4); 2240 } else { 2241 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2242 } 2243 } else { 2244 /* 2245 * If the secondary bus is conventional, then we need to create an 2246 * Alias range for everything downstream. The range covers the 2247 * first devfn on the secondary bus to the last devfn on the 2248 * subordinate bus. The alias target depends on legacy versus 2249 * express bridges, just as in pci_device_iommu_address_space(). 2250 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2251 */ 2252 uint16_t dev_id_a, dev_id_b; 2253 2254 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2255 2256 if (pci_is_express(dev) && 2257 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2258 dev_id_b = dev_id_a; 2259 } else { 2260 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2261 } 2262 2263 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2264 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2265 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2266 2267 /* "End of Range" IVHD entry, type 0x4 */ 2268 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2269 build_append_int_noprefix(table_data, entry, 4); 2270 } 2271 } 2272 } 2273 2274 /* For all PCI host bridges, walk and insert IVHD entries */ 2275 static int 2276 ivrs_host_bridges(Object *obj, void *opaque) 2277 { 2278 GArray *ivhd_blob = opaque; 2279 2280 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2281 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2282 2283 if (bus) { 2284 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob); 2285 } 2286 } 2287 2288 return 0; 2289 } 2290 2291 static void 2292 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2293 { 2294 int ivhd_table_len = 24; 2295 int iommu_start = table_data->len; 2296 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2297 GArray *ivhd_blob = g_array_new(false, true, 1); 2298 2299 /* IVRS header */ 2300 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2301 /* IVinfo - IO virtualization information common to all 2302 * IOMMU units in a system 2303 */ 2304 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2305 /* reserved */ 2306 build_append_int_noprefix(table_data, 0, 8); 2307 2308 /* IVHD definition - type 10h */ 2309 build_append_int_noprefix(table_data, 0x10, 1); 2310 /* virtualization flags */ 2311 build_append_int_noprefix(table_data, 2312 (1UL << 0) | /* HtTunEn */ 2313 (1UL << 4) | /* iotblSup */ 2314 (1UL << 6) | /* PrefSup */ 2315 (1UL << 7), /* PPRSup */ 2316 1); 2317 2318 /* 2319 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2320 * complete set of IVHD entries. Do this into a separate blob so that we 2321 * can calculate the total IVRS table length here and then append the new 2322 * blob further below. Fall back to an entry covering all devices, which 2323 * is sufficient when no aliases are present. 2324 */ 2325 object_child_foreach_recursive(object_get_root(), 2326 ivrs_host_bridges, ivhd_blob); 2327 2328 if (!ivhd_blob->len) { 2329 /* 2330 * Type 1 device entry reporting all devices 2331 * These are 4-byte device entries currently reporting the range of 2332 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2333 */ 2334 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2335 } 2336 2337 ivhd_table_len += ivhd_blob->len; 2338 2339 /* 2340 * When interrupt remapping is supported, we add a special IVHD device 2341 * for type IO-APIC. 2342 */ 2343 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2344 ivhd_table_len += 8; 2345 } 2346 2347 /* IVHD length */ 2348 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2349 /* DeviceID */ 2350 build_append_int_noprefix(table_data, s->devid, 2); 2351 /* Capability offset */ 2352 build_append_int_noprefix(table_data, s->capab_offset, 2); 2353 /* IOMMU base address */ 2354 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2355 /* PCI Segment Group */ 2356 build_append_int_noprefix(table_data, 0, 2); 2357 /* IOMMU info */ 2358 build_append_int_noprefix(table_data, 0, 2); 2359 /* IOMMU Feature Reporting */ 2360 build_append_int_noprefix(table_data, 2361 (48UL << 30) | /* HATS */ 2362 (48UL << 28) | /* GATS */ 2363 (1UL << 2) | /* GTSup */ 2364 (1UL << 6), /* GASup */ 2365 4); 2366 2367 /* IVHD entries as found above */ 2368 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2369 g_array_free(ivhd_blob, TRUE); 2370 2371 /* 2372 * Add a special IVHD device type. 2373 * Refer to spec - Table 95: IVHD device entry type codes 2374 * 2375 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2376 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2377 */ 2378 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2379 build_append_int_noprefix(table_data, 2380 (0x1ull << 56) | /* type IOAPIC */ 2381 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2382 0x48, /* special device */ 2383 8); 2384 } 2385 2386 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2387 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2388 } 2389 2390 typedef 2391 struct AcpiBuildState { 2392 /* Copy of table in RAM (for patching). */ 2393 MemoryRegion *table_mr; 2394 /* Is table patched? */ 2395 uint8_t patched; 2396 void *rsdp; 2397 MemoryRegion *rsdp_mr; 2398 MemoryRegion *linker_mr; 2399 } AcpiBuildState; 2400 2401 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2402 { 2403 Object *pci_host; 2404 QObject *o; 2405 2406 pci_host = acpi_get_i386_pci_host(); 2407 g_assert(pci_host); 2408 2409 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2410 if (!o) { 2411 return false; 2412 } 2413 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2414 qobject_unref(o); 2415 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2416 return false; 2417 } 2418 2419 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2420 assert(o); 2421 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2422 qobject_unref(o); 2423 return true; 2424 } 2425 2426 static 2427 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2428 { 2429 PCMachineState *pcms = PC_MACHINE(machine); 2430 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2431 X86MachineState *x86ms = X86_MACHINE(machine); 2432 GArray *table_offsets; 2433 unsigned facs, dsdt, rsdt, fadt; 2434 AcpiPmInfo pm; 2435 AcpiMiscInfo misc; 2436 AcpiMcfgInfo mcfg; 2437 Range pci_hole, pci_hole64; 2438 uint8_t *u; 2439 size_t aml_len = 0; 2440 GArray *tables_blob = tables->table_data; 2441 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2442 Object *vmgenid_dev; 2443 2444 acpi_get_pm_info(machine, &pm); 2445 acpi_get_misc_info(&misc); 2446 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2447 acpi_get_slic_oem(&slic_oem); 2448 2449 table_offsets = g_array_new(false, true /* clear */, 2450 sizeof(uint32_t)); 2451 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2452 2453 bios_linker_loader_alloc(tables->linker, 2454 ACPI_BUILD_TABLE_FILE, tables_blob, 2455 64 /* Ensure FACS is aligned */, 2456 false /* high memory */); 2457 2458 /* 2459 * FACS is pointed to by FADT. 2460 * We place it first since it's the only table that has alignment 2461 * requirements. 2462 */ 2463 facs = tables_blob->len; 2464 build_facs(tables_blob); 2465 2466 /* DSDT is pointed to by FADT */ 2467 dsdt = tables_blob->len; 2468 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2469 &pci_hole, &pci_hole64, machine); 2470 2471 /* Count the size of the DSDT and SSDT, we will need it for legacy 2472 * sizing of ACPI tables. 2473 */ 2474 aml_len += tables_blob->len - dsdt; 2475 2476 /* ACPI tables pointed to by RSDT */ 2477 fadt = tables_blob->len; 2478 acpi_add_table(table_offsets, tables_blob); 2479 pm.fadt.facs_tbl_offset = &facs; 2480 pm.fadt.dsdt_tbl_offset = &dsdt; 2481 pm.fadt.xdsdt_tbl_offset = &dsdt; 2482 build_fadt(tables_blob, tables->linker, &pm.fadt, 2483 slic_oem.id, slic_oem.table_id); 2484 aml_len += tables_blob->len - fadt; 2485 2486 acpi_add_table(table_offsets, tables_blob); 2487 acpi_build_madt(tables_blob, tables->linker, x86ms, 2488 ACPI_DEVICE_IF(x86ms->acpi_dev)); 2489 2490 vmgenid_dev = find_vmgenid_dev(); 2491 if (vmgenid_dev) { 2492 acpi_add_table(table_offsets, tables_blob); 2493 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2494 tables->vmgenid, tables->linker); 2495 } 2496 2497 if (misc.has_hpet) { 2498 acpi_add_table(table_offsets, tables_blob); 2499 build_hpet(tables_blob, tables->linker); 2500 } 2501 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2502 if (misc.tpm_version == TPM_VERSION_1_2) { 2503 acpi_add_table(table_offsets, tables_blob); 2504 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2505 } else { /* TPM_VERSION_2_0 */ 2506 acpi_add_table(table_offsets, tables_blob); 2507 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2508 } 2509 } 2510 if (pcms->numa_nodes) { 2511 acpi_add_table(table_offsets, tables_blob); 2512 build_srat(tables_blob, tables->linker, machine); 2513 if (machine->numa_state->have_numa_distance) { 2514 acpi_add_table(table_offsets, tables_blob); 2515 build_slit(tables_blob, tables->linker, machine); 2516 } 2517 if (machine->numa_state->hmat_enabled) { 2518 acpi_add_table(table_offsets, tables_blob); 2519 build_hmat(tables_blob, tables->linker, machine->numa_state); 2520 } 2521 } 2522 if (acpi_get_mcfg(&mcfg)) { 2523 acpi_add_table(table_offsets, tables_blob); 2524 build_mcfg(tables_blob, tables->linker, &mcfg); 2525 } 2526 if (x86_iommu_get_default()) { 2527 IommuType IOMMUType = x86_iommu_get_type(); 2528 if (IOMMUType == TYPE_AMD) { 2529 acpi_add_table(table_offsets, tables_blob); 2530 build_amd_iommu(tables_blob, tables->linker); 2531 } else if (IOMMUType == TYPE_INTEL) { 2532 acpi_add_table(table_offsets, tables_blob); 2533 build_dmar_q35(tables_blob, tables->linker); 2534 } 2535 } 2536 if (machine->nvdimms_state->is_enabled) { 2537 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2538 machine->nvdimms_state, machine->ram_slots); 2539 } 2540 2541 acpi_add_table(table_offsets, tables_blob); 2542 build_waet(tables_blob, tables->linker); 2543 2544 /* Add tables supplied by user (if any) */ 2545 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2546 unsigned len = acpi_table_len(u); 2547 2548 acpi_add_table(table_offsets, tables_blob); 2549 g_array_append_vals(tables_blob, u, len); 2550 } 2551 2552 /* RSDT is pointed to by RSDP */ 2553 rsdt = tables_blob->len; 2554 build_rsdt(tables_blob, tables->linker, table_offsets, 2555 slic_oem.id, slic_oem.table_id); 2556 2557 /* RSDP is in FSEG memory, so allocate it separately */ 2558 { 2559 AcpiRsdpData rsdp_data = { 2560 .revision = 0, 2561 .oem_id = ACPI_BUILD_APPNAME6, 2562 .xsdt_tbl_offset = NULL, 2563 .rsdt_tbl_offset = &rsdt, 2564 }; 2565 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2566 if (!pcmc->rsdp_in_ram) { 2567 /* We used to allocate some extra space for RSDP revision 2 but 2568 * only used the RSDP revision 0 space. The extra bytes were 2569 * zeroed out and not used. 2570 * Here we continue wasting those extra 16 bytes to make sure we 2571 * don't break migration for machine types 2.2 and older due to 2572 * RSDP blob size mismatch. 2573 */ 2574 build_append_int_noprefix(tables->rsdp, 0, 16); 2575 } 2576 } 2577 2578 /* We'll expose it all to Guest so we want to reduce 2579 * chance of size changes. 2580 * 2581 * We used to align the tables to 4k, but of course this would 2582 * too simple to be enough. 4k turned out to be too small an 2583 * alignment very soon, and in fact it is almost impossible to 2584 * keep the table size stable for all (max_cpus, max_memory_slots) 2585 * combinations. So the table size is always 64k for pc-i440fx-2.1 2586 * and we give an error if the table grows beyond that limit. 2587 * 2588 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2589 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2590 * than 2.0 and we can always pad the smaller tables with zeros. We can 2591 * then use the exact size of the 2.0 tables. 2592 * 2593 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2594 */ 2595 if (pcmc->legacy_acpi_table_size) { 2596 /* Subtracting aml_len gives the size of fixed tables. Then add the 2597 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2598 */ 2599 int legacy_aml_len = 2600 pcmc->legacy_acpi_table_size + 2601 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2602 int legacy_table_size = 2603 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2604 ACPI_BUILD_ALIGN_SIZE); 2605 if (tables_blob->len > legacy_table_size) { 2606 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2607 warn_report("ACPI table size %u exceeds %d bytes," 2608 " migration may not work", 2609 tables_blob->len, legacy_table_size); 2610 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2611 " or PCI bridges."); 2612 } 2613 g_array_set_size(tables_blob, legacy_table_size); 2614 } else { 2615 /* Make sure we have a buffer in case we need to resize the tables. */ 2616 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2617 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2618 warn_report("ACPI table size %u exceeds %d bytes," 2619 " migration may not work", 2620 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2621 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2622 " or PCI bridges."); 2623 } 2624 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2625 } 2626 2627 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2628 2629 /* Cleanup memory that's no longer used. */ 2630 g_array_free(table_offsets, true); 2631 } 2632 2633 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2634 { 2635 uint32_t size = acpi_data_len(data); 2636 2637 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2638 memory_region_ram_resize(mr, size, &error_abort); 2639 2640 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2641 memory_region_set_dirty(mr, 0, size); 2642 } 2643 2644 static void acpi_build_update(void *build_opaque) 2645 { 2646 AcpiBuildState *build_state = build_opaque; 2647 AcpiBuildTables tables; 2648 2649 /* No state to update or already patched? Nothing to do. */ 2650 if (!build_state || build_state->patched) { 2651 return; 2652 } 2653 build_state->patched = 1; 2654 2655 acpi_build_tables_init(&tables); 2656 2657 acpi_build(&tables, MACHINE(qdev_get_machine())); 2658 2659 acpi_ram_update(build_state->table_mr, tables.table_data); 2660 2661 if (build_state->rsdp) { 2662 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2663 } else { 2664 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2665 } 2666 2667 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2668 acpi_build_tables_cleanup(&tables, true); 2669 } 2670 2671 static void acpi_build_reset(void *build_opaque) 2672 { 2673 AcpiBuildState *build_state = build_opaque; 2674 build_state->patched = 0; 2675 } 2676 2677 static const VMStateDescription vmstate_acpi_build = { 2678 .name = "acpi_build", 2679 .version_id = 1, 2680 .minimum_version_id = 1, 2681 .fields = (VMStateField[]) { 2682 VMSTATE_UINT8(patched, AcpiBuildState), 2683 VMSTATE_END_OF_LIST() 2684 }, 2685 }; 2686 2687 void acpi_setup(void) 2688 { 2689 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2690 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2691 X86MachineState *x86ms = X86_MACHINE(pcms); 2692 AcpiBuildTables tables; 2693 AcpiBuildState *build_state; 2694 Object *vmgenid_dev; 2695 TPMIf *tpm; 2696 static FwCfgTPMConfig tpm_config; 2697 2698 if (!x86ms->fw_cfg) { 2699 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2700 return; 2701 } 2702 2703 if (!pcms->acpi_build_enabled) { 2704 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2705 return; 2706 } 2707 2708 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2709 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2710 return; 2711 } 2712 2713 build_state = g_malloc0(sizeof *build_state); 2714 2715 acpi_build_tables_init(&tables); 2716 acpi_build(&tables, MACHINE(pcms)); 2717 2718 /* Now expose it all to Guest */ 2719 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2720 build_state, tables.table_data, 2721 ACPI_BUILD_TABLE_FILE, 2722 ACPI_BUILD_TABLE_MAX_SIZE); 2723 assert(build_state->table_mr != NULL); 2724 2725 build_state->linker_mr = 2726 acpi_add_rom_blob(acpi_build_update, build_state, 2727 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0); 2728 2729 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2730 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2731 2732 tpm = tpm_find(); 2733 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2734 tpm_config = (FwCfgTPMConfig) { 2735 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2736 .tpm_version = tpm_get_version(tpm), 2737 .tpmppi_version = TPM_PPI_VERSION_1_30 2738 }; 2739 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2740 &tpm_config, sizeof tpm_config); 2741 } 2742 2743 vmgenid_dev = find_vmgenid_dev(); 2744 if (vmgenid_dev) { 2745 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2746 tables.vmgenid); 2747 } 2748 2749 if (!pcmc->rsdp_in_ram) { 2750 /* 2751 * Keep for compatibility with old machine types. 2752 * Though RSDP is small, its contents isn't immutable, so 2753 * we'll update it along with the rest of tables on guest access. 2754 */ 2755 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2756 2757 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2758 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2759 acpi_build_update, NULL, build_state, 2760 build_state->rsdp, rsdp_size, true); 2761 build_state->rsdp_mr = NULL; 2762 } else { 2763 build_state->rsdp = NULL; 2764 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2765 build_state, tables.rsdp, 2766 ACPI_BUILD_RSDP_FILE, 0); 2767 } 2768 2769 qemu_register_reset(acpi_build_reset, build_state); 2770 acpi_build_reset(build_state); 2771 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2772 2773 /* Cleanup tables but don't free the memory: we track it 2774 * in build_state. 2775 */ 2776 acpi_build_tables_cleanup(&tables, false); 2777 } 2778