1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "system/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "system/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "system/numa.h" 54 #include "system/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/ich9.h" 59 #include "hw/acpi/pcihp.h" 60 #include "hw/i386/fw_cfg.h" 61 #include "hw/i386/pc.h" 62 #include "hw/pci/pci_bus.h" 63 #include "hw/pci-host/i440fx.h" 64 #include "hw/pci-host/q35.h" 65 #include "hw/i386/x86-iommu.h" 66 67 #include "hw/acpi/aml-build.h" 68 #include "hw/acpi/utils.h" 69 #include "hw/acpi/pci.h" 70 #include "hw/acpi/cxl.h" 71 72 #include "qom/qom-qobject.h" 73 #include "hw/i386/amd_iommu.h" 74 #include "hw/i386/intel_iommu.h" 75 #include "hw/virtio/virtio-iommu.h" 76 77 #include "hw/acpi/hmat.h" 78 #include "hw/acpi/viot.h" 79 80 #include CONFIG_DEVICES 81 82 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 83 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 84 * a little bit, there should be plenty of free space since the DSDT 85 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 86 */ 87 #define ACPI_BUILD_ALIGN_SIZE 0x1000 88 89 #define ACPI_BUILD_TABLE_SIZE 0x20000 90 91 /* #define DEBUG_ACPI_BUILD */ 92 #ifdef DEBUG_ACPI_BUILD 93 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 94 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 95 #else 96 #define ACPI_BUILD_DPRINTF(fmt, ...) 97 #endif 98 99 typedef struct AcpiPmInfo { 100 bool s3_disabled; 101 bool s4_disabled; 102 bool pcihp_bridge_en; 103 bool smi_on_cpuhp; 104 bool smi_on_cpu_unplug; 105 bool pcihp_root_en; 106 uint8_t s4_val; 107 AcpiFadtData fadt; 108 uint16_t cpu_hp_io_base; 109 uint16_t pcihp_io_base; 110 uint16_t pcihp_io_len; 111 } AcpiPmInfo; 112 113 typedef struct AcpiMiscInfo { 114 bool has_hpet; 115 #ifdef CONFIG_TPM 116 TPMVersion tpm_version; 117 #endif 118 } AcpiMiscInfo; 119 120 typedef struct FwCfgTPMConfig { 121 uint32_t tpmppi_address; 122 uint8_t tpm_version; 123 uint8_t tpmppi_version; 124 } QEMU_PACKED FwCfgTPMConfig; 125 126 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 127 128 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 129 .space_id = AML_AS_SYSTEM_IO, 130 .address = NVDIMM_ACPI_IO_BASE, 131 .bit_width = NVDIMM_ACPI_IO_LEN << 3 132 }; 133 134 static void init_common_fadt_data(MachineState *ms, Object *o, 135 AcpiFadtData *data) 136 { 137 X86MachineState *x86ms = X86_MACHINE(ms); 138 /* 139 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 140 * behavior for compatibility irrelevant to smm_enabled, which doesn't 141 * comforms to ACPI spec. 142 */ 143 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 144 true : x86_machine_is_smm_enabled(x86ms); 145 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 146 AmlAddressSpace as = AML_AS_SYSTEM_IO; 147 AcpiFadtData fadt = { 148 .rev = 3, 149 .flags = 150 (1 << ACPI_FADT_F_WBINVD) | 151 (1 << ACPI_FADT_F_PROC_C1) | 152 (1 << ACPI_FADT_F_SLP_BUTTON) | 153 (1 << ACPI_FADT_F_RTC_S4) | 154 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 155 /* APIC destination mode ("Flat Logical") has an upper limit of 8 156 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 157 * used 158 */ 159 ((ms->smp.max_cpus > 8) ? 160 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 161 .int_model = 1 /* Multiple APIC */, 162 .rtc_century = RTC_CENTURY, 163 .plvl2_lat = 0xfff /* C2 state not supported */, 164 .plvl3_lat = 0xfff /* C3 state not supported */, 165 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 166 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 167 .acpi_enable_cmd = 168 smm_enabled ? 169 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 170 0, 171 .acpi_disable_cmd = 172 smm_enabled ? 173 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 174 0, 175 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 176 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 177 .address = io + 0x04 }, 178 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 179 .gpe0_blk = { .space_id = as, .bit_width = 180 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 181 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 182 }, 183 }; 184 185 /* 186 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 187 * Flags, bit offset 1 - 8042. 188 */ 189 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 190 191 *data = fadt; 192 } 193 194 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 195 { 196 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL); 197 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL); 198 Object *obj = piix ? piix : lpc; 199 QObject *o; 200 pm->cpu_hp_io_base = 0; 201 pm->pcihp_io_base = 0; 202 pm->pcihp_io_len = 0; 203 pm->smi_on_cpuhp = false; 204 pm->smi_on_cpu_unplug = false; 205 206 assert(obj); 207 init_common_fadt_data(machine, obj, &pm->fadt); 208 if (piix) { 209 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 210 pm->fadt.rev = 1; 211 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 212 } 213 if (lpc) { 214 uint64_t smi_features = object_property_get_uint(lpc, 215 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 216 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 217 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 218 pm->fadt.reset_reg = r; 219 pm->fadt.reset_val = 0xf; 220 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 221 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 222 pm->smi_on_cpuhp = 223 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 224 pm->smi_on_cpu_unplug = 225 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 226 } 227 pm->pcihp_io_base = 228 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 229 pm->pcihp_io_len = 230 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 231 232 /* Fill in optional s3/s4 related properties */ 233 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 234 if (o) { 235 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 236 } else { 237 pm->s3_disabled = false; 238 } 239 qobject_unref(o); 240 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 241 if (o) { 242 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 243 } else { 244 pm->s4_disabled = false; 245 } 246 qobject_unref(o); 247 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 248 if (o) { 249 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 250 } else { 251 pm->s4_val = false; 252 } 253 qobject_unref(o); 254 255 pm->pcihp_bridge_en = 256 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 257 NULL); 258 pm->pcihp_root_en = 259 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 260 NULL); 261 } 262 263 static void acpi_get_misc_info(AcpiMiscInfo *info) 264 { 265 info->has_hpet = hpet_find(); 266 #ifdef CONFIG_TPM 267 info->tpm_version = tpm_get_version(tpm_find()); 268 #endif 269 } 270 271 /* 272 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 273 * On i386 arch we only have two pci hosts, so we can look only for them. 274 */ 275 Object *acpi_get_i386_pci_host(void) 276 { 277 PCIHostState *host; 278 279 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 280 if (!host) { 281 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 282 } 283 284 return OBJECT(host); 285 } 286 287 static void acpi_get_pci_holes(Range *hole, Range *hole64) 288 { 289 Object *pci_host; 290 291 pci_host = acpi_get_i386_pci_host(); 292 293 if (!pci_host) { 294 return; 295 } 296 297 range_set_bounds1(hole, 298 object_property_get_uint(pci_host, 299 PCI_HOST_PROP_PCI_HOLE_START, 300 NULL), 301 object_property_get_uint(pci_host, 302 PCI_HOST_PROP_PCI_HOLE_END, 303 NULL)); 304 range_set_bounds1(hole64, 305 object_property_get_uint(pci_host, 306 PCI_HOST_PROP_PCI_HOLE64_START, 307 NULL), 308 object_property_get_uint(pci_host, 309 PCI_HOST_PROP_PCI_HOLE64_END, 310 NULL)); 311 } 312 313 static void acpi_align_size(GArray *blob, unsigned align) 314 { 315 /* Align size to multiple of given size. This reduces the chance 316 * we need to change size in the future (breaking cross version migration). 317 */ 318 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 319 } 320 321 /* 322 * ACPI spec 1.0b, 323 * 5.2.6 Firmware ACPI Control Structure 324 */ 325 static void 326 build_facs(GArray *table_data) 327 { 328 const char *sig = "FACS"; 329 const uint8_t reserved[40] = {}; 330 331 g_array_append_vals(table_data, sig, 4); /* Signature */ 332 build_append_int_noprefix(table_data, 64, 4); /* Length */ 333 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 334 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 335 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 336 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 337 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 338 } 339 340 Aml *aml_pci_device_dsm(void) 341 { 342 Aml *method; 343 344 method = aml_method("_DSM", 4, AML_SERIALIZED); 345 { 346 Aml *params = aml_local(0); 347 Aml *pkg = aml_package(2); 348 aml_append(pkg, aml_int(0)); 349 aml_append(pkg, aml_int(0)); 350 aml_append(method, aml_store(pkg, params)); 351 aml_append(method, 352 aml_store(aml_name("BSEL"), aml_index(params, aml_int(0)))); 353 aml_append(method, 354 aml_store(aml_name("ASUN"), aml_index(params, aml_int(1)))); 355 aml_append(method, 356 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 357 aml_arg(2), aml_arg(3), params)) 358 ); 359 } 360 return method; 361 } 362 363 static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar) 364 { 365 Aml *UUID, *ifctx1; 366 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 367 368 aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar)); 369 /* 370 * PCI Firmware Specification 3.1 371 * 4.6. _DSM Definitions for PCI 372 */ 373 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 374 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 375 { 376 /* call is for unsupported UUID, bail out */ 377 aml_append(ifctx1, aml_return(retvar)); 378 } 379 aml_append(ctx, ifctx1); 380 381 ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2))); 382 { 383 /* call is for unsupported REV, bail out */ 384 aml_append(ifctx1, aml_return(retvar)); 385 } 386 aml_append(ctx, ifctx1); 387 } 388 389 static Aml *aml_pci_edsm(void) 390 { 391 Aml *method, *ifctx; 392 Aml *zero = aml_int(0); 393 Aml *func = aml_arg(2); 394 Aml *ret = aml_local(0); 395 Aml *aidx = aml_local(1); 396 Aml *params = aml_arg(4); 397 398 method = aml_method("EDSM", 5, AML_SERIALIZED); 399 400 /* get supported functions */ 401 ifctx = aml_if(aml_equal(func, zero)); 402 { 403 /* 1: have supported functions */ 404 /* 7: support for function 7 */ 405 const uint8_t caps = 1 | BIT(7); 406 build_append_pci_dsm_func0_common(ifctx, ret); 407 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); 408 aml_append(ifctx, aml_return(ret)); 409 } 410 aml_append(method, ifctx); 411 412 /* handle specific functions requests */ 413 /* 414 * PCI Firmware Specification 3.1 415 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 416 * Operating Systems 417 */ 418 ifctx = aml_if(aml_equal(func, aml_int(7))); 419 { 420 Aml *pkg = aml_package(2); 421 aml_append(pkg, zero); 422 /* optional, if not impl. should return null string */ 423 aml_append(pkg, aml_string("%s", "")); 424 aml_append(ifctx, aml_store(pkg, ret)); 425 426 /* 427 * IASL is fine when initializing Package with computational data, 428 * however it makes guest unhappy /it fails to process such AML/. 429 * So use runtime assignment to set acpi-index after initializer 430 * to make OSPM happy. 431 */ 432 aml_append(ifctx, 433 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); 434 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); 435 aml_append(ifctx, aml_return(ret)); 436 } 437 aml_append(method, ifctx); 438 439 return method; 440 } 441 442 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev) 443 { 444 Aml *method; 445 446 g_assert(pdev->acpi_index != 0); 447 method = aml_method("_DSM", 4, AML_SERIALIZED); 448 { 449 Aml *params = aml_local(0); 450 Aml *pkg = aml_package(1); 451 aml_append(pkg, aml_int(pdev->acpi_index)); 452 aml_append(method, aml_store(pkg, params)); 453 aml_append(method, 454 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1), 455 aml_arg(2), aml_arg(3), params)) 456 ); 457 } 458 return method; 459 } 460 461 static void build_append_pcihp_notify_entry(Aml *method, int slot) 462 { 463 Aml *if_ctx; 464 int32_t devfn = PCI_DEVFN(slot, 0); 465 466 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 467 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 468 aml_append(method, if_ctx); 469 } 470 471 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) 472 { 473 const PCIDevice *pdev = bus->devices[devfn]; 474 475 if (PCI_FUNC(devfn)) { 476 if (IS_PCI_BRIDGE(pdev)) { 477 /* 478 * Ignore only hotplugged PCI bridges on !0 functions, but 479 * allow describing cold plugged bridges on all functions 480 */ 481 if (DEVICE(pdev)->hotplugged) { 482 return true; 483 } 484 } 485 } 486 return false; 487 } 488 489 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) 490 { 491 PCIDevice *pdev = bus->devices[devfn]; 492 if (pdev) { 493 return is_devfn_ignored_generic(devfn, bus) || 494 !DEVICE_GET_CLASS(pdev)->hotpluggable || 495 /* Cold plugged bridges aren't themselves hot-pluggable */ 496 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); 497 } else { /* non populated slots */ 498 /* 499 * hotplug is supported only for non-multifunction device 500 * so generate device description only for function 0 501 */ 502 if (PCI_FUNC(devfn) || 503 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { 504 return true; 505 } 506 } 507 return false; 508 } 509 510 void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus) 511 { 512 int devfn; 513 Aml *dev, *notify_method = NULL, *method; 514 QObject *bsel = object_property_get_qobject(OBJECT(bus), 515 ACPI_PCIHP_PROP_BSEL, NULL); 516 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 517 qobject_unref(bsel); 518 519 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 520 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 521 522 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 523 int slot = PCI_SLOT(devfn); 524 int adr = slot << 16 | PCI_FUNC(devfn); 525 526 if (is_devfn_ignored_hotplug(devfn, bus)) { 527 continue; 528 } 529 530 if (bus->devices[devfn]) { 531 dev = aml_scope("S%.02X", devfn); 532 } else { 533 dev = aml_device("S%.02X", devfn); 534 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 535 } 536 537 /* 538 * Can't declare _SUN here for every device as it changes 'slot' 539 * enumeration order in linux kernel, so use another variable for it 540 */ 541 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 542 aml_append(dev, aml_pci_device_dsm()); 543 544 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 545 /* add _EJ0 to make slot hotpluggable */ 546 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 547 aml_append(method, 548 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 549 ); 550 aml_append(dev, method); 551 552 build_append_pcihp_notify_entry(notify_method, slot); 553 554 /* device descriptor has been composed, add it into parent context */ 555 aml_append(parent_scope, dev); 556 } 557 aml_append(parent_scope, notify_method); 558 } 559 560 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) 561 { 562 int devfn; 563 Aml *dev; 564 565 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 566 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 567 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); 568 PCIDevice *pdev = bus->devices[devfn]; 569 570 if (!pdev || is_devfn_ignored_generic(devfn, bus)) { 571 continue; 572 } 573 574 /* start to compose PCI device descriptor */ 575 dev = aml_device("S%.02X", devfn); 576 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 577 578 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); 579 /* add _DSM if device has acpi-index set */ 580 if (pdev->acpi_index && 581 !object_property_get_bool(OBJECT(pdev), "hotpluggable", 582 &error_abort)) { 583 aml_append(dev, aml_pci_static_endpoint_dsm(pdev)); 584 } 585 586 /* device descriptor has been composed, add it into parent context */ 587 aml_append(parent_scope, dev); 588 } 589 } 590 591 static bool build_append_notfication_callback(Aml *parent_scope, 592 const PCIBus *bus) 593 { 594 Aml *method; 595 PCIBus *sec; 596 QObject *bsel; 597 int nr_notifiers = 0; 598 GQueue *pcnt_bus_list = g_queue_new(); 599 600 QLIST_FOREACH(sec, &bus->child, sibling) { 601 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn); 602 if (pci_bus_is_root(sec)) { 603 continue; 604 } 605 nr_notifiers = nr_notifiers + 606 build_append_notfication_callback(br_scope, sec); 607 /* 608 * add new child scope to parent 609 * and keep track of bus that have PCNT, 610 * bus list is used later to call children PCNTs from this level PCNT 611 */ 612 if (nr_notifiers) { 613 g_queue_push_tail(pcnt_bus_list, sec); 614 aml_append(parent_scope, br_scope); 615 } 616 } 617 618 /* 619 * Append PCNT method to notify about events on local and child buses. 620 * ps: hostbridge might not have hotplug (bsel) enabled but might have 621 * child bridges that do have bsel. 622 */ 623 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 624 625 /* If bus supports hotplug select it and notify about local events */ 626 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 627 if (bsel) { 628 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 629 630 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 631 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 632 aml_int(1))); /* Device Check */ 633 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 634 aml_int(3))); /* Eject Request */ 635 nr_notifiers++; 636 } 637 638 /* Notify about child bus events in any case */ 639 while ((sec = g_queue_pop_head(pcnt_bus_list))) { 640 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn)); 641 } 642 643 aml_append(parent_scope, method); 644 qobject_unref(bsel); 645 g_queue_free(pcnt_bus_list); 646 return !!nr_notifiers; 647 } 648 649 static Aml *aml_pci_pdsm(void) 650 { 651 Aml *method, *ifctx, *ifctx1; 652 Aml *ret = aml_local(0); 653 Aml *caps = aml_local(1); 654 Aml *acpi_index = aml_local(2); 655 Aml *zero = aml_int(0); 656 Aml *one = aml_int(1); 657 Aml *not_supp = aml_int(0xFFFFFFFF); 658 Aml *func = aml_arg(2); 659 Aml *params = aml_arg(4); 660 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 661 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 662 663 method = aml_method("PDSM", 5, AML_SERIALIZED); 664 665 /* get supported functions */ 666 ifctx = aml_if(aml_equal(func, zero)); 667 { 668 build_append_pci_dsm_func0_common(ifctx, ret); 669 670 aml_append(ifctx, aml_store(zero, caps)); 671 aml_append(ifctx, 672 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 673 /* 674 * advertise function 7 if device has acpi-index 675 * acpi_index values: 676 * 0: not present (default value) 677 * FFFFFFFF: not supported (old QEMU without PIDX reg) 678 * other: device's acpi-index 679 */ 680 ifctx1 = aml_if(aml_lnot( 681 aml_or(aml_equal(acpi_index, zero), 682 aml_equal(acpi_index, not_supp), NULL) 683 )); 684 { 685 /* have supported functions */ 686 aml_append(ifctx1, aml_or(caps, one, caps)); 687 /* support for function 7 */ 688 aml_append(ifctx1, 689 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 690 } 691 aml_append(ifctx, ifctx1); 692 693 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 694 aml_append(ifctx, aml_return(ret)); 695 } 696 aml_append(method, ifctx); 697 698 /* handle specific functions requests */ 699 /* 700 * PCI Firmware Specification 3.1 701 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 702 * Operating Systems 703 */ 704 ifctx = aml_if(aml_equal(func, aml_int(7))); 705 { 706 Aml *pkg = aml_package(2); 707 708 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 709 aml_append(ifctx, aml_store(pkg, ret)); 710 /* 711 * Windows calls func=7 without checking if it's available, 712 * as workaround Microsoft has suggested to return invalid for func7 713 * Package, so return 2 elements package but only initialize elements 714 * when acpi_index is supported and leave them uninitialized, which 715 * leads elements to being Uninitialized ObjectType and should trip 716 * Windows into discarding result as an unexpected and prevent setting 717 * bogus 'PCI Label' on the device. 718 */ 719 ifctx1 = aml_if(aml_lnot(aml_lor( 720 aml_equal(acpi_index, zero), aml_equal(acpi_index, not_supp) 721 ))); 722 { 723 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); 724 /* 725 * optional, if not impl. should return null string 726 */ 727 aml_append(ifctx1, aml_store(aml_string("%s", ""), 728 aml_index(ret, one))); 729 } 730 aml_append(ifctx, ifctx1); 731 732 aml_append(ifctx, aml_return(ret)); 733 } 734 735 aml_append(method, ifctx); 736 return method; 737 } 738 739 /* 740 * build_prt - Define interrupt routing rules 741 * 742 * Returns an array of 128 routes, one for each device, 743 * based on device location. 744 * The main goal is to equally distribute the interrupts 745 * over the 4 existing ACPI links (works only for i440fx). 746 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]". 747 * 748 */ 749 static Aml *build_prt(bool is_pci0_prt) 750 { 751 const int nroutes = 128; 752 Aml *rt_pkg, *method; 753 int pin; 754 755 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 756 assert(nroutes < 256); 757 rt_pkg = aml_package(nroutes); 758 759 for (pin = 0; pin < nroutes; pin++) { 760 Aml *pkg = aml_package(4); 761 int slot = pin >> 2; 762 763 aml_append(pkg, aml_int((slot << 16) | 0xFFFF)); 764 aml_append(pkg, aml_int(pin & 3)); 765 /* device 1 is the power-management device, needs SCI */ 766 if (is_pci0_prt && pin == 4) { 767 aml_append(pkg, aml_name("%s", "LNKS")); 768 } else { 769 static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"}; 770 int hash = (slot + pin) & 3; 771 aml_append(pkg, aml_name("%s", link_name[hash])); 772 } 773 aml_append(pkg, aml_int(0)); 774 aml_append(rt_pkg, pkg); 775 } 776 777 aml_append(method, aml_return(rt_pkg)); 778 779 return method; 780 } 781 782 static void build_hpet_aml(Aml *table) 783 { 784 Aml *crs; 785 Aml *field; 786 Aml *method; 787 Aml *if_ctx; 788 Aml *scope = aml_scope("_SB"); 789 Aml *dev = aml_device("HPET"); 790 Aml *zero = aml_int(0); 791 Aml *id = aml_local(0); 792 Aml *period = aml_local(1); 793 794 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 795 aml_append(dev, aml_name_decl("_UID", zero)); 796 797 aml_append(dev, 798 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 799 HPET_LEN)); 800 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 801 aml_append(field, aml_named_field("VEND", 32)); 802 aml_append(field, aml_named_field("PRD", 32)); 803 aml_append(dev, field); 804 805 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 806 aml_append(method, aml_store(aml_name("VEND"), id)); 807 aml_append(method, aml_store(aml_name("PRD"), period)); 808 aml_append(method, aml_shiftright(id, aml_int(16), id)); 809 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 810 aml_equal(id, aml_int(0xffff)))); 811 { 812 aml_append(if_ctx, aml_return(zero)); 813 } 814 aml_append(method, if_ctx); 815 816 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 817 aml_lgreater(period, aml_int(100000000)))); 818 { 819 aml_append(if_ctx, aml_return(zero)); 820 } 821 aml_append(method, if_ctx); 822 823 aml_append(method, aml_return(aml_int(0x0F))); 824 aml_append(dev, method); 825 826 crs = aml_resource_template(); 827 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 828 aml_append(dev, aml_name_decl("_CRS", crs)); 829 830 aml_append(scope, dev); 831 aml_append(table, scope); 832 } 833 834 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 835 { 836 Aml *dev; 837 Aml *method; 838 Aml *crs; 839 840 dev = aml_device("VMBS"); 841 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 842 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 843 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 844 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 845 846 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 847 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 848 aml_name("STA"))); 849 aml_append(dev, method); 850 851 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 852 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 853 aml_name("STA"))); 854 aml_append(dev, method); 855 856 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 857 aml_append(method, aml_return(aml_name("STA"))); 858 aml_append(dev, method); 859 860 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 861 862 crs = aml_resource_template(); 863 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 864 aml_append(dev, aml_name_decl("_CRS", crs)); 865 866 return dev; 867 } 868 869 static void build_dbg_aml(Aml *table) 870 { 871 Aml *field; 872 Aml *method; 873 Aml *while_ctx; 874 Aml *scope = aml_scope("\\"); 875 Aml *buf = aml_local(0); 876 Aml *len = aml_local(1); 877 Aml *idx = aml_local(2); 878 879 aml_append(scope, 880 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 881 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 882 aml_append(field, aml_named_field("DBGB", 8)); 883 aml_append(scope, field); 884 885 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 886 887 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 888 aml_append(method, aml_to_buffer(buf, buf)); 889 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 890 aml_append(method, aml_store(aml_int(0), idx)); 891 892 while_ctx = aml_while(aml_lless(idx, len)); 893 aml_append(while_ctx, 894 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 895 aml_append(while_ctx, aml_increment(idx)); 896 aml_append(method, while_ctx); 897 898 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 899 aml_append(scope, method); 900 901 aml_append(table, scope); 902 } 903 904 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 905 { 906 Aml *dev; 907 Aml *crs; 908 Aml *method; 909 uint32_t irqs[] = {5, 10, 11}; 910 911 dev = aml_device("%s", name); 912 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 913 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 914 915 crs = aml_resource_template(); 916 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 917 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 918 aml_append(dev, aml_name_decl("_PRS", crs)); 919 920 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 921 aml_append(method, aml_return(aml_call1("IQST", reg))); 922 aml_append(dev, method); 923 924 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 925 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 926 aml_append(dev, method); 927 928 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 929 aml_append(method, aml_return(aml_call1("IQCR", reg))); 930 aml_append(dev, method); 931 932 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 933 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 934 aml_append(method, aml_store(aml_name("PRRI"), reg)); 935 aml_append(dev, method); 936 937 return dev; 938 } 939 940 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 941 { 942 Aml *dev; 943 Aml *crs; 944 Aml *method; 945 uint32_t irqs; 946 947 dev = aml_device("%s", name); 948 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 949 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 950 951 crs = aml_resource_template(); 952 irqs = gsi; 953 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 954 AML_SHARED, &irqs, 1)); 955 aml_append(dev, aml_name_decl("_PRS", crs)); 956 957 aml_append(dev, aml_name_decl("_CRS", crs)); 958 959 /* 960 * _DIS can be no-op because the interrupt cannot be disabled. 961 */ 962 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 963 aml_append(dev, method); 964 965 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 966 aml_append(dev, method); 967 968 return dev; 969 } 970 971 /* _CRS method - get current settings */ 972 static Aml *build_iqcr_method(bool is_piix4) 973 { 974 Aml *if_ctx; 975 uint32_t irqs; 976 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 977 Aml *crs = aml_resource_template(); 978 979 irqs = 0; 980 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 981 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 982 aml_append(method, aml_name_decl("PRR0", crs)); 983 984 aml_append(method, 985 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 986 987 if (is_piix4) { 988 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 989 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 990 aml_append(method, if_ctx); 991 } else { 992 aml_append(method, 993 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 994 aml_name("PRRI"))); 995 } 996 997 aml_append(method, aml_return(aml_name("PRR0"))); 998 return method; 999 } 1000 1001 /* _STA method - get status */ 1002 static Aml *build_irq_status_method(void) 1003 { 1004 Aml *if_ctx; 1005 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1006 1007 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1008 aml_append(if_ctx, aml_return(aml_int(0x09))); 1009 aml_append(method, if_ctx); 1010 aml_append(method, aml_return(aml_int(0x0B))); 1011 return method; 1012 } 1013 1014 static void build_piix4_pci0_int(Aml *table) 1015 { 1016 Aml *dev; 1017 Aml *crs; 1018 Aml *method; 1019 uint32_t irqs; 1020 Aml *sb_scope = aml_scope("_SB"); 1021 Aml *pci0_scope = aml_scope("PCI0"); 1022 1023 aml_append(pci0_scope, build_prt(true)); 1024 aml_append(sb_scope, pci0_scope); 1025 1026 aml_append(sb_scope, build_irq_status_method()); 1027 aml_append(sb_scope, build_iqcr_method(true)); 1028 1029 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1030 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1031 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1032 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1033 1034 dev = aml_device("LNKS"); 1035 { 1036 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1037 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1038 1039 crs = aml_resource_template(); 1040 irqs = 9; 1041 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1042 AML_ACTIVE_HIGH, AML_SHARED, 1043 &irqs, 1)); 1044 aml_append(dev, aml_name_decl("_PRS", crs)); 1045 1046 /* The SCI cannot be disabled and is always attached to GSI 9, 1047 * so these are no-ops. We only need this link to override the 1048 * polarity to active high and match the content of the MADT. 1049 */ 1050 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1051 aml_append(method, aml_return(aml_int(0x0b))); 1052 aml_append(dev, method); 1053 1054 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1055 aml_append(dev, method); 1056 1057 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1058 aml_append(method, aml_return(aml_name("_PRS"))); 1059 aml_append(dev, method); 1060 1061 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1062 aml_append(dev, method); 1063 } 1064 aml_append(sb_scope, dev); 1065 1066 aml_append(table, sb_scope); 1067 } 1068 1069 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1070 { 1071 int i; 1072 int head; 1073 Aml *pkg; 1074 char base = name[3] < 'E' ? 'A' : 'E'; 1075 char *s = g_strdup(name); 1076 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1077 1078 assert(strlen(s) == 4); 1079 1080 head = name[3] - base; 1081 for (i = 0; i < 4; i++) { 1082 if (head + i > 3) { 1083 head = i * -1; 1084 } 1085 s[3] = base + head + i; 1086 pkg = aml_package(4); 1087 aml_append(pkg, a_nr); 1088 aml_append(pkg, aml_int(i)); 1089 aml_append(pkg, aml_name("%s", s)); 1090 aml_append(pkg, aml_int(0)); 1091 aml_append(ctx, pkg); 1092 } 1093 g_free(s); 1094 } 1095 1096 static Aml *build_q35_routing_table(const char *str) 1097 { 1098 int i; 1099 Aml *pkg; 1100 char *name = g_strdup_printf("%s ", str); 1101 1102 pkg = aml_package(128); 1103 for (i = 0; i < 0x18; i++) { 1104 name[3] = 'E' + (i & 0x3); 1105 append_q35_prt_entry(pkg, i, name); 1106 } 1107 1108 name[3] = 'E'; 1109 append_q35_prt_entry(pkg, 0x18, name); 1110 1111 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1112 for (i = 0x0019; i < 0x1e; i++) { 1113 name[3] = 'A'; 1114 append_q35_prt_entry(pkg, i, name); 1115 } 1116 1117 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1118 name[3] = 'E'; 1119 append_q35_prt_entry(pkg, 0x1e, name); 1120 name[3] = 'A'; 1121 append_q35_prt_entry(pkg, 0x1f, name); 1122 1123 g_free(name); 1124 return pkg; 1125 } 1126 1127 static void build_q35_pci0_int(Aml *table) 1128 { 1129 Aml *method; 1130 Aml *sb_scope = aml_scope("_SB"); 1131 Aml *pci0_scope = aml_scope("PCI0"); 1132 1133 /* Zero => PIC mode, One => APIC Mode */ 1134 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1135 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1136 { 1137 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1138 } 1139 aml_append(table, method); 1140 1141 aml_append(pci0_scope, 1142 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1143 aml_append(pci0_scope, 1144 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1145 1146 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1147 { 1148 Aml *if_ctx; 1149 Aml *else_ctx; 1150 1151 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1152 section 6.2.8.1 */ 1153 /* Note: we provide the same info as the PCI routing 1154 table of the Bochs BIOS */ 1155 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1156 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1157 aml_append(method, if_ctx); 1158 else_ctx = aml_else(); 1159 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1160 aml_append(method, else_ctx); 1161 } 1162 aml_append(pci0_scope, method); 1163 aml_append(sb_scope, pci0_scope); 1164 1165 aml_append(sb_scope, build_irq_status_method()); 1166 aml_append(sb_scope, build_iqcr_method(false)); 1167 1168 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1169 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1170 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1171 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1172 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1173 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1174 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1175 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1176 1177 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1178 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1179 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1180 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1181 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1182 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1183 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1184 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1185 1186 aml_append(table, sb_scope); 1187 } 1188 1189 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1190 { 1191 Aml *dev; 1192 Aml *resource_template; 1193 1194 /* DRAM controller */ 1195 dev = aml_device("DRAC"); 1196 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1197 1198 resource_template = aml_resource_template(); 1199 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1200 aml_append(resource_template, 1201 aml_qword_memory(AML_POS_DECODE, 1202 AML_MIN_FIXED, 1203 AML_MAX_FIXED, 1204 AML_NON_CACHEABLE, 1205 AML_READ_WRITE, 1206 0x0000000000000000, 1207 mcfg->base, 1208 mcfg->base + mcfg->size - 1, 1209 0x0000000000000000, 1210 mcfg->size)); 1211 } else { 1212 aml_append(resource_template, 1213 aml_dword_memory(AML_POS_DECODE, 1214 AML_MIN_FIXED, 1215 AML_MAX_FIXED, 1216 AML_NON_CACHEABLE, 1217 AML_READ_WRITE, 1218 0x0000000000000000, 1219 mcfg->base, 1220 mcfg->base + mcfg->size - 1, 1221 0x0000000000000000, 1222 mcfg->size)); 1223 } 1224 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1225 1226 return dev; 1227 } 1228 1229 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1230 { 1231 Aml *scope; 1232 Aml *field; 1233 Aml *method; 1234 1235 scope = aml_scope("_SB.PCI0"); 1236 1237 aml_append(scope, 1238 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1239 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1240 aml_append(field, aml_named_field("PCIU", 32)); 1241 aml_append(field, aml_named_field("PCID", 32)); 1242 aml_append(scope, field); 1243 1244 aml_append(scope, 1245 aml_operation_region("SEJ", AML_SYSTEM_IO, 1246 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1247 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1248 aml_append(field, aml_named_field("B0EJ", 32)); 1249 aml_append(scope, field); 1250 1251 aml_append(scope, 1252 aml_operation_region("BNMR", AML_SYSTEM_IO, 1253 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1254 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1255 aml_append(field, aml_named_field("BNUM", 32)); 1256 aml_append(field, aml_named_field("PIDX", 32)); 1257 aml_append(scope, field); 1258 1259 aml_append(scope, aml_mutex("BLCK", 0)); 1260 1261 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1262 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1263 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1264 aml_append(method, 1265 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1266 aml_append(method, aml_release(aml_name("BLCK"))); 1267 aml_append(method, aml_return(aml_int(0))); 1268 aml_append(scope, method); 1269 1270 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1271 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1272 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1273 aml_append(method, 1274 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1275 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1276 aml_append(method, aml_release(aml_name("BLCK"))); 1277 aml_append(method, aml_return(aml_local(0))); 1278 aml_append(scope, method); 1279 1280 aml_append(scope, aml_pci_pdsm()); 1281 1282 aml_append(table, scope); 1283 } 1284 1285 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1286 { 1287 Aml *if_ctx; 1288 Aml *if_ctx2; 1289 Aml *else_ctx; 1290 Aml *method; 1291 Aml *a_cwd1 = aml_name("CDW1"); 1292 Aml *a_ctrl = aml_local(0); 1293 1294 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1295 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1296 1297 if_ctx = aml_if(aml_equal( 1298 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1299 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1300 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1301 1302 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1303 1304 /* 1305 * Always allow native PME, AER (no dependencies) 1306 * Allow SHPC (PCI bridges can have SHPC controller) 1307 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1308 */ 1309 aml_append(if_ctx, aml_and(a_ctrl, 1310 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1311 1312 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1313 /* Unknown revision */ 1314 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1315 aml_append(if_ctx, if_ctx2); 1316 1317 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1318 /* Capabilities bits were masked */ 1319 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1320 aml_append(if_ctx, if_ctx2); 1321 1322 /* Update DWORD3 in the buffer */ 1323 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1324 aml_append(method, if_ctx); 1325 1326 else_ctx = aml_else(); 1327 /* Unrecognized UUID */ 1328 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1329 aml_append(method, else_ctx); 1330 1331 aml_append(method, aml_return(aml_arg(3))); 1332 return method; 1333 } 1334 1335 static void build_acpi0017(Aml *table) 1336 { 1337 Aml *dev, *scope, *method; 1338 1339 scope = aml_scope("_SB"); 1340 dev = aml_device("CXLM"); 1341 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1342 1343 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1344 aml_append(method, aml_return(aml_int(0x0B))); 1345 aml_append(dev, method); 1346 build_cxl_dsm_method(dev); 1347 1348 aml_append(scope, dev); 1349 aml_append(table, scope); 1350 } 1351 1352 static void 1353 build_dsdt(GArray *table_data, BIOSLinker *linker, 1354 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1355 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1356 { 1357 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE, 1358 NULL); 1359 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL); 1360 CrsRangeEntry *entry; 1361 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1362 CrsRangeSet crs_range_set; 1363 PCMachineState *pcms = PC_MACHINE(machine); 1364 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1365 X86MachineState *x86ms = X86_MACHINE(machine); 1366 AcpiMcfgInfo mcfg; 1367 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1368 uint32_t nr_mem = machine->ram_slots; 1369 int root_bus_limit = 0xFF; 1370 PCIBus *bus = NULL; 1371 #ifdef CONFIG_TPM 1372 TPMIf *tpm = tpm_find(); 1373 #endif 1374 bool cxl_present = false; 1375 int i; 1376 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1377 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1378 .oem_table_id = x86ms->oem_table_id }; 1379 1380 assert(!!i440fx != !!q35); 1381 1382 acpi_table_begin(&table, table_data); 1383 dsdt = init_aml_allocator(); 1384 1385 build_dbg_aml(dsdt); 1386 if (i440fx) { 1387 sb_scope = aml_scope("_SB"); 1388 dev = aml_device("PCI0"); 1389 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1390 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1391 aml_append(dev, aml_pci_edsm()); 1392 aml_append(sb_scope, dev); 1393 aml_append(dsdt, sb_scope); 1394 1395 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1396 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1397 } 1398 build_piix4_pci0_int(dsdt); 1399 } else if (q35) { 1400 sb_scope = aml_scope("_SB"); 1401 dev = aml_device("PCI0"); 1402 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1403 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1404 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1405 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1406 aml_append(dev, aml_pci_edsm()); 1407 aml_append(sb_scope, dev); 1408 if (mcfg_valid) { 1409 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1410 } 1411 1412 if (pm->smi_on_cpuhp) { 1413 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1414 dev = aml_device("PCI0.SMI0"); 1415 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1416 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1417 crs = aml_resource_template(); 1418 aml_append(crs, 1419 aml_io( 1420 AML_DECODE16, 1421 pm->fadt.smi_cmd, 1422 pm->fadt.smi_cmd, 1423 1, 1424 2) 1425 ); 1426 aml_append(dev, aml_name_decl("_CRS", crs)); 1427 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1428 aml_int(pm->fadt.smi_cmd), 2)); 1429 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1430 AML_WRITE_AS_ZEROS); 1431 aml_append(field, aml_named_field("SMIC", 8)); 1432 aml_append(field, aml_reserved_field(8)); 1433 aml_append(dev, field); 1434 aml_append(sb_scope, dev); 1435 } 1436 1437 aml_append(dsdt, sb_scope); 1438 1439 if (pm->pcihp_bridge_en) { 1440 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1441 } 1442 build_q35_pci0_int(dsdt); 1443 } 1444 1445 if (misc->has_hpet) { 1446 build_hpet_aml(dsdt); 1447 } 1448 1449 if (vmbus_bridge) { 1450 sb_scope = aml_scope("_SB"); 1451 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1452 aml_append(dsdt, sb_scope); 1453 } 1454 1455 scope = aml_scope("_GPE"); 1456 { 1457 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1458 if (machine->nvdimms_state->is_enabled) { 1459 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1460 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1461 aml_int(0x80))); 1462 aml_append(scope, method); 1463 } 1464 } 1465 aml_append(dsdt, scope); 1466 1467 if (pcmc->legacy_cpu_hotplug) { 1468 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1469 } else { 1470 CPUHotplugFeatures opts = { 1471 .acpi_1_compatible = true, .has_legacy_cphp = true, 1472 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1473 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1474 }; 1475 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, 1476 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", 1477 AML_SYSTEM_IO); 1478 } 1479 1480 if (pcms->memhp_io_base && nr_mem) { 1481 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1482 "\\_GPE._E03", AML_SYSTEM_IO, 1483 pcms->memhp_io_base); 1484 } 1485 1486 crs_range_set_init(&crs_range_set); 1487 bus = PC_MACHINE(machine)->pcibus; 1488 if (bus) { 1489 QLIST_FOREACH(bus, &bus->child, sibling) { 1490 uint8_t bus_num = pci_bus_num(bus); 1491 uint8_t numa_node = pci_bus_numa_node(bus); 1492 uint32_t uid; 1493 1494 /* look only for expander root buses */ 1495 if (!pci_bus_is_root(bus)) { 1496 continue; 1497 } 1498 1499 if (bus_num < root_bus_limit) { 1500 root_bus_limit = bus_num - 1; 1501 } 1502 1503 uid = object_property_get_uint(OBJECT(bus), "acpi_uid", 1504 &error_fatal); 1505 scope = aml_scope("\\_SB"); 1506 1507 if (pci_bus_is_cxl(bus)) { 1508 dev = aml_device("CL%.02X", bus_num); 1509 } else { 1510 dev = aml_device("PC%.02X", bus_num); 1511 } 1512 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1513 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1514 if (pci_bus_is_cxl(bus)) { 1515 struct Aml *aml_pkg = aml_package(2); 1516 1517 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1518 aml_append(aml_pkg, aml_eisaid("PNP0A08")); 1519 aml_append(aml_pkg, aml_eisaid("PNP0A03")); 1520 aml_append(dev, aml_name_decl("_CID", aml_pkg)); 1521 build_cxl_osc_method(dev); 1522 } else if (pci_bus_is_express(bus)) { 1523 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1524 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1525 1526 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1527 aml_append(dev, build_q35_osc_method(true)); 1528 } else { 1529 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1530 } 1531 1532 if (numa_node != NUMA_NODE_UNASSIGNED) { 1533 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1534 } 1535 1536 aml_append(dev, build_prt(false)); 1537 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1538 0, 0, 0, 0); 1539 aml_append(dev, aml_name_decl("_CRS", crs)); 1540 aml_append(scope, dev); 1541 aml_append(dsdt, scope); 1542 1543 /* Handle the ranges for the PXB expanders */ 1544 if (pci_bus_is_cxl(bus)) { 1545 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1546 uint64_t base = mr->addr; 1547 1548 cxl_present = true; 1549 crs_range_insert(crs_range_set.mem_ranges, base, 1550 base + memory_region_size(mr) - 1); 1551 } 1552 } 1553 } 1554 1555 if (cxl_present) { 1556 build_acpi0017(dsdt); 1557 } 1558 1559 /* 1560 * At this point crs_range_set has all the ranges used by pci 1561 * busses *other* than PCI0. These ranges will be excluded from 1562 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1563 * too. 1564 */ 1565 if (mcfg_valid) { 1566 crs_range_insert(crs_range_set.mem_ranges, 1567 mcfg.base, mcfg.base + mcfg.size - 1); 1568 } 1569 1570 scope = aml_scope("\\_SB.PCI0"); 1571 /* build PCI0._CRS */ 1572 crs = aml_resource_template(); 1573 aml_append(crs, 1574 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1575 0x0000, 0x0, root_bus_limit, 1576 0x0000, root_bus_limit + 1)); 1577 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1578 1579 aml_append(crs, 1580 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1581 AML_POS_DECODE, AML_ENTIRE_RANGE, 1582 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1583 1584 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1585 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1586 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1587 aml_append(crs, 1588 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1589 AML_POS_DECODE, AML_ENTIRE_RANGE, 1590 0x0000, entry->base, entry->limit, 1591 0x0000, entry->limit - entry->base + 1)); 1592 } 1593 1594 aml_append(crs, 1595 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1596 AML_CACHEABLE, AML_READ_WRITE, 1597 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1598 1599 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1600 range_lob(pci_hole), 1601 range_upb(pci_hole)); 1602 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1603 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1604 aml_append(crs, 1605 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1606 AML_NON_CACHEABLE, AML_READ_WRITE, 1607 0, entry->base, entry->limit, 1608 0, entry->limit - entry->base + 1)); 1609 } 1610 1611 if (!range_is_empty(pci_hole64)) { 1612 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1613 range_lob(pci_hole64), 1614 range_upb(pci_hole64)); 1615 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1616 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1617 aml_append(crs, 1618 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1619 AML_MAX_FIXED, 1620 AML_CACHEABLE, AML_READ_WRITE, 1621 0, entry->base, entry->limit, 1622 0, entry->limit - entry->base + 1)); 1623 } 1624 } 1625 1626 #ifdef CONFIG_TPM 1627 if (TPM_IS_TIS_ISA(tpm_find())) { 1628 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1629 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1630 } 1631 #endif 1632 aml_append(scope, aml_name_decl("_CRS", crs)); 1633 1634 /* reserve GPE0 block resources */ 1635 dev = aml_device("GPE0"); 1636 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1637 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1638 /* device present, functioning, decoding, not shown in UI */ 1639 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1640 crs = aml_resource_template(); 1641 aml_append(crs, 1642 aml_io( 1643 AML_DECODE16, 1644 pm->fadt.gpe0_blk.address, 1645 pm->fadt.gpe0_blk.address, 1646 1, 1647 pm->fadt.gpe0_blk.bit_width / 8) 1648 ); 1649 aml_append(dev, aml_name_decl("_CRS", crs)); 1650 aml_append(scope, dev); 1651 1652 crs_range_set_free(&crs_range_set); 1653 1654 /* reserve PCIHP resources */ 1655 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1656 dev = aml_device("PHPR"); 1657 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1658 aml_append(dev, 1659 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1660 /* device present, functioning, decoding, not shown in UI */ 1661 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1662 crs = aml_resource_template(); 1663 aml_append(crs, 1664 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1665 pm->pcihp_io_len) 1666 ); 1667 aml_append(dev, aml_name_decl("_CRS", crs)); 1668 aml_append(scope, dev); 1669 } 1670 aml_append(dsdt, scope); 1671 1672 /* create S3_ / S4_ / S5_ packages if necessary */ 1673 scope = aml_scope("\\"); 1674 if (!pm->s3_disabled) { 1675 pkg = aml_package(4); 1676 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1677 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1678 aml_append(pkg, aml_int(0)); /* reserved */ 1679 aml_append(pkg, aml_int(0)); /* reserved */ 1680 aml_append(scope, aml_name_decl("_S3", pkg)); 1681 } 1682 1683 if (!pm->s4_disabled) { 1684 pkg = aml_package(4); 1685 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1686 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1687 aml_append(pkg, aml_int(pm->s4_val)); 1688 aml_append(pkg, aml_int(0)); /* reserved */ 1689 aml_append(pkg, aml_int(0)); /* reserved */ 1690 aml_append(scope, aml_name_decl("_S4", pkg)); 1691 } 1692 1693 pkg = aml_package(4); 1694 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1695 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1696 aml_append(pkg, aml_int(0)); /* reserved */ 1697 aml_append(pkg, aml_int(0)); /* reserved */ 1698 aml_append(scope, aml_name_decl("_S5", pkg)); 1699 aml_append(dsdt, scope); 1700 1701 /* create fw_cfg node, unconditionally */ 1702 { 1703 scope = aml_scope("\\_SB.PCI0"); 1704 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1705 aml_append(dsdt, scope); 1706 } 1707 1708 sb_scope = aml_scope("\\_SB"); 1709 { 1710 Object *pci_host = acpi_get_i386_pci_host(); 1711 1712 if (pci_host) { 1713 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus; 1714 Aml *ascope = aml_scope("PCI0"); 1715 /* Scan all PCI buses. Generate tables to support hotplug. */ 1716 build_append_pci_bus_devices(ascope, pbus); 1717 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) { 1718 build_append_pcihp_slots(ascope, pbus); 1719 } 1720 aml_append(sb_scope, ascope); 1721 } 1722 } 1723 1724 #ifdef CONFIG_TPM 1725 if (TPM_IS_CRB(tpm)) { 1726 dev = aml_device("TPM"); 1727 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1728 aml_append(dev, aml_name_decl("_STR", 1729 aml_string("TPM 2.0 Device"))); 1730 crs = aml_resource_template(); 1731 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1732 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1733 aml_append(dev, aml_name_decl("_CRS", crs)); 1734 1735 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1736 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1737 1738 tpm_build_ppi_acpi(tpm, dev); 1739 1740 aml_append(sb_scope, dev); 1741 } 1742 #endif 1743 1744 if (pcms->sgx_epc.size != 0) { 1745 uint64_t epc_base = pcms->sgx_epc.base; 1746 uint64_t epc_size = pcms->sgx_epc.size; 1747 1748 dev = aml_device("EPC"); 1749 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1750 aml_append(dev, aml_name_decl("_STR", 1751 aml_unicode("Enclave Page Cache 1.0"))); 1752 crs = aml_resource_template(); 1753 aml_append(crs, 1754 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1755 AML_MAX_FIXED, AML_NON_CACHEABLE, 1756 AML_READ_WRITE, 0, epc_base, 1757 epc_base + epc_size - 1, 0, epc_size)); 1758 aml_append(dev, aml_name_decl("_CRS", crs)); 1759 1760 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1761 aml_append(method, aml_return(aml_int(0x0f))); 1762 aml_append(dev, method); 1763 1764 aml_append(sb_scope, dev); 1765 } 1766 aml_append(dsdt, sb_scope); 1767 1768 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1769 bool has_pcnt; 1770 1771 Object *pci_host = acpi_get_i386_pci_host(); 1772 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus; 1773 1774 scope = aml_scope("\\_SB.PCI0"); 1775 has_pcnt = build_append_notfication_callback(scope, b); 1776 if (has_pcnt) { 1777 aml_append(dsdt, scope); 1778 } 1779 1780 scope = aml_scope("_GPE"); 1781 { 1782 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1783 if (has_pcnt) { 1784 aml_append(method, 1785 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1786 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1787 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1788 } 1789 aml_append(scope, method); 1790 } 1791 aml_append(dsdt, scope); 1792 } 1793 1794 /* copy AML table into ACPI tables blob and patch header there */ 1795 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1796 acpi_table_end(linker, &table); 1797 free_aml_allocator(); 1798 } 1799 1800 /* 1801 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1802 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1803 */ 1804 static void 1805 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1806 const char *oem_table_id) 1807 { 1808 AcpiTable table = { .sig = "HPET", .rev = 1, 1809 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1810 1811 acpi_table_begin(&table, table_data); 1812 /* Note timer_block_id value must be kept in sync with value advertised by 1813 * emulated hpet 1814 */ 1815 /* Event Timer Block ID */ 1816 build_append_int_noprefix(table_data, 0x8086a201, 4); 1817 /* BASE_ADDRESS */ 1818 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1819 /* HPET Number */ 1820 build_append_int_noprefix(table_data, 0, 1); 1821 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1822 build_append_int_noprefix(table_data, 0, 2); 1823 /* Page Protection And OEM Attribute */ 1824 build_append_int_noprefix(table_data, 0, 1); 1825 acpi_table_end(linker, &table); 1826 } 1827 1828 #ifdef CONFIG_TPM 1829 /* 1830 * TCPA Description Table 1831 * 1832 * Following Level 00, Rev 00.37 of specs: 1833 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1834 * 7.1.2 ACPI Table Layout 1835 */ 1836 static void 1837 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1838 const char *oem_id, const char *oem_table_id) 1839 { 1840 unsigned log_addr_offset; 1841 AcpiTable table = { .sig = "TCPA", .rev = 2, 1842 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1843 1844 acpi_table_begin(&table, table_data); 1845 /* Platform Class */ 1846 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1847 /* Log Area Minimum Length (LAML) */ 1848 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1849 /* Log Area Start Address (LASA) */ 1850 log_addr_offset = table_data->len; 1851 build_append_int_noprefix(table_data, 0, 8); 1852 1853 /* allocate/reserve space for TPM log area */ 1854 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1855 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1856 false /* high memory */); 1857 /* log area start address to be filled by Guest linker */ 1858 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1859 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1860 1861 acpi_table_end(linker, &table); 1862 } 1863 #endif 1864 1865 #define HOLE_640K_START (640 * KiB) 1866 #define HOLE_640K_END (1 * MiB) 1867 1868 /* 1869 * ACPI spec, Revision 3.0 1870 * 5.2.15 System Resource Affinity Table (SRAT) 1871 */ 1872 static void 1873 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1874 { 1875 int i; 1876 int numa_mem_start, slots; 1877 uint64_t mem_len, mem_base, next_base; 1878 MachineClass *mc = MACHINE_GET_CLASS(machine); 1879 X86MachineState *x86ms = X86_MACHINE(machine); 1880 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1881 int nb_numa_nodes = machine->numa_state->num_nodes; 1882 NodeInfo *numa_info = machine->numa_state->nodes; 1883 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1884 .oem_table_id = x86ms->oem_table_id }; 1885 1886 acpi_table_begin(&table, table_data); 1887 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1888 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1889 1890 for (i = 0; i < apic_ids->len; i++) { 1891 int node_id = apic_ids->cpus[i].props.node_id; 1892 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1893 1894 if (apic_id < 255) { 1895 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1896 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1897 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1898 /* Proximity Domain [7:0] */ 1899 build_append_int_noprefix(table_data, node_id, 1); 1900 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1901 /* Flags, Table 5-36 */ 1902 build_append_int_noprefix(table_data, 1, 4); 1903 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1904 /* Proximity Domain [31:8] */ 1905 build_append_int_noprefix(table_data, 0, 3); 1906 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1907 } else { 1908 /* 1909 * ACPI spec, Revision 4.0 1910 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1911 */ 1912 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1913 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1914 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1915 /* Proximity Domain */ 1916 build_append_int_noprefix(table_data, node_id, 4); 1917 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1918 /* Flags, Table 5-39 */ 1919 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 1920 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 1921 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1922 } 1923 } 1924 1925 /* the memory map is a bit tricky, it contains at least one hole 1926 * from 640k-1M and possibly another one from 3.5G-4G. 1927 */ 1928 next_base = 0; 1929 numa_mem_start = table_data->len; 1930 1931 for (i = 1; i < nb_numa_nodes + 1; ++i) { 1932 mem_base = next_base; 1933 mem_len = numa_info[i - 1].node_mem; 1934 next_base = mem_base + mem_len; 1935 1936 /* Cut out the 640K hole */ 1937 if (mem_base <= HOLE_640K_START && 1938 next_base > HOLE_640K_START) { 1939 mem_len -= next_base - HOLE_640K_START; 1940 if (mem_len > 0) { 1941 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1942 MEM_AFFINITY_ENABLED); 1943 } 1944 1945 /* Check for the rare case: 640K < RAM < 1M */ 1946 if (next_base <= HOLE_640K_END) { 1947 next_base = HOLE_640K_END; 1948 continue; 1949 } 1950 mem_base = HOLE_640K_END; 1951 mem_len = next_base - HOLE_640K_END; 1952 } 1953 1954 /* Cut out the ACPI_PCI hole */ 1955 if (mem_base <= x86ms->below_4g_mem_size && 1956 next_base > x86ms->below_4g_mem_size) { 1957 mem_len -= next_base - x86ms->below_4g_mem_size; 1958 if (mem_len > 0) { 1959 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1960 MEM_AFFINITY_ENABLED); 1961 } 1962 mem_base = x86ms->above_4g_mem_start; 1963 mem_len = next_base - x86ms->below_4g_mem_size; 1964 next_base = mem_base + mem_len; 1965 } 1966 1967 if (mem_len > 0) { 1968 build_srat_memory(table_data, mem_base, mem_len, i - 1, 1969 MEM_AFFINITY_ENABLED); 1970 } 1971 } 1972 1973 if (machine->nvdimms_state->is_enabled) { 1974 nvdimm_build_srat(table_data); 1975 } 1976 1977 sgx_epc_build_srat(table_data); 1978 1979 /* 1980 * TODO: this part is not in ACPI spec and current linux kernel boots fine 1981 * without these entries. But I recall there were issues the last time I 1982 * tried to remove it with some ancient guest OS, however I can't remember 1983 * what that was so keep this around for now 1984 */ 1985 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 1986 for (; slots < nb_numa_nodes + 2; slots++) { 1987 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 1988 } 1989 1990 build_srat_generic_affinity_structures(table_data); 1991 1992 /* 1993 * Entry is required for Windows to enable memory hotplug in OS 1994 * and for Linux to enable SWIOTLB when booted with less than 1995 * 4G of RAM. Windows works better if the entry sets proximity 1996 * to the highest NUMA node in the machine. 1997 * Memory devices may override proximity set by this entry, 1998 * providing _PXM method if necessary. 1999 */ 2000 if (machine->device_memory) { 2001 build_srat_memory(table_data, machine->device_memory->base, 2002 memory_region_size(&machine->device_memory->mr), 2003 nb_numa_nodes - 1, 2004 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2005 } 2006 2007 acpi_table_end(linker, &table); 2008 } 2009 2010 /* 2011 * Insert DMAR scope for PCI bridges and endpoint devices 2012 */ 2013 static void 2014 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2015 { 2016 const size_t device_scope_size = 6 /* device scope structure */ + 2017 2 /* 1 path entry */; 2018 GArray *scope_blob = opaque; 2019 2020 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2021 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2022 build_append_int_noprefix(scope_blob, 0x02, 1); 2023 } else { 2024 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2025 build_append_int_noprefix(scope_blob, 0x01, 1); 2026 } 2027 2028 /* length */ 2029 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2030 /* reserved */ 2031 build_append_int_noprefix(scope_blob, 0, 2); 2032 /* enumeration_id */ 2033 build_append_int_noprefix(scope_blob, 0, 1); 2034 /* bus */ 2035 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2036 /* device */ 2037 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2038 /* function */ 2039 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2040 } 2041 2042 /* For a given PCI host bridge, walk and insert DMAR scope */ 2043 static int 2044 dmar_host_bridges(Object *obj, void *opaque) 2045 { 2046 GArray *scope_blob = opaque; 2047 2048 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2049 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2050 2051 if (bus && !pci_bus_bypass_iommu(bus)) { 2052 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2053 } 2054 } 2055 2056 return 0; 2057 } 2058 2059 /* 2060 * Intel ® Virtualization Technology for Directed I/O 2061 * Architecture Specification. Revision 3.3 2062 * 8.1 DMA Remapping Reporting Structure 2063 */ 2064 static void 2065 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2066 const char *oem_table_id) 2067 { 2068 uint8_t dmar_flags = 0; 2069 uint8_t rsvd10[10] = {}; 2070 /* Root complex IOAPIC uses one path only */ 2071 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2072 2 /* 1 path entry */; 2073 X86IOMMUState *iommu = x86_iommu_get_default(); 2074 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2075 GArray *scope_blob = g_array_new(false, true, 1); 2076 2077 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2078 .oem_table_id = oem_table_id }; 2079 2080 /* 2081 * A PCI bus walk, for each PCI host bridge. 2082 * Insert scope for each PCI bridge and endpoint device which 2083 * is attached to a bus with iommu enabled. 2084 */ 2085 object_child_foreach_recursive(object_get_root(), 2086 dmar_host_bridges, scope_blob); 2087 2088 assert(iommu); 2089 if (x86_iommu_ir_supported(iommu)) { 2090 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2091 } 2092 2093 acpi_table_begin(&table, table_data); 2094 /* Host Address Width */ 2095 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2096 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2097 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2098 2099 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2100 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2101 /* Length */ 2102 build_append_int_noprefix(table_data, 2103 16 + ioapic_scope_size + scope_blob->len, 2); 2104 /* Flags */ 2105 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2106 1); 2107 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2108 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2109 /* Register Base Address */ 2110 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2111 2112 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2113 * 8.3.1 (version Oct. 2014 or later). */ 2114 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2115 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2116 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2117 /* Enumeration ID */ 2118 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2119 /* Start Bus Number */ 2120 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2121 /* Path, {Device, Function} pair */ 2122 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2123 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2124 2125 /* Add scope found above */ 2126 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2127 g_array_free(scope_blob, true); 2128 2129 if (iommu->dt_supported) { 2130 /* 8.5 Root Port ATS Capability Reporting Structure */ 2131 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2132 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2133 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2134 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2135 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2136 } 2137 2138 acpi_table_end(linker, &table); 2139 } 2140 2141 /* 2142 * Windows ACPI Emulated Devices Table 2143 * (Version 1.0 - April 6, 2009) 2144 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2145 * 2146 * Helpful to speedup Windows guests and ignored by others. 2147 */ 2148 static void 2149 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2150 const char *oem_table_id) 2151 { 2152 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2153 .oem_table_id = oem_table_id }; 2154 2155 acpi_table_begin(&table, table_data); 2156 /* 2157 * Set "ACPI PM timer good" flag. 2158 * 2159 * Tells Windows guests that our ACPI PM timer is reliable in the 2160 * sense that guest can read it only once to obtain a reliable value. 2161 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2162 */ 2163 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2164 acpi_table_end(linker, &table); 2165 } 2166 2167 /* 2168 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2169 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2170 */ 2171 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2172 2173 /* 2174 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2175 * necessary for the PCI topology. 2176 */ 2177 static void 2178 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2179 { 2180 GArray *table_data = opaque; 2181 uint32_t entry; 2182 2183 /* "Select" IVHD entry, type 0x2 */ 2184 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2185 build_append_int_noprefix(table_data, entry, 4); 2186 2187 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2188 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2189 uint8_t sec = pci_bus_num(sec_bus); 2190 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2191 2192 if (pci_bus_is_express(sec_bus)) { 2193 /* 2194 * Walk the bus if there are subordinates, otherwise use a range 2195 * to cover an entire leaf bus. We could potentially also use a 2196 * range for traversed buses, but we'd need to take care not to 2197 * create both Select and Range entries covering the same device. 2198 * This is easier and potentially more compact. 2199 * 2200 * An example bare metal system seems to use Select entries for 2201 * root ports without a slot (ie. built-ins) and Range entries 2202 * when there is a slot. The same system also only hard-codes 2203 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2204 * making no effort to support nested bridges. We attempt to 2205 * be more thorough here. 2206 */ 2207 if (sec == sub) { /* leaf bus */ 2208 /* "Start of Range" IVHD entry, type 0x3 */ 2209 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2210 build_append_int_noprefix(table_data, entry, 4); 2211 /* "End of Range" IVHD entry, type 0x4 */ 2212 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2213 build_append_int_noprefix(table_data, entry, 4); 2214 } else { 2215 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2216 } 2217 } else { 2218 /* 2219 * If the secondary bus is conventional, then we need to create an 2220 * Alias range for everything downstream. The range covers the 2221 * first devfn on the secondary bus to the last devfn on the 2222 * subordinate bus. The alias target depends on legacy versus 2223 * express bridges, just as in pci_device_iommu_address_space(). 2224 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2225 */ 2226 uint16_t dev_id_a, dev_id_b; 2227 2228 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2229 2230 if (pci_is_express(dev) && 2231 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2232 dev_id_b = dev_id_a; 2233 } else { 2234 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2235 } 2236 2237 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2238 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2239 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2240 2241 /* "End of Range" IVHD entry, type 0x4 */ 2242 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2243 build_append_int_noprefix(table_data, entry, 4); 2244 } 2245 } 2246 } 2247 2248 /* For all PCI host bridges, walk and insert IVHD entries */ 2249 static int 2250 ivrs_host_bridges(Object *obj, void *opaque) 2251 { 2252 GArray *ivhd_blob = opaque; 2253 2254 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2255 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2256 2257 if (bus && !pci_bus_bypass_iommu(bus)) { 2258 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2259 } 2260 } 2261 2262 return 0; 2263 } 2264 2265 static void 2266 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2267 const char *oem_table_id) 2268 { 2269 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2270 GArray *ivhd_blob = g_array_new(false, true, 1); 2271 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2272 .oem_table_id = oem_table_id }; 2273 uint64_t feature_report; 2274 2275 acpi_table_begin(&table, table_data); 2276 /* IVinfo - IO virtualization information common to all 2277 * IOMMU units in a system 2278 */ 2279 build_append_int_noprefix(table_data, 2280 (1UL << 0) | /* EFRSup */ 2281 (40UL << 8), /* PASize */ 2282 4); 2283 /* reserved */ 2284 build_append_int_noprefix(table_data, 0, 8); 2285 2286 /* 2287 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2288 * complete set of IVHD entries. Do this into a separate blob so that we 2289 * can calculate the total IVRS table length here and then append the new 2290 * blob further below. Fall back to an entry covering all devices, which 2291 * is sufficient when no aliases are present. 2292 */ 2293 object_child_foreach_recursive(object_get_root(), 2294 ivrs_host_bridges, ivhd_blob); 2295 2296 if (!ivhd_blob->len) { 2297 /* 2298 * Type 1 device entry reporting all devices 2299 * These are 4-byte device entries currently reporting the range of 2300 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2301 */ 2302 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2303 } 2304 2305 /* 2306 * When interrupt remapping is supported, we add a special IVHD device 2307 * for type IO-APIC 2308 * Refer to spec - Table 95: IVHD device entry type codes 2309 * 2310 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2311 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2312 */ 2313 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2314 build_append_int_noprefix(ivhd_blob, 2315 (0x1ull << 56) | /* type IOAPIC */ 2316 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2317 0x48, /* special device */ 2318 8); 2319 } 2320 2321 /* IVHD definition - type 10h */ 2322 build_append_int_noprefix(table_data, 0x10, 1); 2323 /* virtualization flags */ 2324 build_append_int_noprefix(table_data, 2325 (1UL << 0) | /* HtTunEn */ 2326 (1UL << 4) | /* iotblSup */ 2327 (1UL << 6) | /* PrefSup */ 2328 (1UL << 7), /* PPRSup */ 2329 1); 2330 2331 /* IVHD length */ 2332 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); 2333 /* DeviceID */ 2334 build_append_int_noprefix(table_data, 2335 object_property_get_int(OBJECT(&s->pci), "addr", 2336 &error_abort), 2); 2337 /* Capability offset */ 2338 build_append_int_noprefix(table_data, s->pci.capab_offset, 2); 2339 /* IOMMU base address */ 2340 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); 2341 /* PCI Segment Group */ 2342 build_append_int_noprefix(table_data, 0, 2); 2343 /* IOMMU info */ 2344 build_append_int_noprefix(table_data, 0, 2); 2345 /* IOMMU Feature Reporting */ 2346 feature_report = (48UL << 30) | /* HATS */ 2347 (48UL << 28) | /* GATS */ 2348 (1UL << 2) | /* GTSup */ 2349 (1UL << 6); /* GASup */ 2350 if (s->xtsup) { 2351 feature_report |= (1UL << 0); /* XTSup */ 2352 } 2353 build_append_int_noprefix(table_data, feature_report, 4); 2354 2355 /* IVHD entries as found above */ 2356 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2357 2358 /* IVHD definition - type 11h */ 2359 build_append_int_noprefix(table_data, 0x11, 1); 2360 /* virtualization flags */ 2361 build_append_int_noprefix(table_data, 2362 (1UL << 0) | /* HtTunEn */ 2363 (1UL << 4), /* iotblSup */ 2364 1); 2365 2366 /* IVHD length */ 2367 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); 2368 /* DeviceID */ 2369 build_append_int_noprefix(table_data, 2370 object_property_get_int(OBJECT(&s->pci), "addr", 2371 &error_abort), 2); 2372 /* Capability offset */ 2373 build_append_int_noprefix(table_data, s->pci.capab_offset, 2); 2374 /* IOMMU base address */ 2375 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); 2376 /* PCI Segment Group */ 2377 build_append_int_noprefix(table_data, 0, 2); 2378 /* IOMMU info */ 2379 build_append_int_noprefix(table_data, 0, 2); 2380 /* IOMMU Attributes */ 2381 build_append_int_noprefix(table_data, 0, 4); 2382 /* EFR Register Image */ 2383 build_append_int_noprefix(table_data, 2384 amdvi_extended_feature_register(s), 2385 8); 2386 /* EFR Register Image 2 */ 2387 build_append_int_noprefix(table_data, 0, 8); 2388 2389 /* IVHD entries as found above */ 2390 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2391 2392 g_array_free(ivhd_blob, TRUE); 2393 acpi_table_end(linker, &table); 2394 } 2395 2396 typedef 2397 struct AcpiBuildState { 2398 /* Copy of table in RAM (for patching). */ 2399 MemoryRegion *table_mr; 2400 /* Is table patched? */ 2401 uint8_t patched; 2402 MemoryRegion *rsdp_mr; 2403 MemoryRegion *linker_mr; 2404 } AcpiBuildState; 2405 2406 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2407 { 2408 Object *pci_host; 2409 QObject *o; 2410 2411 pci_host = acpi_get_i386_pci_host(); 2412 if (!pci_host) { 2413 return false; 2414 } 2415 2416 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2417 if (!o) { 2418 return false; 2419 } 2420 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2421 qobject_unref(o); 2422 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2423 return false; 2424 } 2425 2426 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2427 assert(o); 2428 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2429 qobject_unref(o); 2430 return true; 2431 } 2432 2433 static 2434 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2435 { 2436 PCMachineState *pcms = PC_MACHINE(machine); 2437 X86MachineState *x86ms = X86_MACHINE(machine); 2438 DeviceState *iommu = pcms->iommu; 2439 GArray *table_offsets; 2440 unsigned facs, dsdt, rsdt; 2441 AcpiPmInfo pm; 2442 AcpiMiscInfo misc; 2443 AcpiMcfgInfo mcfg; 2444 Range pci_hole = {}, pci_hole64 = {}; 2445 uint8_t *u; 2446 GArray *tables_blob = tables->table_data; 2447 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2448 Object *vmgenid_dev; 2449 char *oem_id; 2450 char *oem_table_id; 2451 2452 acpi_get_pm_info(machine, &pm); 2453 acpi_get_misc_info(&misc); 2454 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2455 acpi_get_slic_oem(&slic_oem); 2456 2457 if (slic_oem.id) { 2458 oem_id = slic_oem.id; 2459 } else { 2460 oem_id = x86ms->oem_id; 2461 } 2462 2463 if (slic_oem.table_id) { 2464 oem_table_id = slic_oem.table_id; 2465 } else { 2466 oem_table_id = x86ms->oem_table_id; 2467 } 2468 2469 table_offsets = g_array_new(false, true /* clear */, 2470 sizeof(uint32_t)); 2471 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2472 2473 bios_linker_loader_alloc(tables->linker, 2474 ACPI_BUILD_TABLE_FILE, tables_blob, 2475 64 /* Ensure FACS is aligned */, 2476 false /* high memory */); 2477 2478 /* 2479 * FACS is pointed to by FADT. 2480 * We place it first since it's the only table that has alignment 2481 * requirements. 2482 */ 2483 facs = tables_blob->len; 2484 build_facs(tables_blob); 2485 2486 /* DSDT is pointed to by FADT */ 2487 dsdt = tables_blob->len; 2488 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2489 &pci_hole, &pci_hole64, machine); 2490 2491 /* ACPI tables pointed to by RSDT */ 2492 acpi_add_table(table_offsets, tables_blob); 2493 pm.fadt.facs_tbl_offset = &facs; 2494 pm.fadt.dsdt_tbl_offset = &dsdt; 2495 pm.fadt.xdsdt_tbl_offset = &dsdt; 2496 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2497 2498 acpi_add_table(table_offsets, tables_blob); 2499 acpi_build_madt(tables_blob, tables->linker, x86ms, 2500 x86ms->oem_id, x86ms->oem_table_id); 2501 2502 #ifdef CONFIG_ACPI_ERST 2503 { 2504 Object *erst_dev; 2505 erst_dev = find_erst_dev(); 2506 if (erst_dev) { 2507 acpi_add_table(table_offsets, tables_blob); 2508 build_erst(tables_blob, tables->linker, erst_dev, 2509 x86ms->oem_id, x86ms->oem_table_id); 2510 } 2511 } 2512 #endif 2513 2514 vmgenid_dev = find_vmgenid_dev(); 2515 if (vmgenid_dev) { 2516 acpi_add_table(table_offsets, tables_blob); 2517 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2518 tables->vmgenid, tables->linker, x86ms->oem_id); 2519 } 2520 2521 if (misc.has_hpet) { 2522 acpi_add_table(table_offsets, tables_blob); 2523 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2524 x86ms->oem_table_id); 2525 } 2526 #ifdef CONFIG_TPM 2527 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2528 if (misc.tpm_version == TPM_VERSION_1_2) { 2529 acpi_add_table(table_offsets, tables_blob); 2530 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2531 x86ms->oem_id, x86ms->oem_table_id); 2532 } else { /* TPM_VERSION_2_0 */ 2533 acpi_add_table(table_offsets, tables_blob); 2534 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2535 x86ms->oem_id, x86ms->oem_table_id); 2536 } 2537 } 2538 #endif 2539 if (machine->numa_state->num_nodes) { 2540 acpi_add_table(table_offsets, tables_blob); 2541 build_srat(tables_blob, tables->linker, machine); 2542 if (machine->numa_state->have_numa_distance) { 2543 acpi_add_table(table_offsets, tables_blob); 2544 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2545 x86ms->oem_table_id); 2546 } 2547 if (machine->numa_state->hmat_enabled) { 2548 acpi_add_table(table_offsets, tables_blob); 2549 build_hmat(tables_blob, tables->linker, machine->numa_state, 2550 x86ms->oem_id, x86ms->oem_table_id); 2551 } 2552 } 2553 if (acpi_get_mcfg(&mcfg)) { 2554 acpi_add_table(table_offsets, tables_blob); 2555 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2556 x86ms->oem_table_id); 2557 } 2558 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2559 acpi_add_table(table_offsets, tables_blob); 2560 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2561 x86ms->oem_table_id); 2562 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2563 acpi_add_table(table_offsets, tables_blob); 2564 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2565 x86ms->oem_table_id); 2566 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2567 PCIDevice *pdev = PCI_DEVICE(iommu); 2568 2569 acpi_add_table(table_offsets, tables_blob); 2570 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2571 x86ms->oem_id, x86ms->oem_table_id); 2572 } 2573 if (machine->nvdimms_state->is_enabled) { 2574 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2575 machine->nvdimms_state, machine->ram_slots, 2576 x86ms->oem_id, x86ms->oem_table_id); 2577 } 2578 if (pcms->cxl_devices_state.is_enabled) { 2579 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2580 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2581 } 2582 2583 acpi_add_table(table_offsets, tables_blob); 2584 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2585 2586 /* Add tables supplied by user (if any) */ 2587 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2588 unsigned len = acpi_table_len(u); 2589 2590 acpi_add_table(table_offsets, tables_blob); 2591 g_array_append_vals(tables_blob, u, len); 2592 } 2593 2594 /* RSDT is pointed to by RSDP */ 2595 rsdt = tables_blob->len; 2596 build_rsdt(tables_blob, tables->linker, table_offsets, 2597 oem_id, oem_table_id); 2598 2599 /* RSDP is in FSEG memory, so allocate it separately */ 2600 { 2601 AcpiRsdpData rsdp_data = { 2602 .revision = 0, 2603 .oem_id = x86ms->oem_id, 2604 .xsdt_tbl_offset = NULL, 2605 .rsdt_tbl_offset = &rsdt, 2606 }; 2607 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2608 } 2609 2610 /* We'll expose it all to Guest so we want to reduce 2611 * chance of size changes. 2612 * 2613 * We used to align the tables to 4k, but of course this would 2614 * too simple to be enough. 4k turned out to be too small an 2615 * alignment very soon, and in fact it is almost impossible to 2616 * keep the table size stable for all (max_cpus, max_memory_slots) 2617 * combinations. 2618 */ 2619 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2620 2621 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2622 2623 /* Cleanup memory that's no longer used. */ 2624 g_array_free(table_offsets, true); 2625 g_free(slic_oem.id); 2626 g_free(slic_oem.table_id); 2627 } 2628 2629 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2630 { 2631 uint32_t size = acpi_data_len(data); 2632 2633 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2634 memory_region_ram_resize(mr, size, &error_abort); 2635 2636 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2637 memory_region_set_dirty(mr, 0, size); 2638 } 2639 2640 static void acpi_build_update(void *build_opaque) 2641 { 2642 AcpiBuildState *build_state = build_opaque; 2643 AcpiBuildTables tables; 2644 2645 /* No state to update or already patched? Nothing to do. */ 2646 if (!build_state || build_state->patched) { 2647 return; 2648 } 2649 build_state->patched = 1; 2650 2651 acpi_build_tables_init(&tables); 2652 2653 acpi_build(&tables, MACHINE(qdev_get_machine())); 2654 2655 acpi_ram_update(build_state->table_mr, tables.table_data); 2656 2657 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2658 2659 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2660 acpi_build_tables_cleanup(&tables, true); 2661 } 2662 2663 static void acpi_build_reset(void *build_opaque) 2664 { 2665 AcpiBuildState *build_state = build_opaque; 2666 build_state->patched = 0; 2667 } 2668 2669 static const VMStateDescription vmstate_acpi_build = { 2670 .name = "acpi_build", 2671 .version_id = 1, 2672 .minimum_version_id = 1, 2673 .fields = (const VMStateField[]) { 2674 VMSTATE_UINT8(patched, AcpiBuildState), 2675 VMSTATE_END_OF_LIST() 2676 }, 2677 }; 2678 2679 void acpi_setup(void) 2680 { 2681 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2682 X86MachineState *x86ms = X86_MACHINE(pcms); 2683 AcpiBuildTables tables; 2684 AcpiBuildState *build_state; 2685 Object *vmgenid_dev; 2686 #ifdef CONFIG_TPM 2687 TPMIf *tpm; 2688 static FwCfgTPMConfig tpm_config; 2689 #endif 2690 2691 if (!x86ms->fw_cfg) { 2692 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2693 return; 2694 } 2695 2696 if (!pcms->acpi_build_enabled) { 2697 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2698 return; 2699 } 2700 2701 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2702 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2703 return; 2704 } 2705 2706 build_state = g_malloc0(sizeof *build_state); 2707 2708 acpi_build_tables_init(&tables); 2709 acpi_build(&tables, MACHINE(pcms)); 2710 2711 /* Now expose it all to Guest */ 2712 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2713 build_state, tables.table_data, 2714 ACPI_BUILD_TABLE_FILE); 2715 assert(build_state->table_mr != NULL); 2716 2717 build_state->linker_mr = 2718 acpi_add_rom_blob(acpi_build_update, build_state, 2719 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2720 2721 #ifdef CONFIG_TPM 2722 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2723 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2724 2725 tpm = tpm_find(); 2726 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2727 tpm_config = (FwCfgTPMConfig) { 2728 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2729 .tpm_version = tpm_get_version(tpm), 2730 .tpmppi_version = TPM_PPI_VERSION_1_30 2731 }; 2732 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2733 &tpm_config, sizeof tpm_config); 2734 } 2735 #endif 2736 2737 vmgenid_dev = find_vmgenid_dev(); 2738 if (vmgenid_dev) { 2739 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2740 tables.vmgenid); 2741 } 2742 2743 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2744 build_state, tables.rsdp, 2745 ACPI_BUILD_RSDP_FILE); 2746 2747 qemu_register_reset(acpi_build_reset, build_state); 2748 acpi_build_reset(build_state); 2749 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2750 2751 /* Cleanup tables but don't free the memory: we track it 2752 * in build_state. 2753 */ 2754 acpi_build_tables_cleanup(&tables, false); 2755 } 2756