xref: /openbmc/qemu/hw/i386/acpi-build.c (revision 1580b897)
1 /* Support for generating ACPI tables and passing them to Guests
2  *
3  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
4  * Copyright (C) 2006 Fabrice Bellard
5  * Copyright (C) 2013 Red Hat Inc
6  *
7  * Author: Michael S. Tsirkin <mst@redhat.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13 
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18 
19  * You should have received a copy of the GNU General Public License along
20  * with this program; if not, see <http://www.gnu.org/licenses/>.
21  */
22 
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/core/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "sysemu/tpm_backend.h"
47 #include "hw/rtc/mc146818rtc_regs.h"
48 #include "migration/vmstate.h"
49 #include "hw/mem/memory-device.h"
50 #include "hw/mem/nvdimm.h"
51 #include "sysemu/numa.h"
52 #include "sysemu/reset.h"
53 #include "hw/hyperv/vmbus-bridge.h"
54 
55 /* Supported chipsets: */
56 #include "hw/southbridge/piix.h"
57 #include "hw/acpi/pcihp.h"
58 #include "hw/i386/fw_cfg.h"
59 #include "hw/i386/ich9.h"
60 #include "hw/pci/pci_bus.h"
61 #include "hw/pci-host/q35.h"
62 #include "hw/i386/x86-iommu.h"
63 
64 #include "hw/acpi/aml-build.h"
65 #include "hw/acpi/utils.h"
66 #include "hw/acpi/pci.h"
67 
68 #include "qom/qom-qobject.h"
69 #include "hw/i386/amd_iommu.h"
70 #include "hw/i386/intel_iommu.h"
71 
72 #include "hw/acpi/ipmi.h"
73 #include "hw/acpi/hmat.h"
74 
75 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
76  * -M pc-i440fx-2.0.  Even if the actual amount of AML generated grows
77  * a little bit, there should be plenty of free space since the DSDT
78  * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
79  */
80 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE    97
81 #define ACPI_BUILD_ALIGN_SIZE             0x1000
82 
83 #define ACPI_BUILD_TABLE_SIZE             0x20000
84 
85 /* #define DEBUG_ACPI_BUILD */
86 #ifdef DEBUG_ACPI_BUILD
87 #define ACPI_BUILD_DPRINTF(fmt, ...)        \
88     do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
89 #else
90 #define ACPI_BUILD_DPRINTF(fmt, ...)
91 #endif
92 
93 typedef struct AcpiPmInfo {
94     bool s3_disabled;
95     bool s4_disabled;
96     bool pcihp_bridge_en;
97     bool smi_on_cpuhp;
98     bool smi_on_cpu_unplug;
99     bool pcihp_root_en;
100     uint8_t s4_val;
101     AcpiFadtData fadt;
102     uint16_t cpu_hp_io_base;
103     uint16_t pcihp_io_base;
104     uint16_t pcihp_io_len;
105 } AcpiPmInfo;
106 
107 typedef struct AcpiMiscInfo {
108     bool is_piix4;
109     bool has_hpet;
110 #ifdef CONFIG_TPM
111     TPMVersion tpm_version;
112 #endif
113     const unsigned char *dsdt_code;
114     unsigned dsdt_size;
115     uint16_t pvpanic_port;
116     uint16_t applesmc_io_base;
117 } AcpiMiscInfo;
118 
119 typedef struct AcpiBuildPciBusHotplugState {
120     GArray *device_table;
121     GArray *notify_table;
122     struct AcpiBuildPciBusHotplugState *parent;
123     bool pcihp_bridge_en;
124 } AcpiBuildPciBusHotplugState;
125 
126 typedef struct FwCfgTPMConfig {
127     uint32_t tpmppi_address;
128     uint8_t tpm_version;
129     uint8_t tpmppi_version;
130 } QEMU_PACKED FwCfgTPMConfig;
131 
132 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
133 
134 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
135     .space_id = AML_AS_SYSTEM_IO,
136     .address = NVDIMM_ACPI_IO_BASE,
137     .bit_width = NVDIMM_ACPI_IO_LEN << 3
138 };
139 
140 static void init_common_fadt_data(MachineState *ms, Object *o,
141                                   AcpiFadtData *data)
142 {
143     X86MachineState *x86ms = X86_MACHINE(ms);
144     /*
145      * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
146      * behavior for compatibility irrelevant to smm_enabled, which doesn't
147      * comforms to ACPI spec.
148      */
149     bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
150         true : x86_machine_is_smm_enabled(x86ms);
151     uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
152     AmlAddressSpace as = AML_AS_SYSTEM_IO;
153     AcpiFadtData fadt = {
154         .rev = 3,
155         .flags =
156             (1 << ACPI_FADT_F_WBINVD) |
157             (1 << ACPI_FADT_F_PROC_C1) |
158             (1 << ACPI_FADT_F_SLP_BUTTON) |
159             (1 << ACPI_FADT_F_RTC_S4) |
160             (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
161             /* APIC destination mode ("Flat Logical") has an upper limit of 8
162              * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
163              * used
164              */
165             ((ms->smp.max_cpus > 8) ?
166                         (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
167         .int_model = 1 /* Multiple APIC */,
168         .rtc_century = RTC_CENTURY,
169         .plvl2_lat = 0xfff /* C2 state not supported */,
170         .plvl3_lat = 0xfff /* C3 state not supported */,
171         .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
172         .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
173         .acpi_enable_cmd =
174             smm_enabled ?
175             object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
176             0,
177         .acpi_disable_cmd =
178             smm_enabled ?
179             object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
180             0,
181         .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
182         .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
183                       .address = io + 0x04 },
184         .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
185         .gpe0_blk = { .space_id = as, .bit_width =
186             object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
187             .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
188         },
189     };
190     *data = fadt;
191 }
192 
193 static Object *object_resolve_type_unambiguous(const char *typename)
194 {
195     bool ambig;
196     Object *o = object_resolve_path_type("", typename, &ambig);
197 
198     if (ambig || !o) {
199         return NULL;
200     }
201     return o;
202 }
203 
204 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
205 {
206     Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
207     Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
208     Object *obj = piix ? piix : lpc;
209     QObject *o;
210     pm->cpu_hp_io_base = 0;
211     pm->pcihp_io_base = 0;
212     pm->pcihp_io_len = 0;
213     pm->smi_on_cpuhp = false;
214     pm->smi_on_cpu_unplug = false;
215 
216     assert(obj);
217     init_common_fadt_data(machine, obj, &pm->fadt);
218     if (piix) {
219         /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
220         pm->fadt.rev = 1;
221         pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
222     }
223     if (lpc) {
224         uint64_t smi_features = object_property_get_uint(lpc,
225             ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
226         struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
227             .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
228         pm->fadt.reset_reg = r;
229         pm->fadt.reset_val = 0xf;
230         pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
231         pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
232         pm->smi_on_cpuhp =
233             !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
234         pm->smi_on_cpu_unplug =
235             !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
236     }
237     pm->pcihp_io_base =
238         object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
239     pm->pcihp_io_len =
240         object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
241 
242     /* The above need not be conditional on machine type because the reset port
243      * happens to be the same on PIIX (pc) and ICH9 (q35). */
244     QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
245 
246     /* Fill in optional s3/s4 related properties */
247     o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
248     if (o) {
249         pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
250     } else {
251         pm->s3_disabled = false;
252     }
253     qobject_unref(o);
254     o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
255     if (o) {
256         pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
257     } else {
258         pm->s4_disabled = false;
259     }
260     qobject_unref(o);
261     o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
262     if (o) {
263         pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
264     } else {
265         pm->s4_val = false;
266     }
267     qobject_unref(o);
268 
269     pm->pcihp_bridge_en =
270         object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
271                                  NULL);
272     pm->pcihp_root_en =
273         object_property_get_bool(obj, "acpi-root-pci-hotplug",
274                                  NULL);
275 }
276 
277 static void acpi_get_misc_info(AcpiMiscInfo *info)
278 {
279     Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
280     Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
281     assert(!!piix != !!lpc);
282 
283     if (piix) {
284         info->is_piix4 = true;
285     }
286     if (lpc) {
287         info->is_piix4 = false;
288     }
289 
290     info->has_hpet = hpet_find();
291 #ifdef CONFIG_TPM
292     info->tpm_version = tpm_get_version(tpm_find());
293 #endif
294     info->pvpanic_port = pvpanic_port();
295     info->applesmc_io_base = applesmc_port();
296 }
297 
298 /*
299  * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
300  * On i386 arch we only have two pci hosts, so we can look only for them.
301  */
302 Object *acpi_get_i386_pci_host(void)
303 {
304     PCIHostState *host;
305 
306     host = OBJECT_CHECK(PCIHostState,
307                         object_resolve_path("/machine/i440fx", NULL),
308                         TYPE_PCI_HOST_BRIDGE);
309     if (!host) {
310         host = OBJECT_CHECK(PCIHostState,
311                             object_resolve_path("/machine/q35", NULL),
312                             TYPE_PCI_HOST_BRIDGE);
313     }
314 
315     return OBJECT(host);
316 }
317 
318 static void acpi_get_pci_holes(Range *hole, Range *hole64)
319 {
320     Object *pci_host;
321 
322     pci_host = acpi_get_i386_pci_host();
323 
324     if (!pci_host) {
325         return;
326     }
327 
328     range_set_bounds1(hole,
329                       object_property_get_uint(pci_host,
330                                                PCI_HOST_PROP_PCI_HOLE_START,
331                                                NULL),
332                       object_property_get_uint(pci_host,
333                                                PCI_HOST_PROP_PCI_HOLE_END,
334                                                NULL));
335     range_set_bounds1(hole64,
336                       object_property_get_uint(pci_host,
337                                                PCI_HOST_PROP_PCI_HOLE64_START,
338                                                NULL),
339                       object_property_get_uint(pci_host,
340                                                PCI_HOST_PROP_PCI_HOLE64_END,
341                                                NULL));
342 }
343 
344 static void acpi_align_size(GArray *blob, unsigned align)
345 {
346     /* Align size to multiple of given size. This reduces the chance
347      * we need to change size in the future (breaking cross version migration).
348      */
349     g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
350 }
351 
352 /* FACS */
353 static void
354 build_facs(GArray *table_data)
355 {
356     AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
357     memcpy(&facs->signature, "FACS", 4);
358     facs->length = cpu_to_le32(sizeof(*facs));
359 }
360 
361 static void build_append_pcihp_notify_entry(Aml *method, int slot)
362 {
363     Aml *if_ctx;
364     int32_t devfn = PCI_DEVFN(slot, 0);
365 
366     if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
367     aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
368     aml_append(method, if_ctx);
369 }
370 
371 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
372                                          bool pcihp_bridge_en)
373 {
374     Aml *dev, *notify_method = NULL, *method;
375     QObject *bsel;
376     PCIBus *sec;
377     int i;
378 
379     bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
380     if (bsel) {
381         uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
382 
383         aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
384         notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
385     }
386 
387     for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
388         DeviceClass *dc;
389         PCIDeviceClass *pc;
390         PCIDevice *pdev = bus->devices[i];
391         int slot = PCI_SLOT(i);
392         bool hotplug_enabled_dev;
393         bool bridge_in_acpi;
394         bool cold_plugged_bridge;
395 
396         if (!pdev) {
397             if (bsel) { /* add hotplug slots for non present devices */
398                 if (pci_bus_is_express(bus) && slot > 0) {
399                     break;
400                 }
401                 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
402                 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
403                 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
404                 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
405                 aml_append(method,
406                     aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
407                 );
408                 aml_append(dev, method);
409                 method = aml_method("_DSM", 4, AML_SERIALIZED);
410                 aml_append(method,
411                     aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1),
412                                          aml_arg(2), aml_arg(3),
413                                          aml_name("BSEL"), aml_name("_SUN")))
414                 );
415                 aml_append(dev, method);
416                 aml_append(parent_scope, dev);
417 
418                 build_append_pcihp_notify_entry(notify_method, slot);
419             }
420             continue;
421         }
422 
423         pc = PCI_DEVICE_GET_CLASS(pdev);
424         dc = DEVICE_GET_CLASS(pdev);
425 
426         /*
427          * Cold plugged bridges aren't themselves hot-pluggable.
428          * Hotplugged bridges *are* hot-pluggable.
429          */
430         cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
431         bridge_in_acpi =  cold_plugged_bridge && pcihp_bridge_en;
432 
433         hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
434 
435         if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
436             continue;
437         }
438 
439         /* start to compose PCI slot descriptor */
440         dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
441         aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
442 
443         if (bsel) {
444             /*
445              * Can't declare _SUN here for every device as it changes 'slot'
446              * enumeration order in linux kernel, so use another variable for it
447              */
448             aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
449             method = aml_method("_DSM", 4, AML_SERIALIZED);
450             aml_append(method, aml_return(
451                 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2),
452                           aml_arg(3), aml_name("BSEL"), aml_name("ASUN"))
453             ));
454             aml_append(dev, method);
455         }
456 
457         if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
458             /* add VGA specific AML methods */
459             int s3d;
460 
461             if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
462                 s3d = 3;
463             } else {
464                 s3d = 0;
465             }
466 
467             method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
468             aml_append(method, aml_return(aml_int(0)));
469             aml_append(dev, method);
470 
471             method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
472             aml_append(method, aml_return(aml_int(0)));
473             aml_append(dev, method);
474 
475             method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
476             aml_append(method, aml_return(aml_int(s3d)));
477             aml_append(dev, method);
478         } else if (hotplug_enabled_dev) {
479             aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
480             /* add _EJ0 to make slot hotpluggable  */
481             method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
482             aml_append(method,
483                 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
484             );
485             aml_append(dev, method);
486 
487             if (bsel) {
488                 build_append_pcihp_notify_entry(notify_method, slot);
489             }
490         } else if (bridge_in_acpi) {
491             /*
492              * device is coldplugged bridge,
493              * add child device descriptions into its scope
494              */
495             PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
496 
497             build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
498         }
499         /* slot descriptor has been composed, add it into parent context */
500         aml_append(parent_scope, dev);
501     }
502 
503     if (bsel) {
504         aml_append(parent_scope, notify_method);
505     }
506 
507     /* Append PCNT method to notify about events on local and child buses.
508      * Add this method for root bus only when hotplug is enabled since DSDT
509      * expects it.
510      */
511     if (bsel || pcihp_bridge_en) {
512         method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
513 
514         /* If bus supports hotplug select it and notify about local events */
515         if (bsel) {
516             uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
517 
518             aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
519             aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
520                                          aml_int(1))); /* Device Check */
521             aml_append(method, aml_call2("DVNT", aml_name("PCID"),
522                                          aml_int(3))); /* Eject Request */
523         }
524 
525         /* Notify about child bus events in any case */
526         if (pcihp_bridge_en) {
527             QLIST_FOREACH(sec, &bus->child, sibling) {
528                 int32_t devfn = sec->parent_dev->devfn;
529 
530                 if (pci_bus_is_root(sec)) {
531                     continue;
532                 }
533 
534                 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
535             }
536         }
537 
538         aml_append(parent_scope, method);
539     }
540     qobject_unref(bsel);
541 }
542 
543 Aml *aml_pci_device_dsm(void)
544 {
545     Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx;
546     Aml *acpi_index = aml_local(0);
547     Aml *zero = aml_int(0);
548     Aml *bnum = aml_arg(4);
549     Aml *func = aml_arg(2);
550     Aml *rev = aml_arg(1);
551     Aml *sun = aml_arg(5);
552 
553     method = aml_method("PDSM", 6, AML_SERIALIZED);
554 
555     /*
556      * PCI Firmware Specification 3.1
557      * 4.6.  _DSM Definitions for PCI
558      */
559     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
560     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
561     {
562         aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index));
563         ifctx1 = aml_if(aml_equal(func, zero));
564         {
565             uint8_t byte_list[1];
566 
567             ifctx2 = aml_if(aml_equal(rev, aml_int(2)));
568             {
569                 /*
570                  * advertise function 7 if device has acpi-index
571                  * acpi_index values:
572                  *            0: not present (default value)
573                  *     FFFFFFFF: not supported (old QEMU without PIDX reg)
574                  *        other: device's acpi-index
575                  */
576                 ifctx3 = aml_if(aml_lnot(
577                     aml_or(aml_equal(acpi_index, zero),
578                            aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
579                 ));
580                 {
581                     byte_list[0] =
582                         1 /* have supported functions */ |
583                         1 << 7 /* support for function 7 */
584                     ;
585                     aml_append(ifctx3, aml_return(aml_buffer(1, byte_list)));
586                 }
587                 aml_append(ifctx2, ifctx3);
588              }
589              aml_append(ifctx1, ifctx2);
590 
591              byte_list[0] = 0; /* nothing supported */
592              aml_append(ifctx1, aml_return(aml_buffer(1, byte_list)));
593          }
594          aml_append(ifctx, ifctx1);
595          elsectx = aml_else();
596          /*
597           * PCI Firmware Specification 3.1
598           * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
599           *        Operating Systems
600           */
601          ifctx1 = aml_if(aml_equal(func, aml_int(7)));
602          {
603              Aml *pkg = aml_package(2);
604              Aml *ret = aml_local(1);
605 
606              aml_append(pkg, zero);
607              /*
608               * optional, if not impl. should return null string
609               */
610              aml_append(pkg, aml_string("%s", ""));
611              aml_append(ifctx1, aml_store(pkg, ret));
612              /*
613               * update acpi-index to actual value
614               */
615              aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero)));
616              aml_append(ifctx1, aml_return(ret));
617          }
618          aml_append(elsectx, ifctx1);
619          aml_append(ifctx, elsectx);
620     }
621     aml_append(method, ifctx);
622     return method;
623 }
624 
625 /**
626  * build_prt_entry:
627  * @link_name: link name for PCI route entry
628  *
629  * build AML package containing a PCI route entry for @link_name
630  */
631 static Aml *build_prt_entry(const char *link_name)
632 {
633     Aml *a_zero = aml_int(0);
634     Aml *pkg = aml_package(4);
635     aml_append(pkg, a_zero);
636     aml_append(pkg, a_zero);
637     aml_append(pkg, aml_name("%s", link_name));
638     aml_append(pkg, a_zero);
639     return pkg;
640 }
641 
642 /*
643  * initialize_route - Initialize the interrupt routing rule
644  * through a specific LINK:
645  *  if (lnk_idx == idx)
646  *      route using link 'link_name'
647  */
648 static Aml *initialize_route(Aml *route, const char *link_name,
649                              Aml *lnk_idx, int idx)
650 {
651     Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
652     Aml *pkg = build_prt_entry(link_name);
653 
654     aml_append(if_ctx, aml_store(pkg, route));
655 
656     return if_ctx;
657 }
658 
659 /*
660  * build_prt - Define interrupt rounting rules
661  *
662  * Returns an array of 128 routes, one for each device,
663  * based on device location.
664  * The main goal is to equaly distribute the interrupts
665  * over the 4 existing ACPI links (works only for i440fx).
666  * The hash function is  (slot + pin) & 3 -> "LNK[D|A|B|C]".
667  *
668  */
669 static Aml *build_prt(bool is_pci0_prt)
670 {
671     Aml *method, *while_ctx, *pin, *res;
672 
673     method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
674     res = aml_local(0);
675     pin = aml_local(1);
676     aml_append(method, aml_store(aml_package(128), res));
677     aml_append(method, aml_store(aml_int(0), pin));
678 
679     /* while (pin < 128) */
680     while_ctx = aml_while(aml_lless(pin, aml_int(128)));
681     {
682         Aml *slot = aml_local(2);
683         Aml *lnk_idx = aml_local(3);
684         Aml *route = aml_local(4);
685 
686         /* slot = pin >> 2 */
687         aml_append(while_ctx,
688                    aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
689         /* lnk_idx = (slot + pin) & 3 */
690         aml_append(while_ctx,
691             aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
692                       lnk_idx));
693 
694         /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3  */
695         aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
696         if (is_pci0_prt) {
697             Aml *if_device_1, *if_pin_4, *else_pin_4;
698 
699             /* device 1 is the power-management device, needs SCI */
700             if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
701             {
702                 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
703                 {
704                     aml_append(if_pin_4,
705                         aml_store(build_prt_entry("LNKS"), route));
706                 }
707                 aml_append(if_device_1, if_pin_4);
708                 else_pin_4 = aml_else();
709                 {
710                     aml_append(else_pin_4,
711                         aml_store(build_prt_entry("LNKA"), route));
712                 }
713                 aml_append(if_device_1, else_pin_4);
714             }
715             aml_append(while_ctx, if_device_1);
716         } else {
717             aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
718         }
719         aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
720         aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
721 
722         /* route[0] = 0x[slot]FFFF */
723         aml_append(while_ctx,
724             aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
725                              NULL),
726                       aml_index(route, aml_int(0))));
727         /* route[1] = pin & 3 */
728         aml_append(while_ctx,
729             aml_store(aml_and(pin, aml_int(3), NULL),
730                       aml_index(route, aml_int(1))));
731         /* res[pin] = route */
732         aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
733         /* pin++ */
734         aml_append(while_ctx, aml_increment(pin));
735     }
736     aml_append(method, while_ctx);
737     /* return res*/
738     aml_append(method, aml_return(res));
739 
740     return method;
741 }
742 
743 static void build_hpet_aml(Aml *table)
744 {
745     Aml *crs;
746     Aml *field;
747     Aml *method;
748     Aml *if_ctx;
749     Aml *scope = aml_scope("_SB");
750     Aml *dev = aml_device("HPET");
751     Aml *zero = aml_int(0);
752     Aml *id = aml_local(0);
753     Aml *period = aml_local(1);
754 
755     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
756     aml_append(dev, aml_name_decl("_UID", zero));
757 
758     aml_append(dev,
759         aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
760                              HPET_LEN));
761     field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
762     aml_append(field, aml_named_field("VEND", 32));
763     aml_append(field, aml_named_field("PRD", 32));
764     aml_append(dev, field);
765 
766     method = aml_method("_STA", 0, AML_NOTSERIALIZED);
767     aml_append(method, aml_store(aml_name("VEND"), id));
768     aml_append(method, aml_store(aml_name("PRD"), period));
769     aml_append(method, aml_shiftright(id, aml_int(16), id));
770     if_ctx = aml_if(aml_lor(aml_equal(id, zero),
771                             aml_equal(id, aml_int(0xffff))));
772     {
773         aml_append(if_ctx, aml_return(zero));
774     }
775     aml_append(method, if_ctx);
776 
777     if_ctx = aml_if(aml_lor(aml_equal(period, zero),
778                             aml_lgreater(period, aml_int(100000000))));
779     {
780         aml_append(if_ctx, aml_return(zero));
781     }
782     aml_append(method, if_ctx);
783 
784     aml_append(method, aml_return(aml_int(0x0F)));
785     aml_append(dev, method);
786 
787     crs = aml_resource_template();
788     aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
789     aml_append(dev, aml_name_decl("_CRS", crs));
790 
791     aml_append(scope, dev);
792     aml_append(table, scope);
793 }
794 
795 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
796 {
797     Aml *dev;
798     Aml *method;
799     Aml *crs;
800 
801     dev = aml_device("VMBS");
802     aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
803     aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
804     aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
805     aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
806 
807     method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
808     aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
809                                      aml_name("STA")));
810     aml_append(dev, method);
811 
812     method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
813     aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
814                                      aml_name("STA")));
815     aml_append(dev, method);
816 
817     method = aml_method("_STA", 0, AML_NOTSERIALIZED);
818     aml_append(method, aml_return(aml_name("STA")));
819     aml_append(dev, method);
820 
821     aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
822 
823     crs = aml_resource_template();
824     aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
825     aml_append(dev, aml_name_decl("_CRS", crs));
826 
827     return dev;
828 }
829 
830 static void build_isa_devices_aml(Aml *table)
831 {
832     bool ambiguous;
833     Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
834     Aml *scope;
835 
836     assert(obj && !ambiguous);
837 
838     scope = aml_scope("_SB.PCI0.ISA");
839     build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
840     isa_build_aml(ISA_BUS(obj), scope);
841 
842     aml_append(table, scope);
843 }
844 
845 static void build_dbg_aml(Aml *table)
846 {
847     Aml *field;
848     Aml *method;
849     Aml *while_ctx;
850     Aml *scope = aml_scope("\\");
851     Aml *buf = aml_local(0);
852     Aml *len = aml_local(1);
853     Aml *idx = aml_local(2);
854 
855     aml_append(scope,
856        aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
857     field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
858     aml_append(field, aml_named_field("DBGB", 8));
859     aml_append(scope, field);
860 
861     method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
862 
863     aml_append(method, aml_to_hexstring(aml_arg(0), buf));
864     aml_append(method, aml_to_buffer(buf, buf));
865     aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
866     aml_append(method, aml_store(aml_int(0), idx));
867 
868     while_ctx = aml_while(aml_lless(idx, len));
869     aml_append(while_ctx,
870         aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
871     aml_append(while_ctx, aml_increment(idx));
872     aml_append(method, while_ctx);
873 
874     aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
875     aml_append(scope, method);
876 
877     aml_append(table, scope);
878 }
879 
880 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
881 {
882     Aml *dev;
883     Aml *crs;
884     Aml *method;
885     uint32_t irqs[] = {5, 10, 11};
886 
887     dev = aml_device("%s", name);
888     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
889     aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
890 
891     crs = aml_resource_template();
892     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
893                                   AML_SHARED, irqs, ARRAY_SIZE(irqs)));
894     aml_append(dev, aml_name_decl("_PRS", crs));
895 
896     method = aml_method("_STA", 0, AML_NOTSERIALIZED);
897     aml_append(method, aml_return(aml_call1("IQST", reg)));
898     aml_append(dev, method);
899 
900     method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
901     aml_append(method, aml_or(reg, aml_int(0x80), reg));
902     aml_append(dev, method);
903 
904     method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
905     aml_append(method, aml_return(aml_call1("IQCR", reg)));
906     aml_append(dev, method);
907 
908     method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
909     aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
910     aml_append(method, aml_store(aml_name("PRRI"), reg));
911     aml_append(dev, method);
912 
913     return dev;
914  }
915 
916 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
917 {
918     Aml *dev;
919     Aml *crs;
920     Aml *method;
921     uint32_t irqs;
922 
923     dev = aml_device("%s", name);
924     aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
925     aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
926 
927     crs = aml_resource_template();
928     irqs = gsi;
929     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
930                                   AML_SHARED, &irqs, 1));
931     aml_append(dev, aml_name_decl("_PRS", crs));
932 
933     aml_append(dev, aml_name_decl("_CRS", crs));
934 
935     /*
936      * _DIS can be no-op because the interrupt cannot be disabled.
937      */
938     method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
939     aml_append(dev, method);
940 
941     method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
942     aml_append(dev, method);
943 
944     return dev;
945 }
946 
947 /* _CRS method - get current settings */
948 static Aml *build_iqcr_method(bool is_piix4)
949 {
950     Aml *if_ctx;
951     uint32_t irqs;
952     Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
953     Aml *crs = aml_resource_template();
954 
955     irqs = 0;
956     aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
957                                   AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
958     aml_append(method, aml_name_decl("PRR0", crs));
959 
960     aml_append(method,
961         aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
962 
963     if (is_piix4) {
964         if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
965         aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
966         aml_append(method, if_ctx);
967     } else {
968         aml_append(method,
969             aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
970                       aml_name("PRRI")));
971     }
972 
973     aml_append(method, aml_return(aml_name("PRR0")));
974     return method;
975 }
976 
977 /* _STA method - get status */
978 static Aml *build_irq_status_method(void)
979 {
980     Aml *if_ctx;
981     Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
982 
983     if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
984     aml_append(if_ctx, aml_return(aml_int(0x09)));
985     aml_append(method, if_ctx);
986     aml_append(method, aml_return(aml_int(0x0B)));
987     return method;
988 }
989 
990 static void build_piix4_pci0_int(Aml *table)
991 {
992     Aml *dev;
993     Aml *crs;
994     Aml *field;
995     Aml *method;
996     uint32_t irqs;
997     Aml *sb_scope = aml_scope("_SB");
998     Aml *pci0_scope = aml_scope("PCI0");
999 
1000     aml_append(pci0_scope, build_prt(true));
1001     aml_append(sb_scope, pci0_scope);
1002 
1003     field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1004     aml_append(field, aml_named_field("PRQ0", 8));
1005     aml_append(field, aml_named_field("PRQ1", 8));
1006     aml_append(field, aml_named_field("PRQ2", 8));
1007     aml_append(field, aml_named_field("PRQ3", 8));
1008     aml_append(sb_scope, field);
1009 
1010     aml_append(sb_scope, build_irq_status_method());
1011     aml_append(sb_scope, build_iqcr_method(true));
1012 
1013     aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1014     aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1015     aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1016     aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1017 
1018     dev = aml_device("LNKS");
1019     {
1020         aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1021         aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1022 
1023         crs = aml_resource_template();
1024         irqs = 9;
1025         aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1026                                       AML_ACTIVE_HIGH, AML_SHARED,
1027                                       &irqs, 1));
1028         aml_append(dev, aml_name_decl("_PRS", crs));
1029 
1030         /* The SCI cannot be disabled and is always attached to GSI 9,
1031          * so these are no-ops.  We only need this link to override the
1032          * polarity to active high and match the content of the MADT.
1033          */
1034         method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1035         aml_append(method, aml_return(aml_int(0x0b)));
1036         aml_append(dev, method);
1037 
1038         method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1039         aml_append(dev, method);
1040 
1041         method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1042         aml_append(method, aml_return(aml_name("_PRS")));
1043         aml_append(dev, method);
1044 
1045         method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1046         aml_append(dev, method);
1047     }
1048     aml_append(sb_scope, dev);
1049 
1050     aml_append(table, sb_scope);
1051 }
1052 
1053 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1054 {
1055     int i;
1056     int head;
1057     Aml *pkg;
1058     char base = name[3] < 'E' ? 'A' : 'E';
1059     char *s = g_strdup(name);
1060     Aml *a_nr = aml_int((nr << 16) | 0xffff);
1061 
1062     assert(strlen(s) == 4);
1063 
1064     head = name[3] - base;
1065     for (i = 0; i < 4; i++) {
1066         if (head + i > 3) {
1067             head = i * -1;
1068         }
1069         s[3] = base + head + i;
1070         pkg = aml_package(4);
1071         aml_append(pkg, a_nr);
1072         aml_append(pkg, aml_int(i));
1073         aml_append(pkg, aml_name("%s", s));
1074         aml_append(pkg, aml_int(0));
1075         aml_append(ctx, pkg);
1076     }
1077     g_free(s);
1078 }
1079 
1080 static Aml *build_q35_routing_table(const char *str)
1081 {
1082     int i;
1083     Aml *pkg;
1084     char *name = g_strdup_printf("%s ", str);
1085 
1086     pkg = aml_package(128);
1087     for (i = 0; i < 0x18; i++) {
1088             name[3] = 'E' + (i & 0x3);
1089             append_q35_prt_entry(pkg, i, name);
1090     }
1091 
1092     name[3] = 'E';
1093     append_q35_prt_entry(pkg, 0x18, name);
1094 
1095     /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1096     for (i = 0x0019; i < 0x1e; i++) {
1097         name[3] = 'A';
1098         append_q35_prt_entry(pkg, i, name);
1099     }
1100 
1101     /* PCIe->PCI bridge. use PIRQ[E-H] */
1102     name[3] = 'E';
1103     append_q35_prt_entry(pkg, 0x1e, name);
1104     name[3] = 'A';
1105     append_q35_prt_entry(pkg, 0x1f, name);
1106 
1107     g_free(name);
1108     return pkg;
1109 }
1110 
1111 static void build_q35_pci0_int(Aml *table)
1112 {
1113     Aml *field;
1114     Aml *method;
1115     Aml *sb_scope = aml_scope("_SB");
1116     Aml *pci0_scope = aml_scope("PCI0");
1117 
1118     /* Zero => PIC mode, One => APIC Mode */
1119     aml_append(table, aml_name_decl("PICF", aml_int(0)));
1120     method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1121     {
1122         aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1123     }
1124     aml_append(table, method);
1125 
1126     aml_append(pci0_scope,
1127         aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1128     aml_append(pci0_scope,
1129         aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1130 
1131     method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1132     {
1133         Aml *if_ctx;
1134         Aml *else_ctx;
1135 
1136         /* PCI IRQ routing table, example from ACPI 2.0a specification,
1137            section 6.2.8.1 */
1138         /* Note: we provide the same info as the PCI routing
1139            table of the Bochs BIOS */
1140         if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1141         aml_append(if_ctx, aml_return(aml_name("PRTP")));
1142         aml_append(method, if_ctx);
1143         else_ctx = aml_else();
1144         aml_append(else_ctx, aml_return(aml_name("PRTA")));
1145         aml_append(method, else_ctx);
1146     }
1147     aml_append(pci0_scope, method);
1148     aml_append(sb_scope, pci0_scope);
1149 
1150     field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1151     aml_append(field, aml_named_field("PRQA", 8));
1152     aml_append(field, aml_named_field("PRQB", 8));
1153     aml_append(field, aml_named_field("PRQC", 8));
1154     aml_append(field, aml_named_field("PRQD", 8));
1155     aml_append(field, aml_reserved_field(0x20));
1156     aml_append(field, aml_named_field("PRQE", 8));
1157     aml_append(field, aml_named_field("PRQF", 8));
1158     aml_append(field, aml_named_field("PRQG", 8));
1159     aml_append(field, aml_named_field("PRQH", 8));
1160     aml_append(sb_scope, field);
1161 
1162     aml_append(sb_scope, build_irq_status_method());
1163     aml_append(sb_scope, build_iqcr_method(false));
1164 
1165     aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1166     aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1167     aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1168     aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1169     aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1170     aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1171     aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1172     aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1173 
1174     aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1175     aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1176     aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1177     aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1178     aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1179     aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1180     aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1181     aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1182 
1183     aml_append(table, sb_scope);
1184 }
1185 
1186 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1187 {
1188     Aml *dev;
1189     Aml *resource_template;
1190 
1191     /* DRAM controller */
1192     dev = aml_device("DRAC");
1193     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1194 
1195     resource_template = aml_resource_template();
1196     if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1197         aml_append(resource_template,
1198                    aml_qword_memory(AML_POS_DECODE,
1199                                     AML_MIN_FIXED,
1200                                     AML_MAX_FIXED,
1201                                     AML_NON_CACHEABLE,
1202                                     AML_READ_WRITE,
1203                                     0x0000000000000000,
1204                                     mcfg->base,
1205                                     mcfg->base + mcfg->size - 1,
1206                                     0x0000000000000000,
1207                                     mcfg->size));
1208     } else {
1209         aml_append(resource_template,
1210                    aml_dword_memory(AML_POS_DECODE,
1211                                     AML_MIN_FIXED,
1212                                     AML_MAX_FIXED,
1213                                     AML_NON_CACHEABLE,
1214                                     AML_READ_WRITE,
1215                                     0x0000000000000000,
1216                                     mcfg->base,
1217                                     mcfg->base + mcfg->size - 1,
1218                                     0x0000000000000000,
1219                                     mcfg->size));
1220     }
1221     aml_append(dev, aml_name_decl("_CRS", resource_template));
1222 
1223     return dev;
1224 }
1225 
1226 static void build_q35_isa_bridge(Aml *table)
1227 {
1228     Aml *dev;
1229     Aml *scope;
1230 
1231     scope =  aml_scope("_SB.PCI0");
1232     dev = aml_device("ISA");
1233     aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1234 
1235     /* ICH9 PCI to ISA irq remapping */
1236     aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1237                                          aml_int(0x60), 0x0C));
1238 
1239     aml_append(scope, dev);
1240     aml_append(table, scope);
1241 }
1242 
1243 static void build_piix4_isa_bridge(Aml *table)
1244 {
1245     Aml *dev;
1246     Aml *scope;
1247 
1248     scope =  aml_scope("_SB.PCI0");
1249     dev = aml_device("ISA");
1250     aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1251 
1252     /* PIIX PCI to ISA irq remapping */
1253     aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1254                                          aml_int(0x60), 0x04));
1255 
1256     aml_append(scope, dev);
1257     aml_append(table, scope);
1258 }
1259 
1260 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
1261 {
1262     Aml *scope;
1263     Aml *field;
1264     Aml *method;
1265 
1266     scope =  aml_scope("_SB.PCI0");
1267 
1268     aml_append(scope,
1269         aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
1270     field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1271     aml_append(field, aml_named_field("PCIU", 32));
1272     aml_append(field, aml_named_field("PCID", 32));
1273     aml_append(scope, field);
1274 
1275     aml_append(scope,
1276         aml_operation_region("SEJ", AML_SYSTEM_IO,
1277                              aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
1278     field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1279     aml_append(field, aml_named_field("B0EJ", 32));
1280     aml_append(scope, field);
1281 
1282     aml_append(scope,
1283         aml_operation_region("BNMR", AML_SYSTEM_IO,
1284                              aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
1285     field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1286     aml_append(field, aml_named_field("BNUM", 32));
1287     aml_append(field, aml_named_field("PIDX", 32));
1288     aml_append(scope, field);
1289 
1290     aml_append(scope, aml_mutex("BLCK", 0));
1291 
1292     method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1293     aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1294     aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1295     aml_append(method,
1296         aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1297     aml_append(method, aml_release(aml_name("BLCK")));
1298     aml_append(method, aml_return(aml_int(0)));
1299     aml_append(scope, method);
1300 
1301     method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1302     aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1303     aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1304     aml_append(method,
1305         aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1306     aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1307     aml_append(method, aml_release(aml_name("BLCK")));
1308     aml_append(method, aml_return(aml_local(0)));
1309     aml_append(scope, method);
1310 
1311     aml_append(scope, aml_pci_device_dsm());
1312 
1313     aml_append(table, scope);
1314 }
1315 
1316 static Aml *build_q35_osc_method(void)
1317 {
1318     Aml *if_ctx;
1319     Aml *if_ctx2;
1320     Aml *else_ctx;
1321     Aml *method;
1322     Aml *a_cwd1 = aml_name("CDW1");
1323     Aml *a_ctrl = aml_local(0);
1324 
1325     method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1326     aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1327 
1328     if_ctx = aml_if(aml_equal(
1329         aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1330     aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1331     aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1332 
1333     aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1334 
1335     /*
1336      * Always allow native PME, AER (no dependencies)
1337      * Allow SHPC (PCI bridges can have SHPC controller)
1338      */
1339     aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1340 
1341     if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1342     /* Unknown revision */
1343     aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1344     aml_append(if_ctx, if_ctx2);
1345 
1346     if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1347     /* Capabilities bits were masked */
1348     aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1349     aml_append(if_ctx, if_ctx2);
1350 
1351     /* Update DWORD3 in the buffer */
1352     aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1353     aml_append(method, if_ctx);
1354 
1355     else_ctx = aml_else();
1356     /* Unrecognized UUID */
1357     aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1358     aml_append(method, else_ctx);
1359 
1360     aml_append(method, aml_return(aml_arg(3)));
1361     return method;
1362 }
1363 
1364 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1365 {
1366     Aml *scope = aml_scope("_SB.PCI0");
1367     Aml *dev = aml_device("SMB0");
1368 
1369     aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1370     build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1371     aml_append(scope, dev);
1372     aml_append(table, scope);
1373 }
1374 
1375 static void
1376 build_dsdt(GArray *table_data, BIOSLinker *linker,
1377            AcpiPmInfo *pm, AcpiMiscInfo *misc,
1378            Range *pci_hole, Range *pci_hole64, MachineState *machine)
1379 {
1380     CrsRangeEntry *entry;
1381     Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1382     CrsRangeSet crs_range_set;
1383     PCMachineState *pcms = PC_MACHINE(machine);
1384     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1385     X86MachineState *x86ms = X86_MACHINE(machine);
1386     AcpiMcfgInfo mcfg;
1387     bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
1388     uint32_t nr_mem = machine->ram_slots;
1389     int root_bus_limit = 0xFF;
1390     PCIBus *bus = NULL;
1391 #ifdef CONFIG_TPM
1392     TPMIf *tpm = tpm_find();
1393 #endif
1394     int i;
1395     VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1396 
1397     dsdt = init_aml_allocator();
1398 
1399     /* Reserve space for header */
1400     acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1401 
1402     build_dbg_aml(dsdt);
1403     if (misc->is_piix4) {
1404         sb_scope = aml_scope("_SB");
1405         dev = aml_device("PCI0");
1406         aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1407         aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1408         aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1409         aml_append(sb_scope, dev);
1410         aml_append(dsdt, sb_scope);
1411 
1412         if (misc->has_hpet) {
1413             build_hpet_aml(dsdt);
1414         }
1415         build_piix4_isa_bridge(dsdt);
1416         build_isa_devices_aml(dsdt);
1417         if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1418             build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1419         }
1420         build_piix4_pci0_int(dsdt);
1421     } else {
1422         sb_scope = aml_scope("_SB");
1423         dev = aml_device("PCI0");
1424         aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1425         aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1426         aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1427         aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1428         aml_append(dev, build_q35_osc_method());
1429         aml_append(sb_scope, dev);
1430         if (mcfg_valid) {
1431             aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1432         }
1433 
1434         if (pm->smi_on_cpuhp) {
1435             /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1436             dev = aml_device("PCI0.SMI0");
1437             aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1438             aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1439             crs = aml_resource_template();
1440             aml_append(crs,
1441                 aml_io(
1442                        AML_DECODE16,
1443                        ACPI_PORT_SMI_CMD,
1444                        ACPI_PORT_SMI_CMD,
1445                        1,
1446                        2)
1447             );
1448             aml_append(dev, aml_name_decl("_CRS", crs));
1449             aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1450                 aml_int(ACPI_PORT_SMI_CMD), 2));
1451             field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1452                               AML_WRITE_AS_ZEROS);
1453             aml_append(field, aml_named_field("SMIC", 8));
1454             aml_append(field, aml_reserved_field(8));
1455             aml_append(dev, field);
1456             aml_append(sb_scope, dev);
1457         }
1458 
1459         aml_append(dsdt, sb_scope);
1460 
1461         if (misc->has_hpet) {
1462             build_hpet_aml(dsdt);
1463         }
1464         build_q35_isa_bridge(dsdt);
1465         build_isa_devices_aml(dsdt);
1466         if (pm->pcihp_bridge_en) {
1467             build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1468         }
1469         build_q35_pci0_int(dsdt);
1470         if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1471             build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1472         }
1473     }
1474 
1475     if (vmbus_bridge) {
1476         sb_scope = aml_scope("_SB");
1477         aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1478         aml_append(dsdt, sb_scope);
1479     }
1480 
1481     if (pcmc->legacy_cpu_hotplug) {
1482         build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1483     } else {
1484         CPUHotplugFeatures opts = {
1485             .acpi_1_compatible = true, .has_legacy_cphp = true,
1486             .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1487             .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1488         };
1489         build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1490                        "\\_SB.PCI0", "\\_GPE._E02");
1491     }
1492 
1493     if (pcms->memhp_io_base && nr_mem) {
1494         build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1495                                  "\\_GPE._E03", AML_SYSTEM_IO,
1496                                  pcms->memhp_io_base);
1497     }
1498 
1499     scope =  aml_scope("_GPE");
1500     {
1501         aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1502 
1503         if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1504             method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1505             aml_append(method,
1506                 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1507             aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1508             aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1509             aml_append(scope, method);
1510         }
1511 
1512         if (machine->nvdimms_state->is_enabled) {
1513             method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1514             aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1515                                           aml_int(0x80)));
1516             aml_append(scope, method);
1517         }
1518     }
1519     aml_append(dsdt, scope);
1520 
1521     crs_range_set_init(&crs_range_set);
1522     bus = PC_MACHINE(machine)->bus;
1523     if (bus) {
1524         QLIST_FOREACH(bus, &bus->child, sibling) {
1525             uint8_t bus_num = pci_bus_num(bus);
1526             uint8_t numa_node = pci_bus_numa_node(bus);
1527 
1528             /* look only for expander root buses */
1529             if (!pci_bus_is_root(bus)) {
1530                 continue;
1531             }
1532 
1533             if (bus_num < root_bus_limit) {
1534                 root_bus_limit = bus_num - 1;
1535             }
1536 
1537             scope = aml_scope("\\_SB");
1538             dev = aml_device("PC%.02X", bus_num);
1539             aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1540             aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1541             if (pci_bus_is_express(bus)) {
1542                 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1543                 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1544                 aml_append(dev, build_q35_osc_method());
1545             } else {
1546                 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1547             }
1548 
1549             if (numa_node != NUMA_NODE_UNASSIGNED) {
1550                 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1551             }
1552 
1553             aml_append(dev, build_prt(false));
1554             crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1555                             0, 0, 0, 0);
1556             aml_append(dev, aml_name_decl("_CRS", crs));
1557             aml_append(scope, dev);
1558             aml_append(dsdt, scope);
1559         }
1560     }
1561 
1562     /*
1563      * At this point crs_range_set has all the ranges used by pci
1564      * busses *other* than PCI0.  These ranges will be excluded from
1565      * the PCI0._CRS.  Add mmconfig to the set so it will be excluded
1566      * too.
1567      */
1568     if (mcfg_valid) {
1569         crs_range_insert(crs_range_set.mem_ranges,
1570                          mcfg.base, mcfg.base + mcfg.size - 1);
1571     }
1572 
1573     scope = aml_scope("\\_SB.PCI0");
1574     /* build PCI0._CRS */
1575     crs = aml_resource_template();
1576     aml_append(crs,
1577         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1578                             0x0000, 0x0, root_bus_limit,
1579                             0x0000, root_bus_limit + 1));
1580     aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1581 
1582     aml_append(crs,
1583         aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1584                     AML_POS_DECODE, AML_ENTIRE_RANGE,
1585                     0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1586 
1587     crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1588     for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1589         entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1590         aml_append(crs,
1591             aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1592                         AML_POS_DECODE, AML_ENTIRE_RANGE,
1593                         0x0000, entry->base, entry->limit,
1594                         0x0000, entry->limit - entry->base + 1));
1595     }
1596 
1597     aml_append(crs,
1598         aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1599                          AML_CACHEABLE, AML_READ_WRITE,
1600                          0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1601 
1602     crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1603                                  range_lob(pci_hole),
1604                                  range_upb(pci_hole));
1605     for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1606         entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1607         aml_append(crs,
1608             aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1609                              AML_NON_CACHEABLE, AML_READ_WRITE,
1610                              0, entry->base, entry->limit,
1611                              0, entry->limit - entry->base + 1));
1612     }
1613 
1614     if (!range_is_empty(pci_hole64)) {
1615         crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1616                                      range_lob(pci_hole64),
1617                                      range_upb(pci_hole64));
1618         for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1619             entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1620             aml_append(crs,
1621                        aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1622                                         AML_MAX_FIXED,
1623                                         AML_CACHEABLE, AML_READ_WRITE,
1624                                         0, entry->base, entry->limit,
1625                                         0, entry->limit - entry->base + 1));
1626         }
1627     }
1628 
1629 #ifdef CONFIG_TPM
1630     if (TPM_IS_TIS_ISA(tpm_find())) {
1631         aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1632                    TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1633     }
1634 #endif
1635     aml_append(scope, aml_name_decl("_CRS", crs));
1636 
1637     /* reserve GPE0 block resources */
1638     dev = aml_device("GPE0");
1639     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1640     aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1641     /* device present, functioning, decoding, not shown in UI */
1642     aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1643     crs = aml_resource_template();
1644     aml_append(crs,
1645         aml_io(
1646                AML_DECODE16,
1647                pm->fadt.gpe0_blk.address,
1648                pm->fadt.gpe0_blk.address,
1649                1,
1650                pm->fadt.gpe0_blk.bit_width / 8)
1651     );
1652     aml_append(dev, aml_name_decl("_CRS", crs));
1653     aml_append(scope, dev);
1654 
1655     crs_range_set_free(&crs_range_set);
1656 
1657     /* reserve PCIHP resources */
1658     if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1659         dev = aml_device("PHPR");
1660         aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1661         aml_append(dev,
1662             aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1663         /* device present, functioning, decoding, not shown in UI */
1664         aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1665         crs = aml_resource_template();
1666         aml_append(crs,
1667             aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1668                    pm->pcihp_io_len)
1669         );
1670         aml_append(dev, aml_name_decl("_CRS", crs));
1671         aml_append(scope, dev);
1672     }
1673     aml_append(dsdt, scope);
1674 
1675     /*  create S3_ / S4_ / S5_ packages if necessary */
1676     scope = aml_scope("\\");
1677     if (!pm->s3_disabled) {
1678         pkg = aml_package(4);
1679         aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1680         aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1681         aml_append(pkg, aml_int(0)); /* reserved */
1682         aml_append(pkg, aml_int(0)); /* reserved */
1683         aml_append(scope, aml_name_decl("_S3", pkg));
1684     }
1685 
1686     if (!pm->s4_disabled) {
1687         pkg = aml_package(4);
1688         aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1689         /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1690         aml_append(pkg, aml_int(pm->s4_val));
1691         aml_append(pkg, aml_int(0)); /* reserved */
1692         aml_append(pkg, aml_int(0)); /* reserved */
1693         aml_append(scope, aml_name_decl("_S4", pkg));
1694     }
1695 
1696     pkg = aml_package(4);
1697     aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1698     aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1699     aml_append(pkg, aml_int(0)); /* reserved */
1700     aml_append(pkg, aml_int(0)); /* reserved */
1701     aml_append(scope, aml_name_decl("_S5", pkg));
1702     aml_append(dsdt, scope);
1703 
1704     /* create fw_cfg node, unconditionally */
1705     {
1706         scope = aml_scope("\\_SB.PCI0");
1707         fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1708         aml_append(dsdt, scope);
1709     }
1710 
1711     if (misc->applesmc_io_base) {
1712         scope = aml_scope("\\_SB.PCI0.ISA");
1713         dev = aml_device("SMC");
1714 
1715         aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1716         /* device present, functioning, decoding, not shown in UI */
1717         aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1718 
1719         crs = aml_resource_template();
1720         aml_append(crs,
1721             aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1722                    0x01, APPLESMC_MAX_DATA_LENGTH)
1723         );
1724         aml_append(crs, aml_irq_no_flags(6));
1725         aml_append(dev, aml_name_decl("_CRS", crs));
1726 
1727         aml_append(scope, dev);
1728         aml_append(dsdt, scope);
1729     }
1730 
1731     if (misc->pvpanic_port) {
1732         scope = aml_scope("\\_SB.PCI0.ISA");
1733 
1734         dev = aml_device("PEVT");
1735         aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1736 
1737         crs = aml_resource_template();
1738         aml_append(crs,
1739             aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1740         );
1741         aml_append(dev, aml_name_decl("_CRS", crs));
1742 
1743         aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1744                                               aml_int(misc->pvpanic_port), 1));
1745         field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1746         aml_append(field, aml_named_field("PEPT", 8));
1747         aml_append(dev, field);
1748 
1749         /* device present, functioning, decoding, shown in UI */
1750         aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1751 
1752         method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1753         aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1754         aml_append(method, aml_return(aml_local(0)));
1755         aml_append(dev, method);
1756 
1757         method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1758         aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1759         aml_append(dev, method);
1760 
1761         aml_append(scope, dev);
1762         aml_append(dsdt, scope);
1763     }
1764 
1765     sb_scope = aml_scope("\\_SB");
1766     {
1767         Object *pci_host;
1768         PCIBus *bus = NULL;
1769 
1770         pci_host = acpi_get_i386_pci_host();
1771 
1772         if (pci_host) {
1773             bus = PCI_HOST_BRIDGE(pci_host)->bus;
1774         }
1775 
1776         if (bus) {
1777             Aml *scope = aml_scope("PCI0");
1778             /* Scan all PCI buses. Generate tables to support hotplug. */
1779             build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1780 
1781 #ifdef CONFIG_TPM
1782             if (TPM_IS_TIS_ISA(tpm)) {
1783                 if (misc->tpm_version == TPM_VERSION_2_0) {
1784                     dev = aml_device("TPM");
1785                     aml_append(dev, aml_name_decl("_HID",
1786                                                   aml_string("MSFT0101")));
1787                 } else {
1788                     dev = aml_device("ISA.TPM");
1789                     aml_append(dev, aml_name_decl("_HID",
1790                                                   aml_eisaid("PNP0C31")));
1791                 }
1792 
1793                 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1794                 crs = aml_resource_template();
1795                 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1796                            TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1797                 /*
1798                     FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1799                     Rewrite to take IRQ from TPM device model and
1800                     fix default IRQ value there to use some unused IRQ
1801                  */
1802                 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1803                 aml_append(dev, aml_name_decl("_CRS", crs));
1804 
1805                 tpm_build_ppi_acpi(tpm, dev);
1806 
1807                 aml_append(scope, dev);
1808             }
1809 #endif
1810 
1811             aml_append(sb_scope, scope);
1812         }
1813     }
1814 
1815 #ifdef CONFIG_TPM
1816     if (TPM_IS_CRB(tpm)) {
1817         dev = aml_device("TPM");
1818         aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1819         crs = aml_resource_template();
1820         aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1821                                            TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1822         aml_append(dev, aml_name_decl("_CRS", crs));
1823 
1824         aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1825 
1826         tpm_build_ppi_acpi(tpm, dev);
1827 
1828         aml_append(sb_scope, dev);
1829     }
1830 #endif
1831 
1832     aml_append(dsdt, sb_scope);
1833 
1834     /* copy AML table into ACPI tables blob and patch header there */
1835     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1836     build_header(linker, table_data,
1837         (void *)(table_data->data + table_data->len - dsdt->buf->len),
1838                  "DSDT", dsdt->buf->len, 1, x86ms->oem_id, x86ms->oem_table_id);
1839     free_aml_allocator();
1840 }
1841 
1842 static void
1843 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1844            const char *oem_table_id)
1845 {
1846     Acpi20Hpet *hpet;
1847     int hpet_start = table_data->len;
1848 
1849     hpet = acpi_data_push(table_data, sizeof(*hpet));
1850     /* Note timer_block_id value must be kept in sync with value advertised by
1851      * emulated hpet
1852      */
1853     hpet->timer_block_id = cpu_to_le32(0x8086a201);
1854     hpet->addr.address = cpu_to_le64(HPET_BASE);
1855     build_header(linker, table_data,
1856                  (void *)(table_data->data + hpet_start),
1857                  "HPET", sizeof(*hpet), 1, oem_id, oem_table_id);
1858 }
1859 
1860 #ifdef CONFIG_TPM
1861 static void
1862 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1863                const char *oem_id, const char *oem_table_id)
1864 {
1865     int tcpa_start = table_data->len;
1866     Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1867     unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
1868     unsigned log_addr_offset =
1869         (char *)&tcpa->log_area_start_address - table_data->data;
1870 
1871     tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1872     tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1873     acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
1874 
1875     bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1876                              false /* high memory */);
1877 
1878     /* log area start address to be filled by Guest linker */
1879     bios_linker_loader_add_pointer(linker,
1880         ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
1881         ACPI_BUILD_TPMLOG_FILE, 0);
1882 
1883     build_header(linker, table_data,
1884                  (void *)(table_data->data + tcpa_start),
1885                  "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id);
1886 }
1887 #endif
1888 
1889 #define HOLE_640K_START  (640 * KiB)
1890 #define HOLE_640K_END   (1 * MiB)
1891 
1892 static void
1893 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1894 {
1895     AcpiSystemResourceAffinityTable *srat;
1896     AcpiSratMemoryAffinity *numamem;
1897 
1898     int i;
1899     int srat_start, numa_start, slots;
1900     uint64_t mem_len, mem_base, next_base;
1901     MachineClass *mc = MACHINE_GET_CLASS(machine);
1902     X86MachineState *x86ms = X86_MACHINE(machine);
1903     const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1904     PCMachineState *pcms = PC_MACHINE(machine);
1905     ram_addr_t hotplugabble_address_space_size =
1906         object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1907                                 NULL);
1908 
1909     srat_start = table_data->len;
1910 
1911     srat = acpi_data_push(table_data, sizeof *srat);
1912     srat->reserved1 = cpu_to_le32(1);
1913 
1914     for (i = 0; i < apic_ids->len; i++) {
1915         int node_id = apic_ids->cpus[i].props.node_id;
1916         uint32_t apic_id = apic_ids->cpus[i].arch_id;
1917 
1918         if (apic_id < 255) {
1919             AcpiSratProcessorAffinity *core;
1920 
1921             core = acpi_data_push(table_data, sizeof *core);
1922             core->type = ACPI_SRAT_PROCESSOR_APIC;
1923             core->length = sizeof(*core);
1924             core->local_apic_id = apic_id;
1925             core->proximity_lo = node_id;
1926             memset(core->proximity_hi, 0, 3);
1927             core->local_sapic_eid = 0;
1928             core->flags = cpu_to_le32(1);
1929         } else {
1930             AcpiSratProcessorX2ApicAffinity *core;
1931 
1932             core = acpi_data_push(table_data, sizeof *core);
1933             core->type = ACPI_SRAT_PROCESSOR_x2APIC;
1934             core->length = sizeof(*core);
1935             core->x2apic_id = cpu_to_le32(apic_id);
1936             core->proximity_domain = cpu_to_le32(node_id);
1937             core->flags = cpu_to_le32(1);
1938         }
1939     }
1940 
1941 
1942     /* the memory map is a bit tricky, it contains at least one hole
1943      * from 640k-1M and possibly another one from 3.5G-4G.
1944      */
1945     next_base = 0;
1946     numa_start = table_data->len;
1947 
1948     for (i = 1; i < pcms->numa_nodes + 1; ++i) {
1949         mem_base = next_base;
1950         mem_len = pcms->node_mem[i - 1];
1951         next_base = mem_base + mem_len;
1952 
1953         /* Cut out the 640K hole */
1954         if (mem_base <= HOLE_640K_START &&
1955             next_base > HOLE_640K_START) {
1956             mem_len -= next_base - HOLE_640K_START;
1957             if (mem_len > 0) {
1958                 numamem = acpi_data_push(table_data, sizeof *numamem);
1959                 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1960                                   MEM_AFFINITY_ENABLED);
1961             }
1962 
1963             /* Check for the rare case: 640K < RAM < 1M */
1964             if (next_base <= HOLE_640K_END) {
1965                 next_base = HOLE_640K_END;
1966                 continue;
1967             }
1968             mem_base = HOLE_640K_END;
1969             mem_len = next_base - HOLE_640K_END;
1970         }
1971 
1972         /* Cut out the ACPI_PCI hole */
1973         if (mem_base <= x86ms->below_4g_mem_size &&
1974             next_base > x86ms->below_4g_mem_size) {
1975             mem_len -= next_base - x86ms->below_4g_mem_size;
1976             if (mem_len > 0) {
1977                 numamem = acpi_data_push(table_data, sizeof *numamem);
1978                 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1979                                   MEM_AFFINITY_ENABLED);
1980             }
1981             mem_base = 1ULL << 32;
1982             mem_len = next_base - x86ms->below_4g_mem_size;
1983             next_base = mem_base + mem_len;
1984         }
1985 
1986         if (mem_len > 0) {
1987             numamem = acpi_data_push(table_data, sizeof *numamem);
1988             build_srat_memory(numamem, mem_base, mem_len, i - 1,
1989                               MEM_AFFINITY_ENABLED);
1990         }
1991     }
1992 
1993     if (machine->nvdimms_state->is_enabled) {
1994         nvdimm_build_srat(table_data);
1995     }
1996 
1997     slots = (table_data->len - numa_start) / sizeof *numamem;
1998     for (; slots < pcms->numa_nodes + 2; slots++) {
1999         numamem = acpi_data_push(table_data, sizeof *numamem);
2000         build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2001     }
2002 
2003     /*
2004      * Entry is required for Windows to enable memory hotplug in OS
2005      * and for Linux to enable SWIOTLB when booted with less than
2006      * 4G of RAM. Windows works better if the entry sets proximity
2007      * to the highest NUMA node in the machine.
2008      * Memory devices may override proximity set by this entry,
2009      * providing _PXM method if necessary.
2010      */
2011     if (hotplugabble_address_space_size) {
2012         numamem = acpi_data_push(table_data, sizeof *numamem);
2013         build_srat_memory(numamem, machine->device_memory->base,
2014                           hotplugabble_address_space_size, pcms->numa_nodes - 1,
2015                           MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2016     }
2017 
2018     build_header(linker, table_data,
2019                  (void *)(table_data->data + srat_start),
2020                  "SRAT",
2021                  table_data->len - srat_start, 1, x86ms->oem_id,
2022                  x86ms->oem_table_id);
2023 }
2024 
2025 /*
2026  * VT-d spec 8.1 DMA Remapping Reporting Structure
2027  * (version Oct. 2014 or later)
2028  */
2029 static void
2030 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2031                const char *oem_table_id)
2032 {
2033     int dmar_start = table_data->len;
2034 
2035     AcpiTableDmar *dmar;
2036     AcpiDmarHardwareUnit *drhd;
2037     AcpiDmarRootPortATS *atsr;
2038     uint8_t dmar_flags = 0;
2039     X86IOMMUState *iommu = x86_iommu_get_default();
2040     AcpiDmarDeviceScope *scope = NULL;
2041     /* Root complex IOAPIC use one path[0] only */
2042     size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2043     IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2044 
2045     assert(iommu);
2046     if (x86_iommu_ir_supported(iommu)) {
2047         dmar_flags |= 0x1;      /* Flags: 0x1: INT_REMAP */
2048     }
2049 
2050     dmar = acpi_data_push(table_data, sizeof(*dmar));
2051     dmar->host_address_width = intel_iommu->aw_bits - 1;
2052     dmar->flags = dmar_flags;
2053 
2054     /* DMAR Remapping Hardware Unit Definition structure */
2055     drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2056     drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2057     drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2058     drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2059     drhd->pci_segment = cpu_to_le16(0);
2060     drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2061 
2062     /* Scope definition for the root-complex IOAPIC. See VT-d spec
2063      * 8.3.1 (version Oct. 2014 or later). */
2064     scope = &drhd->scope[0];
2065     scope->entry_type = 0x03;   /* Type: 0x03 for IOAPIC */
2066     scope->length = ioapic_scope_size;
2067     scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2068     scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2069     scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2070     scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2071 
2072     if (iommu->dt_supported) {
2073         atsr = acpi_data_push(table_data, sizeof(*atsr));
2074         atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2075         atsr->length = cpu_to_le16(sizeof(*atsr));
2076         atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2077         atsr->pci_segment = cpu_to_le16(0);
2078     }
2079 
2080     build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2081                  "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id);
2082 }
2083 
2084 /*
2085  * Windows ACPI Emulated Devices Table
2086  * (Version 1.0 - April 6, 2009)
2087  * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2088  *
2089  * Helpful to speedup Windows guests and ignored by others.
2090  */
2091 static void
2092 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2093            const char *oem_table_id)
2094 {
2095     int waet_start = table_data->len;
2096 
2097     /* WAET header */
2098     acpi_data_push(table_data, sizeof(AcpiTableHeader));
2099     /*
2100      * Set "ACPI PM timer good" flag.
2101      *
2102      * Tells Windows guests that our ACPI PM timer is reliable in the
2103      * sense that guest can read it only once to obtain a reliable value.
2104      * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2105      */
2106     build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2107 
2108     build_header(linker, table_data, (void *)(table_data->data + waet_start),
2109                  "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id);
2110 }
2111 
2112 /*
2113  *   IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2114  *   accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2115  */
2116 #define IOAPIC_SB_DEVID   (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2117 
2118 /*
2119  * Insert IVHD entry for device and recurse, insert alias, or insert range as
2120  * necessary for the PCI topology.
2121  */
2122 static void
2123 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2124 {
2125     GArray *table_data = opaque;
2126     uint32_t entry;
2127 
2128     /* "Select" IVHD entry, type 0x2 */
2129     entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2130     build_append_int_noprefix(table_data, entry, 4);
2131 
2132     if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2133         PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2134         uint8_t sec = pci_bus_num(sec_bus);
2135         uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2136 
2137         if (pci_bus_is_express(sec_bus)) {
2138             /*
2139              * Walk the bus if there are subordinates, otherwise use a range
2140              * to cover an entire leaf bus.  We could potentially also use a
2141              * range for traversed buses, but we'd need to take care not to
2142              * create both Select and Range entries covering the same device.
2143              * This is easier and potentially more compact.
2144              *
2145              * An example bare metal system seems to use Select entries for
2146              * root ports without a slot (ie. built-ins) and Range entries
2147              * when there is a slot.  The same system also only hard-codes
2148              * the alias range for an onboard PCIe-to-PCI bridge, apparently
2149              * making no effort to support nested bridges.  We attempt to
2150              * be more thorough here.
2151              */
2152             if (sec == sub) { /* leaf bus */
2153                 /* "Start of Range" IVHD entry, type 0x3 */
2154                 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2155                 build_append_int_noprefix(table_data, entry, 4);
2156                 /* "End of Range" IVHD entry, type 0x4 */
2157                 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2158                 build_append_int_noprefix(table_data, entry, 4);
2159             } else {
2160                 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2161             }
2162         } else {
2163             /*
2164              * If the secondary bus is conventional, then we need to create an
2165              * Alias range for everything downstream.  The range covers the
2166              * first devfn on the secondary bus to the last devfn on the
2167              * subordinate bus.  The alias target depends on legacy versus
2168              * express bridges, just as in pci_device_iommu_address_space().
2169              * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2170              */
2171             uint16_t dev_id_a, dev_id_b;
2172 
2173             dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2174 
2175             if (pci_is_express(dev) &&
2176                 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2177                 dev_id_b = dev_id_a;
2178             } else {
2179                 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2180             }
2181 
2182             /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2183             build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2184             build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2185 
2186             /* "End of Range" IVHD entry, type 0x4 */
2187             entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2188             build_append_int_noprefix(table_data, entry, 4);
2189         }
2190     }
2191 }
2192 
2193 /* For all PCI host bridges, walk and insert IVHD entries */
2194 static int
2195 ivrs_host_bridges(Object *obj, void *opaque)
2196 {
2197     GArray *ivhd_blob = opaque;
2198 
2199     if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2200         PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2201 
2202         if (bus) {
2203             pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
2204         }
2205     }
2206 
2207     return 0;
2208 }
2209 
2210 static void
2211 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2212                 const char *oem_table_id)
2213 {
2214     int ivhd_table_len = 24;
2215     int iommu_start = table_data->len;
2216     AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2217     GArray *ivhd_blob = g_array_new(false, true, 1);
2218 
2219     /* IVRS header */
2220     acpi_data_push(table_data, sizeof(AcpiTableHeader));
2221     /* IVinfo - IO virtualization information common to all
2222      * IOMMU units in a system
2223      */
2224     build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2225     /* reserved */
2226     build_append_int_noprefix(table_data, 0, 8);
2227 
2228     /* IVHD definition - type 10h */
2229     build_append_int_noprefix(table_data, 0x10, 1);
2230     /* virtualization flags */
2231     build_append_int_noprefix(table_data,
2232                              (1UL << 0) | /* HtTunEn      */
2233                              (1UL << 4) | /* iotblSup     */
2234                              (1UL << 6) | /* PrefSup      */
2235                              (1UL << 7),  /* PPRSup       */
2236                              1);
2237 
2238     /*
2239      * A PCI bus walk, for each PCI host bridge, is necessary to create a
2240      * complete set of IVHD entries.  Do this into a separate blob so that we
2241      * can calculate the total IVRS table length here and then append the new
2242      * blob further below.  Fall back to an entry covering all devices, which
2243      * is sufficient when no aliases are present.
2244      */
2245     object_child_foreach_recursive(object_get_root(),
2246                                    ivrs_host_bridges, ivhd_blob);
2247 
2248     if (!ivhd_blob->len) {
2249         /*
2250          *   Type 1 device entry reporting all devices
2251          *   These are 4-byte device entries currently reporting the range of
2252          *   Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2253          */
2254         build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2255     }
2256 
2257     ivhd_table_len += ivhd_blob->len;
2258 
2259     /*
2260      * When interrupt remapping is supported, we add a special IVHD device
2261      * for type IO-APIC.
2262      */
2263     if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2264         ivhd_table_len += 8;
2265     }
2266 
2267     /* IVHD length */
2268     build_append_int_noprefix(table_data, ivhd_table_len, 2);
2269     /* DeviceID */
2270     build_append_int_noprefix(table_data, s->devid, 2);
2271     /* Capability offset */
2272     build_append_int_noprefix(table_data, s->capab_offset, 2);
2273     /* IOMMU base address */
2274     build_append_int_noprefix(table_data, s->mmio.addr, 8);
2275     /* PCI Segment Group */
2276     build_append_int_noprefix(table_data, 0, 2);
2277     /* IOMMU info */
2278     build_append_int_noprefix(table_data, 0, 2);
2279     /* IOMMU Feature Reporting */
2280     build_append_int_noprefix(table_data,
2281                              (48UL << 30) | /* HATS   */
2282                              (48UL << 28) | /* GATS   */
2283                              (1UL << 2)   | /* GTSup  */
2284                              (1UL << 6),    /* GASup  */
2285                              4);
2286 
2287     /* IVHD entries as found above */
2288     g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2289     g_array_free(ivhd_blob, TRUE);
2290 
2291     /*
2292      * Add a special IVHD device type.
2293      * Refer to spec - Table 95: IVHD device entry type codes
2294      *
2295      * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2296      * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2297      */
2298     if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2299         build_append_int_noprefix(table_data,
2300                                  (0x1ull << 56) |           /* type IOAPIC */
2301                                  (IOAPIC_SB_DEVID << 40) |  /* IOAPIC devid */
2302                                  0x48,                      /* special device */
2303                                  8);
2304     }
2305 
2306     build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2307                  "IVRS", table_data->len - iommu_start, 1, oem_id,
2308                  oem_table_id);
2309 }
2310 
2311 typedef
2312 struct AcpiBuildState {
2313     /* Copy of table in RAM (for patching). */
2314     MemoryRegion *table_mr;
2315     /* Is table patched? */
2316     uint8_t patched;
2317     void *rsdp;
2318     MemoryRegion *rsdp_mr;
2319     MemoryRegion *linker_mr;
2320 } AcpiBuildState;
2321 
2322 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2323 {
2324     Object *pci_host;
2325     QObject *o;
2326 
2327     pci_host = acpi_get_i386_pci_host();
2328     if (!pci_host) {
2329         return false;
2330     }
2331 
2332     o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2333     if (!o) {
2334         return false;
2335     }
2336     mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2337     qobject_unref(o);
2338     if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2339         return false;
2340     }
2341 
2342     o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2343     assert(o);
2344     mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2345     qobject_unref(o);
2346     return true;
2347 }
2348 
2349 static
2350 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2351 {
2352     PCMachineState *pcms = PC_MACHINE(machine);
2353     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2354     X86MachineState *x86ms = X86_MACHINE(machine);
2355     GArray *table_offsets;
2356     unsigned facs, dsdt, rsdt, fadt;
2357     AcpiPmInfo pm;
2358     AcpiMiscInfo misc;
2359     AcpiMcfgInfo mcfg;
2360     Range pci_hole = {}, pci_hole64 = {};
2361     uint8_t *u;
2362     size_t aml_len = 0;
2363     GArray *tables_blob = tables->table_data;
2364     AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2365     Object *vmgenid_dev;
2366     char *oem_id;
2367     char *oem_table_id;
2368 
2369     acpi_get_pm_info(machine, &pm);
2370     acpi_get_misc_info(&misc);
2371     acpi_get_pci_holes(&pci_hole, &pci_hole64);
2372     acpi_get_slic_oem(&slic_oem);
2373 
2374     if (slic_oem.id) {
2375         oem_id = slic_oem.id;
2376     } else {
2377         oem_id = x86ms->oem_id;
2378     }
2379 
2380     if (slic_oem.table_id) {
2381         oem_table_id = slic_oem.table_id;
2382     } else {
2383         oem_table_id = x86ms->oem_table_id;
2384     }
2385 
2386     table_offsets = g_array_new(false, true /* clear */,
2387                                         sizeof(uint32_t));
2388     ACPI_BUILD_DPRINTF("init ACPI tables\n");
2389 
2390     bios_linker_loader_alloc(tables->linker,
2391                              ACPI_BUILD_TABLE_FILE, tables_blob,
2392                              64 /* Ensure FACS is aligned */,
2393                              false /* high memory */);
2394 
2395     /*
2396      * FACS is pointed to by FADT.
2397      * We place it first since it's the only table that has alignment
2398      * requirements.
2399      */
2400     facs = tables_blob->len;
2401     build_facs(tables_blob);
2402 
2403     /* DSDT is pointed to by FADT */
2404     dsdt = tables_blob->len;
2405     build_dsdt(tables_blob, tables->linker, &pm, &misc,
2406                &pci_hole, &pci_hole64, machine);
2407 
2408     /* Count the size of the DSDT and SSDT, we will need it for legacy
2409      * sizing of ACPI tables.
2410      */
2411     aml_len += tables_blob->len - dsdt;
2412 
2413     /* ACPI tables pointed to by RSDT */
2414     fadt = tables_blob->len;
2415     acpi_add_table(table_offsets, tables_blob);
2416     pm.fadt.facs_tbl_offset = &facs;
2417     pm.fadt.dsdt_tbl_offset = &dsdt;
2418     pm.fadt.xdsdt_tbl_offset = &dsdt;
2419     build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2420     aml_len += tables_blob->len - fadt;
2421 
2422     acpi_add_table(table_offsets, tables_blob);
2423     acpi_build_madt(tables_blob, tables->linker, x86ms,
2424                     ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
2425                     x86ms->oem_table_id);
2426 
2427     vmgenid_dev = find_vmgenid_dev();
2428     if (vmgenid_dev) {
2429         acpi_add_table(table_offsets, tables_blob);
2430         vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2431                            tables->vmgenid, tables->linker, x86ms->oem_id);
2432     }
2433 
2434     if (misc.has_hpet) {
2435         acpi_add_table(table_offsets, tables_blob);
2436         build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2437                    x86ms->oem_table_id);
2438     }
2439 #ifdef CONFIG_TPM
2440     if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2441         if (misc.tpm_version == TPM_VERSION_1_2) {
2442             acpi_add_table(table_offsets, tables_blob);
2443             build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2444                            x86ms->oem_id, x86ms->oem_table_id);
2445         } else { /* TPM_VERSION_2_0 */
2446             acpi_add_table(table_offsets, tables_blob);
2447             build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2448                        x86ms->oem_id, x86ms->oem_table_id);
2449         }
2450     }
2451 #endif
2452     if (pcms->numa_nodes) {
2453         acpi_add_table(table_offsets, tables_blob);
2454         build_srat(tables_blob, tables->linker, machine);
2455         if (machine->numa_state->have_numa_distance) {
2456             acpi_add_table(table_offsets, tables_blob);
2457             build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2458                        x86ms->oem_table_id);
2459         }
2460         if (machine->numa_state->hmat_enabled) {
2461             acpi_add_table(table_offsets, tables_blob);
2462             build_hmat(tables_blob, tables->linker, machine->numa_state,
2463                        x86ms->oem_id, x86ms->oem_table_id);
2464         }
2465     }
2466     if (acpi_get_mcfg(&mcfg)) {
2467         acpi_add_table(table_offsets, tables_blob);
2468         build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2469                    x86ms->oem_table_id);
2470     }
2471     if (x86_iommu_get_default()) {
2472         IommuType IOMMUType = x86_iommu_get_type();
2473         if (IOMMUType == TYPE_AMD) {
2474             acpi_add_table(table_offsets, tables_blob);
2475             build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2476                             x86ms->oem_table_id);
2477         } else if (IOMMUType == TYPE_INTEL) {
2478             acpi_add_table(table_offsets, tables_blob);
2479             build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2480                            x86ms->oem_table_id);
2481         }
2482     }
2483     if (machine->nvdimms_state->is_enabled) {
2484         nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2485                           machine->nvdimms_state, machine->ram_slots,
2486                           x86ms->oem_id, x86ms->oem_table_id);
2487     }
2488 
2489     acpi_add_table(table_offsets, tables_blob);
2490     build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2491 
2492     /* Add tables supplied by user (if any) */
2493     for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2494         unsigned len = acpi_table_len(u);
2495 
2496         acpi_add_table(table_offsets, tables_blob);
2497         g_array_append_vals(tables_blob, u, len);
2498     }
2499 
2500     /* RSDT is pointed to by RSDP */
2501     rsdt = tables_blob->len;
2502     build_rsdt(tables_blob, tables->linker, table_offsets,
2503                oem_id, oem_table_id);
2504 
2505     /* RSDP is in FSEG memory, so allocate it separately */
2506     {
2507         AcpiRsdpData rsdp_data = {
2508             .revision = 0,
2509             .oem_id = x86ms->oem_id,
2510             .xsdt_tbl_offset = NULL,
2511             .rsdt_tbl_offset = &rsdt,
2512         };
2513         build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2514         if (!pcmc->rsdp_in_ram) {
2515             /* We used to allocate some extra space for RSDP revision 2 but
2516              * only used the RSDP revision 0 space. The extra bytes were
2517              * zeroed out and not used.
2518              * Here we continue wasting those extra 16 bytes to make sure we
2519              * don't break migration for machine types 2.2 and older due to
2520              * RSDP blob size mismatch.
2521              */
2522             build_append_int_noprefix(tables->rsdp, 0, 16);
2523         }
2524     }
2525 
2526     /* We'll expose it all to Guest so we want to reduce
2527      * chance of size changes.
2528      *
2529      * We used to align the tables to 4k, but of course this would
2530      * too simple to be enough.  4k turned out to be too small an
2531      * alignment very soon, and in fact it is almost impossible to
2532      * keep the table size stable for all (max_cpus, max_memory_slots)
2533      * combinations.  So the table size is always 64k for pc-i440fx-2.1
2534      * and we give an error if the table grows beyond that limit.
2535      *
2536      * We still have the problem of migrating from "-M pc-i440fx-2.0".  For
2537      * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2538      * than 2.0 and we can always pad the smaller tables with zeros.  We can
2539      * then use the exact size of the 2.0 tables.
2540      *
2541      * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2542      */
2543     if (pcmc->legacy_acpi_table_size) {
2544         /* Subtracting aml_len gives the size of fixed tables.  Then add the
2545          * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2546          */
2547         int legacy_aml_len =
2548             pcmc->legacy_acpi_table_size +
2549             ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2550         int legacy_table_size =
2551             ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2552                      ACPI_BUILD_ALIGN_SIZE);
2553         if (tables_blob->len > legacy_table_size) {
2554             /* Should happen only with PCI bridges and -M pc-i440fx-2.0.  */
2555             warn_report("ACPI table size %u exceeds %d bytes,"
2556                         " migration may not work",
2557                         tables_blob->len, legacy_table_size);
2558             error_printf("Try removing CPUs, NUMA nodes, memory slots"
2559                          " or PCI bridges.");
2560         }
2561         g_array_set_size(tables_blob, legacy_table_size);
2562     } else {
2563         /* Make sure we have a buffer in case we need to resize the tables. */
2564         if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2565             /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots.  */
2566             warn_report("ACPI table size %u exceeds %d bytes,"
2567                         " migration may not work",
2568                         tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2569             error_printf("Try removing CPUs, NUMA nodes, memory slots"
2570                          " or PCI bridges.");
2571         }
2572         acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2573     }
2574 
2575     acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2576 
2577     /* Cleanup memory that's no longer used. */
2578     g_array_free(table_offsets, true);
2579 }
2580 
2581 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2582 {
2583     uint32_t size = acpi_data_len(data);
2584 
2585     /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2586     memory_region_ram_resize(mr, size, &error_abort);
2587 
2588     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2589     memory_region_set_dirty(mr, 0, size);
2590 }
2591 
2592 static void acpi_build_update(void *build_opaque)
2593 {
2594     AcpiBuildState *build_state = build_opaque;
2595     AcpiBuildTables tables;
2596 
2597     /* No state to update or already patched? Nothing to do. */
2598     if (!build_state || build_state->patched) {
2599         return;
2600     }
2601     build_state->patched = 1;
2602 
2603     acpi_build_tables_init(&tables);
2604 
2605     acpi_build(&tables, MACHINE(qdev_get_machine()));
2606 
2607     acpi_ram_update(build_state->table_mr, tables.table_data);
2608 
2609     if (build_state->rsdp) {
2610         memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2611     } else {
2612         acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2613     }
2614 
2615     acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2616     acpi_build_tables_cleanup(&tables, true);
2617 }
2618 
2619 static void acpi_build_reset(void *build_opaque)
2620 {
2621     AcpiBuildState *build_state = build_opaque;
2622     build_state->patched = 0;
2623 }
2624 
2625 static const VMStateDescription vmstate_acpi_build = {
2626     .name = "acpi_build",
2627     .version_id = 1,
2628     .minimum_version_id = 1,
2629     .fields = (VMStateField[]) {
2630         VMSTATE_UINT8(patched, AcpiBuildState),
2631         VMSTATE_END_OF_LIST()
2632     },
2633 };
2634 
2635 void acpi_setup(void)
2636 {
2637     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2638     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2639     X86MachineState *x86ms = X86_MACHINE(pcms);
2640     AcpiBuildTables tables;
2641     AcpiBuildState *build_state;
2642     Object *vmgenid_dev;
2643 #ifdef CONFIG_TPM
2644     TPMIf *tpm;
2645     static FwCfgTPMConfig tpm_config;
2646 #endif
2647 
2648     if (!x86ms->fw_cfg) {
2649         ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2650         return;
2651     }
2652 
2653     if (!pcms->acpi_build_enabled) {
2654         ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2655         return;
2656     }
2657 
2658     if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2659         ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2660         return;
2661     }
2662 
2663     build_state = g_malloc0(sizeof *build_state);
2664 
2665     acpi_build_tables_init(&tables);
2666     acpi_build(&tables, MACHINE(pcms));
2667 
2668     /* Now expose it all to Guest */
2669     build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2670                                               build_state, tables.table_data,
2671                                               ACPI_BUILD_TABLE_FILE);
2672     assert(build_state->table_mr != NULL);
2673 
2674     build_state->linker_mr =
2675         acpi_add_rom_blob(acpi_build_update, build_state,
2676                           tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2677 
2678 #ifdef CONFIG_TPM
2679     fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2680                     tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2681 
2682     tpm = tpm_find();
2683     if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2684         tpm_config = (FwCfgTPMConfig) {
2685             .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2686             .tpm_version = tpm_get_version(tpm),
2687             .tpmppi_version = TPM_PPI_VERSION_1_30
2688         };
2689         fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2690                         &tpm_config, sizeof tpm_config);
2691     }
2692 #endif
2693 
2694     vmgenid_dev = find_vmgenid_dev();
2695     if (vmgenid_dev) {
2696         vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2697                            tables.vmgenid);
2698     }
2699 
2700     if (!pcmc->rsdp_in_ram) {
2701         /*
2702          * Keep for compatibility with old machine types.
2703          * Though RSDP is small, its contents isn't immutable, so
2704          * we'll update it along with the rest of tables on guest access.
2705          */
2706         uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2707 
2708         build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2709         fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2710                                  acpi_build_update, NULL, build_state,
2711                                  build_state->rsdp, rsdp_size, true);
2712         build_state->rsdp_mr = NULL;
2713     } else {
2714         build_state->rsdp = NULL;
2715         build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2716                                                  build_state, tables.rsdp,
2717                                                  ACPI_BUILD_RSDP_FILE);
2718     }
2719 
2720     qemu_register_reset(acpi_build_reset, build_state);
2721     acpi_build_reset(build_state);
2722     vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2723 
2724     /* Cleanup tables but don't free the memory: we track it
2725      * in build_state.
2726      */
2727     acpi_build_tables_cleanup(&tables, false);
2728 }
2729