1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci.h" 31 #include "hw/core/cpu.h" 32 #include "target/i386/cpu.h" 33 #include "hw/misc/pvpanic.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/isa/isa.h" 41 #include "hw/input/i8042.h" 42 #include "hw/block/fdc.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "sysemu/tpm.h" 45 #include "hw/acpi/tpm.h" 46 #include "hw/acpi/vmgenid.h" 47 #include "hw/acpi/erst.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/piix.h" 59 #include "hw/acpi/pcihp.h" 60 #include "hw/i386/fw_cfg.h" 61 #include "hw/i386/ich9.h" 62 #include "hw/pci/pci_bus.h" 63 #include "hw/pci-host/q35.h" 64 #include "hw/i386/x86-iommu.h" 65 66 #include "hw/acpi/aml-build.h" 67 #include "hw/acpi/utils.h" 68 #include "hw/acpi/pci.h" 69 70 #include "qom/qom-qobject.h" 71 #include "hw/i386/amd_iommu.h" 72 #include "hw/i386/intel_iommu.h" 73 #include "hw/virtio/virtio-iommu.h" 74 75 #include "hw/acpi/ipmi.h" 76 #include "hw/acpi/hmat.h" 77 #include "hw/acpi/viot.h" 78 79 #include CONFIG_DEVICES 80 81 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 82 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 83 * a little bit, there should be plenty of free space since the DSDT 84 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 85 */ 86 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 87 #define ACPI_BUILD_ALIGN_SIZE 0x1000 88 89 #define ACPI_BUILD_TABLE_SIZE 0x20000 90 91 /* #define DEBUG_ACPI_BUILD */ 92 #ifdef DEBUG_ACPI_BUILD 93 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 94 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 95 #else 96 #define ACPI_BUILD_DPRINTF(fmt, ...) 97 #endif 98 99 typedef struct AcpiPmInfo { 100 bool s3_disabled; 101 bool s4_disabled; 102 bool pcihp_bridge_en; 103 bool smi_on_cpuhp; 104 bool smi_on_cpu_unplug; 105 bool pcihp_root_en; 106 uint8_t s4_val; 107 AcpiFadtData fadt; 108 uint16_t cpu_hp_io_base; 109 uint16_t pcihp_io_base; 110 uint16_t pcihp_io_len; 111 } AcpiPmInfo; 112 113 typedef struct AcpiMiscInfo { 114 bool is_piix4; 115 bool has_hpet; 116 #ifdef CONFIG_TPM 117 TPMVersion tpm_version; 118 #endif 119 const unsigned char *dsdt_code; 120 unsigned dsdt_size; 121 uint16_t pvpanic_port; 122 uint16_t applesmc_io_base; 123 } AcpiMiscInfo; 124 125 typedef struct AcpiBuildPciBusHotplugState { 126 GArray *device_table; 127 GArray *notify_table; 128 struct AcpiBuildPciBusHotplugState *parent; 129 bool pcihp_bridge_en; 130 } AcpiBuildPciBusHotplugState; 131 132 typedef struct FwCfgTPMConfig { 133 uint32_t tpmppi_address; 134 uint8_t tpm_version; 135 uint8_t tpmppi_version; 136 } QEMU_PACKED FwCfgTPMConfig; 137 138 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 139 140 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 141 .space_id = AML_AS_SYSTEM_IO, 142 .address = NVDIMM_ACPI_IO_BASE, 143 .bit_width = NVDIMM_ACPI_IO_LEN << 3 144 }; 145 146 static void init_common_fadt_data(MachineState *ms, Object *o, 147 AcpiFadtData *data) 148 { 149 X86MachineState *x86ms = X86_MACHINE(ms); 150 /* 151 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 152 * behavior for compatibility irrelevant to smm_enabled, which doesn't 153 * comforms to ACPI spec. 154 */ 155 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 156 true : x86_machine_is_smm_enabled(x86ms); 157 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 158 AmlAddressSpace as = AML_AS_SYSTEM_IO; 159 AcpiFadtData fadt = { 160 .rev = 3, 161 .flags = 162 (1 << ACPI_FADT_F_WBINVD) | 163 (1 << ACPI_FADT_F_PROC_C1) | 164 (1 << ACPI_FADT_F_SLP_BUTTON) | 165 (1 << ACPI_FADT_F_RTC_S4) | 166 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 167 /* APIC destination mode ("Flat Logical") has an upper limit of 8 168 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 169 * used 170 */ 171 ((ms->smp.max_cpus > 8) ? 172 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 173 .int_model = 1 /* Multiple APIC */, 174 .rtc_century = RTC_CENTURY, 175 .plvl2_lat = 0xfff /* C2 state not supported */, 176 .plvl3_lat = 0xfff /* C3 state not supported */, 177 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 178 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 179 .acpi_enable_cmd = 180 smm_enabled ? 181 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 182 0, 183 .acpi_disable_cmd = 184 smm_enabled ? 185 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 186 0, 187 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 188 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 189 .address = io + 0x04 }, 190 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 191 .gpe0_blk = { .space_id = as, .bit_width = 192 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 193 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 194 }, 195 }; 196 197 /* 198 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 199 * Flags, bit offset 1 - 8042. 200 */ 201 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 202 203 *data = fadt; 204 } 205 206 static Object *object_resolve_type_unambiguous(const char *typename) 207 { 208 bool ambig; 209 Object *o = object_resolve_path_type("", typename, &ambig); 210 211 if (ambig || !o) { 212 return NULL; 213 } 214 return o; 215 } 216 217 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 218 { 219 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 220 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 221 Object *obj = piix ? piix : lpc; 222 QObject *o; 223 pm->cpu_hp_io_base = 0; 224 pm->pcihp_io_base = 0; 225 pm->pcihp_io_len = 0; 226 pm->smi_on_cpuhp = false; 227 pm->smi_on_cpu_unplug = false; 228 229 assert(obj); 230 init_common_fadt_data(machine, obj, &pm->fadt); 231 if (piix) { 232 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 233 pm->fadt.rev = 1; 234 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 235 } 236 if (lpc) { 237 uint64_t smi_features = object_property_get_uint(lpc, 238 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 239 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 240 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 241 pm->fadt.reset_reg = r; 242 pm->fadt.reset_val = 0xf; 243 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 244 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 245 pm->smi_on_cpuhp = 246 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 247 pm->smi_on_cpu_unplug = 248 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 249 } 250 pm->pcihp_io_base = 251 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 252 pm->pcihp_io_len = 253 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 254 255 /* The above need not be conditional on machine type because the reset port 256 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 257 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 258 259 /* Fill in optional s3/s4 related properties */ 260 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 261 if (o) { 262 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 263 } else { 264 pm->s3_disabled = false; 265 } 266 qobject_unref(o); 267 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 268 if (o) { 269 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 270 } else { 271 pm->s4_disabled = false; 272 } 273 qobject_unref(o); 274 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 275 if (o) { 276 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 277 } else { 278 pm->s4_val = false; 279 } 280 qobject_unref(o); 281 282 pm->pcihp_bridge_en = 283 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 284 NULL); 285 pm->pcihp_root_en = 286 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 287 NULL); 288 } 289 290 static void acpi_get_misc_info(AcpiMiscInfo *info) 291 { 292 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 293 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 294 assert(!!piix != !!lpc); 295 296 if (piix) { 297 info->is_piix4 = true; 298 } 299 if (lpc) { 300 info->is_piix4 = false; 301 } 302 303 info->has_hpet = hpet_find(); 304 #ifdef CONFIG_TPM 305 info->tpm_version = tpm_get_version(tpm_find()); 306 #endif 307 info->pvpanic_port = pvpanic_port(); 308 info->applesmc_io_base = applesmc_port(); 309 } 310 311 /* 312 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 313 * On i386 arch we only have two pci hosts, so we can look only for them. 314 */ 315 Object *acpi_get_i386_pci_host(void) 316 { 317 PCIHostState *host; 318 319 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 320 if (!host) { 321 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 322 } 323 324 return OBJECT(host); 325 } 326 327 static void acpi_get_pci_holes(Range *hole, Range *hole64) 328 { 329 Object *pci_host; 330 331 pci_host = acpi_get_i386_pci_host(); 332 333 if (!pci_host) { 334 return; 335 } 336 337 range_set_bounds1(hole, 338 object_property_get_uint(pci_host, 339 PCI_HOST_PROP_PCI_HOLE_START, 340 NULL), 341 object_property_get_uint(pci_host, 342 PCI_HOST_PROP_PCI_HOLE_END, 343 NULL)); 344 range_set_bounds1(hole64, 345 object_property_get_uint(pci_host, 346 PCI_HOST_PROP_PCI_HOLE64_START, 347 NULL), 348 object_property_get_uint(pci_host, 349 PCI_HOST_PROP_PCI_HOLE64_END, 350 NULL)); 351 } 352 353 static void acpi_align_size(GArray *blob, unsigned align) 354 { 355 /* Align size to multiple of given size. This reduces the chance 356 * we need to change size in the future (breaking cross version migration). 357 */ 358 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 359 } 360 361 /* 362 * ACPI spec 1.0b, 363 * 5.2.6 Firmware ACPI Control Structure 364 */ 365 static void 366 build_facs(GArray *table_data) 367 { 368 const char *sig = "FACS"; 369 const uint8_t reserved[40] = {}; 370 371 g_array_append_vals(table_data, sig, 4); /* Signature */ 372 build_append_int_noprefix(table_data, 64, 4); /* Length */ 373 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 374 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 375 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 376 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 377 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 378 } 379 380 static void build_append_pcihp_notify_entry(Aml *method, int slot) 381 { 382 Aml *if_ctx; 383 int32_t devfn = PCI_DEVFN(slot, 0); 384 385 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 386 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 387 aml_append(method, if_ctx); 388 } 389 390 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 391 bool pcihp_bridge_en) 392 { 393 Aml *dev, *notify_method = NULL, *method; 394 QObject *bsel; 395 PCIBus *sec; 396 int devfn; 397 398 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 399 if (bsel) { 400 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 401 402 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 403 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 404 } 405 406 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 407 DeviceClass *dc; 408 PCIDeviceClass *pc; 409 PCIDevice *pdev = bus->devices[devfn]; 410 int slot = PCI_SLOT(devfn); 411 int func = PCI_FUNC(devfn); 412 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 413 int adr = slot << 16 | func; 414 bool hotplug_enabled_dev; 415 bool bridge_in_acpi; 416 bool cold_plugged_bridge; 417 418 if (!pdev) { 419 /* 420 * add hotplug slots for non present devices. 421 * hotplug is supported only for non-multifunction device 422 * so generate device description only for function 0 423 */ 424 if (bsel && !func) { 425 if (pci_bus_is_express(bus) && slot > 0) { 426 break; 427 } 428 dev = aml_device("S%.02X", devfn); 429 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 430 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 431 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 432 aml_append(method, 433 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 434 ); 435 aml_append(dev, method); 436 method = aml_method("_DSM", 4, AML_SERIALIZED); 437 aml_append(method, 438 aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1), 439 aml_arg(2), aml_arg(3), 440 aml_name("BSEL"), aml_name("_SUN"))) 441 ); 442 aml_append(dev, method); 443 aml_append(parent_scope, dev); 444 445 build_append_pcihp_notify_entry(notify_method, slot); 446 } 447 continue; 448 } 449 450 pc = PCI_DEVICE_GET_CLASS(pdev); 451 dc = DEVICE_GET_CLASS(pdev); 452 453 /* 454 * Cold plugged bridges aren't themselves hot-pluggable. 455 * Hotplugged bridges *are* hot-pluggable. 456 */ 457 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; 458 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; 459 460 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; 461 462 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 463 continue; 464 } 465 466 /* 467 * allow describing coldplugged bridges in ACPI even if they are not 468 * on function 0, as they are not unpluggable, for all other devices 469 * generate description only for function 0 per slot 470 */ 471 if (func && !bridge_in_acpi) { 472 continue; 473 } 474 475 /* start to compose PCI device descriptor */ 476 dev = aml_device("S%.02X", devfn); 477 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 478 479 if (bsel) { 480 /* 481 * Can't declare _SUN here for every device as it changes 'slot' 482 * enumeration order in linux kernel, so use another variable for it 483 */ 484 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 485 method = aml_method("_DSM", 4, AML_SERIALIZED); 486 aml_append(method, aml_return( 487 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2), 488 aml_arg(3), aml_name("BSEL"), aml_name("ASUN")) 489 )); 490 aml_append(dev, method); 491 } 492 493 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 494 /* add VGA specific AML methods */ 495 int s3d; 496 497 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 498 s3d = 3; 499 } else { 500 s3d = 0; 501 } 502 503 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 504 aml_append(method, aml_return(aml_int(0))); 505 aml_append(dev, method); 506 507 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 508 aml_append(method, aml_return(aml_int(0))); 509 aml_append(dev, method); 510 511 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 512 aml_append(method, aml_return(aml_int(s3d))); 513 aml_append(dev, method); 514 } else if (hotplug_enabled_dev) { 515 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 516 /* add _EJ0 to make slot hotpluggable */ 517 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 518 aml_append(method, 519 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 520 ); 521 aml_append(dev, method); 522 523 if (bsel) { 524 build_append_pcihp_notify_entry(notify_method, slot); 525 } 526 } else if (bridge_in_acpi) { 527 /* 528 * device is coldplugged bridge, 529 * add child device descriptions into its scope 530 */ 531 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 532 533 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 534 } 535 /* device descriptor has been composed, add it into parent context */ 536 aml_append(parent_scope, dev); 537 } 538 539 if (bsel) { 540 aml_append(parent_scope, notify_method); 541 } 542 543 /* Append PCNT method to notify about events on local and child buses. 544 * Add this method for root bus only when hotplug is enabled since DSDT 545 * expects it. 546 */ 547 if (bsel || pcihp_bridge_en) { 548 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 549 550 /* If bus supports hotplug select it and notify about local events */ 551 if (bsel) { 552 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 553 554 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 555 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 556 aml_int(1))); /* Device Check */ 557 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 558 aml_int(3))); /* Eject Request */ 559 } 560 561 /* Notify about child bus events in any case */ 562 if (pcihp_bridge_en) { 563 QLIST_FOREACH(sec, &bus->child, sibling) { 564 if (pci_bus_is_root(sec)) { 565 continue; 566 } 567 568 aml_append(method, aml_name("^S%.02X.PCNT", 569 sec->parent_dev->devfn)); 570 } 571 } 572 573 aml_append(parent_scope, method); 574 } 575 qobject_unref(bsel); 576 } 577 578 Aml *aml_pci_device_dsm(void) 579 { 580 Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx; 581 Aml *acpi_index = aml_local(0); 582 Aml *zero = aml_int(0); 583 Aml *bnum = aml_arg(4); 584 Aml *func = aml_arg(2); 585 Aml *rev = aml_arg(1); 586 Aml *sunum = aml_arg(5); 587 588 method = aml_method("PDSM", 6, AML_SERIALIZED); 589 590 /* 591 * PCI Firmware Specification 3.1 592 * 4.6. _DSM Definitions for PCI 593 */ 594 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 595 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 596 { 597 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 598 ifctx1 = aml_if(aml_equal(func, zero)); 599 { 600 uint8_t byte_list[1]; 601 602 ifctx2 = aml_if(aml_equal(rev, aml_int(2))); 603 { 604 /* 605 * advertise function 7 if device has acpi-index 606 * acpi_index values: 607 * 0: not present (default value) 608 * FFFFFFFF: not supported (old QEMU without PIDX reg) 609 * other: device's acpi-index 610 */ 611 ifctx3 = aml_if(aml_lnot( 612 aml_or(aml_equal(acpi_index, zero), 613 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 614 )); 615 { 616 byte_list[0] = 617 1 /* have supported functions */ | 618 1 << 7 /* support for function 7 */ 619 ; 620 aml_append(ifctx3, aml_return(aml_buffer(1, byte_list))); 621 } 622 aml_append(ifctx2, ifctx3); 623 } 624 aml_append(ifctx1, ifctx2); 625 626 byte_list[0] = 0; /* nothing supported */ 627 aml_append(ifctx1, aml_return(aml_buffer(1, byte_list))); 628 } 629 aml_append(ifctx, ifctx1); 630 elsectx = aml_else(); 631 /* 632 * PCI Firmware Specification 3.1 633 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 634 * Operating Systems 635 */ 636 ifctx1 = aml_if(aml_equal(func, aml_int(7))); 637 { 638 Aml *pkg = aml_package(2); 639 Aml *ret = aml_local(1); 640 641 aml_append(pkg, zero); 642 /* 643 * optional, if not impl. should return null string 644 */ 645 aml_append(pkg, aml_string("%s", "")); 646 aml_append(ifctx1, aml_store(pkg, ret)); 647 /* 648 * update acpi-index to actual value 649 */ 650 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); 651 aml_append(ifctx1, aml_return(ret)); 652 } 653 aml_append(elsectx, ifctx1); 654 aml_append(ifctx, elsectx); 655 } 656 aml_append(method, ifctx); 657 return method; 658 } 659 660 /** 661 * build_prt_entry: 662 * @link_name: link name for PCI route entry 663 * 664 * build AML package containing a PCI route entry for @link_name 665 */ 666 static Aml *build_prt_entry(const char *link_name) 667 { 668 Aml *a_zero = aml_int(0); 669 Aml *pkg = aml_package(4); 670 aml_append(pkg, a_zero); 671 aml_append(pkg, a_zero); 672 aml_append(pkg, aml_name("%s", link_name)); 673 aml_append(pkg, a_zero); 674 return pkg; 675 } 676 677 /* 678 * initialize_route - Initialize the interrupt routing rule 679 * through a specific LINK: 680 * if (lnk_idx == idx) 681 * route using link 'link_name' 682 */ 683 static Aml *initialize_route(Aml *route, const char *link_name, 684 Aml *lnk_idx, int idx) 685 { 686 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 687 Aml *pkg = build_prt_entry(link_name); 688 689 aml_append(if_ctx, aml_store(pkg, route)); 690 691 return if_ctx; 692 } 693 694 /* 695 * build_prt - Define interrupt rounting rules 696 * 697 * Returns an array of 128 routes, one for each device, 698 * based on device location. 699 * The main goal is to equaly distribute the interrupts 700 * over the 4 existing ACPI links (works only for i440fx). 701 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 702 * 703 */ 704 static Aml *build_prt(bool is_pci0_prt) 705 { 706 Aml *method, *while_ctx, *pin, *res; 707 708 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 709 res = aml_local(0); 710 pin = aml_local(1); 711 aml_append(method, aml_store(aml_package(128), res)); 712 aml_append(method, aml_store(aml_int(0), pin)); 713 714 /* while (pin < 128) */ 715 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 716 { 717 Aml *slot = aml_local(2); 718 Aml *lnk_idx = aml_local(3); 719 Aml *route = aml_local(4); 720 721 /* slot = pin >> 2 */ 722 aml_append(while_ctx, 723 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 724 /* lnk_idx = (slot + pin) & 3 */ 725 aml_append(while_ctx, 726 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 727 lnk_idx)); 728 729 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 730 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 731 if (is_pci0_prt) { 732 Aml *if_device_1, *if_pin_4, *else_pin_4; 733 734 /* device 1 is the power-management device, needs SCI */ 735 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 736 { 737 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 738 { 739 aml_append(if_pin_4, 740 aml_store(build_prt_entry("LNKS"), route)); 741 } 742 aml_append(if_device_1, if_pin_4); 743 else_pin_4 = aml_else(); 744 { 745 aml_append(else_pin_4, 746 aml_store(build_prt_entry("LNKA"), route)); 747 } 748 aml_append(if_device_1, else_pin_4); 749 } 750 aml_append(while_ctx, if_device_1); 751 } else { 752 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 753 } 754 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 755 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 756 757 /* route[0] = 0x[slot]FFFF */ 758 aml_append(while_ctx, 759 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 760 NULL), 761 aml_index(route, aml_int(0)))); 762 /* route[1] = pin & 3 */ 763 aml_append(while_ctx, 764 aml_store(aml_and(pin, aml_int(3), NULL), 765 aml_index(route, aml_int(1)))); 766 /* res[pin] = route */ 767 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 768 /* pin++ */ 769 aml_append(while_ctx, aml_increment(pin)); 770 } 771 aml_append(method, while_ctx); 772 /* return res*/ 773 aml_append(method, aml_return(res)); 774 775 return method; 776 } 777 778 static void build_hpet_aml(Aml *table) 779 { 780 Aml *crs; 781 Aml *field; 782 Aml *method; 783 Aml *if_ctx; 784 Aml *scope = aml_scope("_SB"); 785 Aml *dev = aml_device("HPET"); 786 Aml *zero = aml_int(0); 787 Aml *id = aml_local(0); 788 Aml *period = aml_local(1); 789 790 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 791 aml_append(dev, aml_name_decl("_UID", zero)); 792 793 aml_append(dev, 794 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 795 HPET_LEN)); 796 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 797 aml_append(field, aml_named_field("VEND", 32)); 798 aml_append(field, aml_named_field("PRD", 32)); 799 aml_append(dev, field); 800 801 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 802 aml_append(method, aml_store(aml_name("VEND"), id)); 803 aml_append(method, aml_store(aml_name("PRD"), period)); 804 aml_append(method, aml_shiftright(id, aml_int(16), id)); 805 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 806 aml_equal(id, aml_int(0xffff)))); 807 { 808 aml_append(if_ctx, aml_return(zero)); 809 } 810 aml_append(method, if_ctx); 811 812 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 813 aml_lgreater(period, aml_int(100000000)))); 814 { 815 aml_append(if_ctx, aml_return(zero)); 816 } 817 aml_append(method, if_ctx); 818 819 aml_append(method, aml_return(aml_int(0x0F))); 820 aml_append(dev, method); 821 822 crs = aml_resource_template(); 823 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 824 aml_append(dev, aml_name_decl("_CRS", crs)); 825 826 aml_append(scope, dev); 827 aml_append(table, scope); 828 } 829 830 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 831 { 832 Aml *dev; 833 Aml *method; 834 Aml *crs; 835 836 dev = aml_device("VMBS"); 837 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 838 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 839 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 840 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 841 842 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 843 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 844 aml_name("STA"))); 845 aml_append(dev, method); 846 847 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 848 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 849 aml_name("STA"))); 850 aml_append(dev, method); 851 852 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 853 aml_append(method, aml_return(aml_name("STA"))); 854 aml_append(dev, method); 855 856 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 857 858 crs = aml_resource_template(); 859 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 860 aml_append(dev, aml_name_decl("_CRS", crs)); 861 862 return dev; 863 } 864 865 static void build_isa_devices_aml(Aml *table) 866 { 867 bool ambiguous; 868 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 869 Aml *scope; 870 871 assert(obj && !ambiguous); 872 873 scope = aml_scope("_SB.PCI0.ISA"); 874 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA"); 875 isa_build_aml(ISA_BUS(obj), scope); 876 877 aml_append(table, scope); 878 } 879 880 static void build_dbg_aml(Aml *table) 881 { 882 Aml *field; 883 Aml *method; 884 Aml *while_ctx; 885 Aml *scope = aml_scope("\\"); 886 Aml *buf = aml_local(0); 887 Aml *len = aml_local(1); 888 Aml *idx = aml_local(2); 889 890 aml_append(scope, 891 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 892 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 893 aml_append(field, aml_named_field("DBGB", 8)); 894 aml_append(scope, field); 895 896 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 897 898 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 899 aml_append(method, aml_to_buffer(buf, buf)); 900 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 901 aml_append(method, aml_store(aml_int(0), idx)); 902 903 while_ctx = aml_while(aml_lless(idx, len)); 904 aml_append(while_ctx, 905 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 906 aml_append(while_ctx, aml_increment(idx)); 907 aml_append(method, while_ctx); 908 909 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 910 aml_append(scope, method); 911 912 aml_append(table, scope); 913 } 914 915 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 916 { 917 Aml *dev; 918 Aml *crs; 919 Aml *method; 920 uint32_t irqs[] = {5, 10, 11}; 921 922 dev = aml_device("%s", name); 923 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 924 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 925 926 crs = aml_resource_template(); 927 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 928 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 929 aml_append(dev, aml_name_decl("_PRS", crs)); 930 931 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 932 aml_append(method, aml_return(aml_call1("IQST", reg))); 933 aml_append(dev, method); 934 935 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 936 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 937 aml_append(dev, method); 938 939 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 940 aml_append(method, aml_return(aml_call1("IQCR", reg))); 941 aml_append(dev, method); 942 943 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 944 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 945 aml_append(method, aml_store(aml_name("PRRI"), reg)); 946 aml_append(dev, method); 947 948 return dev; 949 } 950 951 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 952 { 953 Aml *dev; 954 Aml *crs; 955 Aml *method; 956 uint32_t irqs; 957 958 dev = aml_device("%s", name); 959 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 960 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 961 962 crs = aml_resource_template(); 963 irqs = gsi; 964 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 965 AML_SHARED, &irqs, 1)); 966 aml_append(dev, aml_name_decl("_PRS", crs)); 967 968 aml_append(dev, aml_name_decl("_CRS", crs)); 969 970 /* 971 * _DIS can be no-op because the interrupt cannot be disabled. 972 */ 973 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 974 aml_append(dev, method); 975 976 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 977 aml_append(dev, method); 978 979 return dev; 980 } 981 982 /* _CRS method - get current settings */ 983 static Aml *build_iqcr_method(bool is_piix4) 984 { 985 Aml *if_ctx; 986 uint32_t irqs; 987 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 988 Aml *crs = aml_resource_template(); 989 990 irqs = 0; 991 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 992 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 993 aml_append(method, aml_name_decl("PRR0", crs)); 994 995 aml_append(method, 996 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 997 998 if (is_piix4) { 999 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1000 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1001 aml_append(method, if_ctx); 1002 } else { 1003 aml_append(method, 1004 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1005 aml_name("PRRI"))); 1006 } 1007 1008 aml_append(method, aml_return(aml_name("PRR0"))); 1009 return method; 1010 } 1011 1012 /* _STA method - get status */ 1013 static Aml *build_irq_status_method(void) 1014 { 1015 Aml *if_ctx; 1016 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1017 1018 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1019 aml_append(if_ctx, aml_return(aml_int(0x09))); 1020 aml_append(method, if_ctx); 1021 aml_append(method, aml_return(aml_int(0x0B))); 1022 return method; 1023 } 1024 1025 static void build_piix4_pci0_int(Aml *table) 1026 { 1027 Aml *dev; 1028 Aml *crs; 1029 Aml *field; 1030 Aml *method; 1031 uint32_t irqs; 1032 Aml *sb_scope = aml_scope("_SB"); 1033 Aml *pci0_scope = aml_scope("PCI0"); 1034 1035 aml_append(pci0_scope, build_prt(true)); 1036 aml_append(sb_scope, pci0_scope); 1037 1038 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1039 aml_append(field, aml_named_field("PRQ0", 8)); 1040 aml_append(field, aml_named_field("PRQ1", 8)); 1041 aml_append(field, aml_named_field("PRQ2", 8)); 1042 aml_append(field, aml_named_field("PRQ3", 8)); 1043 aml_append(sb_scope, field); 1044 1045 aml_append(sb_scope, build_irq_status_method()); 1046 aml_append(sb_scope, build_iqcr_method(true)); 1047 1048 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1049 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1050 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1051 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1052 1053 dev = aml_device("LNKS"); 1054 { 1055 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1056 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1057 1058 crs = aml_resource_template(); 1059 irqs = 9; 1060 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1061 AML_ACTIVE_HIGH, AML_SHARED, 1062 &irqs, 1)); 1063 aml_append(dev, aml_name_decl("_PRS", crs)); 1064 1065 /* The SCI cannot be disabled and is always attached to GSI 9, 1066 * so these are no-ops. We only need this link to override the 1067 * polarity to active high and match the content of the MADT. 1068 */ 1069 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1070 aml_append(method, aml_return(aml_int(0x0b))); 1071 aml_append(dev, method); 1072 1073 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1074 aml_append(dev, method); 1075 1076 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1077 aml_append(method, aml_return(aml_name("_PRS"))); 1078 aml_append(dev, method); 1079 1080 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1081 aml_append(dev, method); 1082 } 1083 aml_append(sb_scope, dev); 1084 1085 aml_append(table, sb_scope); 1086 } 1087 1088 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1089 { 1090 int i; 1091 int head; 1092 Aml *pkg; 1093 char base = name[3] < 'E' ? 'A' : 'E'; 1094 char *s = g_strdup(name); 1095 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1096 1097 assert(strlen(s) == 4); 1098 1099 head = name[3] - base; 1100 for (i = 0; i < 4; i++) { 1101 if (head + i > 3) { 1102 head = i * -1; 1103 } 1104 s[3] = base + head + i; 1105 pkg = aml_package(4); 1106 aml_append(pkg, a_nr); 1107 aml_append(pkg, aml_int(i)); 1108 aml_append(pkg, aml_name("%s", s)); 1109 aml_append(pkg, aml_int(0)); 1110 aml_append(ctx, pkg); 1111 } 1112 g_free(s); 1113 } 1114 1115 static Aml *build_q35_routing_table(const char *str) 1116 { 1117 int i; 1118 Aml *pkg; 1119 char *name = g_strdup_printf("%s ", str); 1120 1121 pkg = aml_package(128); 1122 for (i = 0; i < 0x18; i++) { 1123 name[3] = 'E' + (i & 0x3); 1124 append_q35_prt_entry(pkg, i, name); 1125 } 1126 1127 name[3] = 'E'; 1128 append_q35_prt_entry(pkg, 0x18, name); 1129 1130 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1131 for (i = 0x0019; i < 0x1e; i++) { 1132 name[3] = 'A'; 1133 append_q35_prt_entry(pkg, i, name); 1134 } 1135 1136 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1137 name[3] = 'E'; 1138 append_q35_prt_entry(pkg, 0x1e, name); 1139 name[3] = 'A'; 1140 append_q35_prt_entry(pkg, 0x1f, name); 1141 1142 g_free(name); 1143 return pkg; 1144 } 1145 1146 static void build_q35_pci0_int(Aml *table) 1147 { 1148 Aml *field; 1149 Aml *method; 1150 Aml *sb_scope = aml_scope("_SB"); 1151 Aml *pci0_scope = aml_scope("PCI0"); 1152 1153 /* Zero => PIC mode, One => APIC Mode */ 1154 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1155 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1156 { 1157 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1158 } 1159 aml_append(table, method); 1160 1161 aml_append(pci0_scope, 1162 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1163 aml_append(pci0_scope, 1164 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1165 1166 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1167 { 1168 Aml *if_ctx; 1169 Aml *else_ctx; 1170 1171 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1172 section 6.2.8.1 */ 1173 /* Note: we provide the same info as the PCI routing 1174 table of the Bochs BIOS */ 1175 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1176 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1177 aml_append(method, if_ctx); 1178 else_ctx = aml_else(); 1179 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1180 aml_append(method, else_ctx); 1181 } 1182 aml_append(pci0_scope, method); 1183 aml_append(sb_scope, pci0_scope); 1184 1185 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1186 aml_append(field, aml_named_field("PRQA", 8)); 1187 aml_append(field, aml_named_field("PRQB", 8)); 1188 aml_append(field, aml_named_field("PRQC", 8)); 1189 aml_append(field, aml_named_field("PRQD", 8)); 1190 aml_append(field, aml_reserved_field(0x20)); 1191 aml_append(field, aml_named_field("PRQE", 8)); 1192 aml_append(field, aml_named_field("PRQF", 8)); 1193 aml_append(field, aml_named_field("PRQG", 8)); 1194 aml_append(field, aml_named_field("PRQH", 8)); 1195 aml_append(sb_scope, field); 1196 1197 aml_append(sb_scope, build_irq_status_method()); 1198 aml_append(sb_scope, build_iqcr_method(false)); 1199 1200 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1201 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1202 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1203 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1204 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1205 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1206 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1207 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1208 1209 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1210 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1211 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1212 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1213 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1214 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1215 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1216 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1217 1218 aml_append(table, sb_scope); 1219 } 1220 1221 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1222 { 1223 Aml *dev; 1224 Aml *resource_template; 1225 1226 /* DRAM controller */ 1227 dev = aml_device("DRAC"); 1228 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1229 1230 resource_template = aml_resource_template(); 1231 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1232 aml_append(resource_template, 1233 aml_qword_memory(AML_POS_DECODE, 1234 AML_MIN_FIXED, 1235 AML_MAX_FIXED, 1236 AML_NON_CACHEABLE, 1237 AML_READ_WRITE, 1238 0x0000000000000000, 1239 mcfg->base, 1240 mcfg->base + mcfg->size - 1, 1241 0x0000000000000000, 1242 mcfg->size)); 1243 } else { 1244 aml_append(resource_template, 1245 aml_dword_memory(AML_POS_DECODE, 1246 AML_MIN_FIXED, 1247 AML_MAX_FIXED, 1248 AML_NON_CACHEABLE, 1249 AML_READ_WRITE, 1250 0x0000000000000000, 1251 mcfg->base, 1252 mcfg->base + mcfg->size - 1, 1253 0x0000000000000000, 1254 mcfg->size)); 1255 } 1256 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1257 1258 return dev; 1259 } 1260 1261 static void build_q35_isa_bridge(Aml *table) 1262 { 1263 Aml *dev; 1264 Aml *scope; 1265 1266 scope = aml_scope("_SB.PCI0"); 1267 dev = aml_device("ISA"); 1268 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1269 1270 /* ICH9 PCI to ISA irq remapping */ 1271 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1272 aml_int(0x60), 0x0C)); 1273 1274 aml_append(scope, dev); 1275 aml_append(table, scope); 1276 } 1277 1278 static void build_piix4_isa_bridge(Aml *table) 1279 { 1280 Aml *dev; 1281 Aml *scope; 1282 1283 scope = aml_scope("_SB.PCI0"); 1284 dev = aml_device("ISA"); 1285 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1286 1287 /* PIIX PCI to ISA irq remapping */ 1288 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1289 aml_int(0x60), 0x04)); 1290 1291 aml_append(scope, dev); 1292 aml_append(table, scope); 1293 } 1294 1295 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1296 { 1297 Aml *scope; 1298 Aml *field; 1299 Aml *method; 1300 1301 scope = aml_scope("_SB.PCI0"); 1302 1303 aml_append(scope, 1304 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1305 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1306 aml_append(field, aml_named_field("PCIU", 32)); 1307 aml_append(field, aml_named_field("PCID", 32)); 1308 aml_append(scope, field); 1309 1310 aml_append(scope, 1311 aml_operation_region("SEJ", AML_SYSTEM_IO, 1312 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1313 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1314 aml_append(field, aml_named_field("B0EJ", 32)); 1315 aml_append(scope, field); 1316 1317 aml_append(scope, 1318 aml_operation_region("BNMR", AML_SYSTEM_IO, 1319 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1320 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1321 aml_append(field, aml_named_field("BNUM", 32)); 1322 aml_append(field, aml_named_field("PIDX", 32)); 1323 aml_append(scope, field); 1324 1325 aml_append(scope, aml_mutex("BLCK", 0)); 1326 1327 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1328 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1329 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1330 aml_append(method, 1331 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1332 aml_append(method, aml_release(aml_name("BLCK"))); 1333 aml_append(method, aml_return(aml_int(0))); 1334 aml_append(scope, method); 1335 1336 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1337 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1338 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1339 aml_append(method, 1340 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1341 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1342 aml_append(method, aml_release(aml_name("BLCK"))); 1343 aml_append(method, aml_return(aml_local(0))); 1344 aml_append(scope, method); 1345 1346 aml_append(scope, aml_pci_device_dsm()); 1347 1348 aml_append(table, scope); 1349 } 1350 1351 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1352 { 1353 Aml *if_ctx; 1354 Aml *if_ctx2; 1355 Aml *else_ctx; 1356 Aml *method; 1357 Aml *a_cwd1 = aml_name("CDW1"); 1358 Aml *a_ctrl = aml_local(0); 1359 1360 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1361 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1362 1363 if_ctx = aml_if(aml_equal( 1364 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1365 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1366 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1367 1368 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1369 1370 /* 1371 * Always allow native PME, AER (no dependencies) 1372 * Allow SHPC (PCI bridges can have SHPC controller) 1373 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1374 */ 1375 aml_append(if_ctx, aml_and(a_ctrl, 1376 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1377 1378 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1379 /* Unknown revision */ 1380 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1381 aml_append(if_ctx, if_ctx2); 1382 1383 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1384 /* Capabilities bits were masked */ 1385 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1386 aml_append(if_ctx, if_ctx2); 1387 1388 /* Update DWORD3 in the buffer */ 1389 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1390 aml_append(method, if_ctx); 1391 1392 else_ctx = aml_else(); 1393 /* Unrecognized UUID */ 1394 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1395 aml_append(method, else_ctx); 1396 1397 aml_append(method, aml_return(aml_arg(3))); 1398 return method; 1399 } 1400 1401 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func) 1402 { 1403 Aml *scope = aml_scope("_SB.PCI0"); 1404 Aml *dev = aml_device("SMB0"); 1405 1406 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); 1407 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0"); 1408 aml_append(scope, dev); 1409 aml_append(table, scope); 1410 } 1411 1412 static void 1413 build_dsdt(GArray *table_data, BIOSLinker *linker, 1414 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1415 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1416 { 1417 CrsRangeEntry *entry; 1418 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1419 CrsRangeSet crs_range_set; 1420 PCMachineState *pcms = PC_MACHINE(machine); 1421 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1422 X86MachineState *x86ms = X86_MACHINE(machine); 1423 AcpiMcfgInfo mcfg; 1424 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1425 uint32_t nr_mem = machine->ram_slots; 1426 int root_bus_limit = 0xFF; 1427 PCIBus *bus = NULL; 1428 #ifdef CONFIG_TPM 1429 TPMIf *tpm = tpm_find(); 1430 #endif 1431 int i; 1432 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1433 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1434 .oem_table_id = x86ms->oem_table_id }; 1435 1436 acpi_table_begin(&table, table_data); 1437 dsdt = init_aml_allocator(); 1438 1439 build_dbg_aml(dsdt); 1440 if (misc->is_piix4) { 1441 sb_scope = aml_scope("_SB"); 1442 dev = aml_device("PCI0"); 1443 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1444 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1445 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1446 aml_append(sb_scope, dev); 1447 aml_append(dsdt, sb_scope); 1448 1449 if (misc->has_hpet) { 1450 build_hpet_aml(dsdt); 1451 } 1452 build_piix4_isa_bridge(dsdt); 1453 build_isa_devices_aml(dsdt); 1454 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1455 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1456 } 1457 build_piix4_pci0_int(dsdt); 1458 } else { 1459 sb_scope = aml_scope("_SB"); 1460 dev = aml_device("PCI0"); 1461 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1462 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1463 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1464 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1465 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1466 aml_append(sb_scope, dev); 1467 if (mcfg_valid) { 1468 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1469 } 1470 1471 if (pm->smi_on_cpuhp) { 1472 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1473 dev = aml_device("PCI0.SMI0"); 1474 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1475 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1476 crs = aml_resource_template(); 1477 aml_append(crs, 1478 aml_io( 1479 AML_DECODE16, 1480 ACPI_PORT_SMI_CMD, 1481 ACPI_PORT_SMI_CMD, 1482 1, 1483 2) 1484 ); 1485 aml_append(dev, aml_name_decl("_CRS", crs)); 1486 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1487 aml_int(ACPI_PORT_SMI_CMD), 2)); 1488 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1489 AML_WRITE_AS_ZEROS); 1490 aml_append(field, aml_named_field("SMIC", 8)); 1491 aml_append(field, aml_reserved_field(8)); 1492 aml_append(dev, field); 1493 aml_append(sb_scope, dev); 1494 } 1495 1496 aml_append(dsdt, sb_scope); 1497 1498 if (misc->has_hpet) { 1499 build_hpet_aml(dsdt); 1500 } 1501 build_q35_isa_bridge(dsdt); 1502 build_isa_devices_aml(dsdt); 1503 if (pm->pcihp_bridge_en) { 1504 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1505 } 1506 build_q35_pci0_int(dsdt); 1507 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { 1508 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); 1509 } 1510 } 1511 1512 if (vmbus_bridge) { 1513 sb_scope = aml_scope("_SB"); 1514 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1515 aml_append(dsdt, sb_scope); 1516 } 1517 1518 if (pcmc->legacy_cpu_hotplug) { 1519 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1520 } else { 1521 CPUHotplugFeatures opts = { 1522 .acpi_1_compatible = true, .has_legacy_cphp = true, 1523 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1524 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1525 }; 1526 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1527 "\\_SB.PCI0", "\\_GPE._E02"); 1528 } 1529 1530 if (pcms->memhp_io_base && nr_mem) { 1531 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1532 "\\_GPE._E03", AML_SYSTEM_IO, 1533 pcms->memhp_io_base); 1534 } 1535 1536 scope = aml_scope("_GPE"); 1537 { 1538 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1539 1540 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1541 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1542 aml_append(method, 1543 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1544 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1545 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1546 aml_append(scope, method); 1547 } 1548 1549 if (machine->nvdimms_state->is_enabled) { 1550 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1551 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1552 aml_int(0x80))); 1553 aml_append(scope, method); 1554 } 1555 } 1556 aml_append(dsdt, scope); 1557 1558 crs_range_set_init(&crs_range_set); 1559 bus = PC_MACHINE(machine)->bus; 1560 if (bus) { 1561 QLIST_FOREACH(bus, &bus->child, sibling) { 1562 uint8_t bus_num = pci_bus_num(bus); 1563 uint8_t numa_node = pci_bus_numa_node(bus); 1564 1565 /* look only for expander root buses */ 1566 if (!pci_bus_is_root(bus)) { 1567 continue; 1568 } 1569 1570 if (bus_num < root_bus_limit) { 1571 root_bus_limit = bus_num - 1; 1572 } 1573 1574 scope = aml_scope("\\_SB"); 1575 dev = aml_device("PC%.02X", bus_num); 1576 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1577 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1578 if (pci_bus_is_express(bus)) { 1579 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1580 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1581 1582 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1583 aml_append(dev, build_q35_osc_method(true)); 1584 } else { 1585 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1586 } 1587 1588 if (numa_node != NUMA_NODE_UNASSIGNED) { 1589 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1590 } 1591 1592 aml_append(dev, build_prt(false)); 1593 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1594 0, 0, 0, 0); 1595 aml_append(dev, aml_name_decl("_CRS", crs)); 1596 aml_append(scope, dev); 1597 aml_append(dsdt, scope); 1598 } 1599 } 1600 1601 /* 1602 * At this point crs_range_set has all the ranges used by pci 1603 * busses *other* than PCI0. These ranges will be excluded from 1604 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1605 * too. 1606 */ 1607 if (mcfg_valid) { 1608 crs_range_insert(crs_range_set.mem_ranges, 1609 mcfg.base, mcfg.base + mcfg.size - 1); 1610 } 1611 1612 scope = aml_scope("\\_SB.PCI0"); 1613 /* build PCI0._CRS */ 1614 crs = aml_resource_template(); 1615 aml_append(crs, 1616 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1617 0x0000, 0x0, root_bus_limit, 1618 0x0000, root_bus_limit + 1)); 1619 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1620 1621 aml_append(crs, 1622 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1623 AML_POS_DECODE, AML_ENTIRE_RANGE, 1624 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1625 1626 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1627 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1628 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1629 aml_append(crs, 1630 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1631 AML_POS_DECODE, AML_ENTIRE_RANGE, 1632 0x0000, entry->base, entry->limit, 1633 0x0000, entry->limit - entry->base + 1)); 1634 } 1635 1636 aml_append(crs, 1637 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1638 AML_CACHEABLE, AML_READ_WRITE, 1639 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1640 1641 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1642 range_lob(pci_hole), 1643 range_upb(pci_hole)); 1644 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1645 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1646 aml_append(crs, 1647 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1648 AML_NON_CACHEABLE, AML_READ_WRITE, 1649 0, entry->base, entry->limit, 1650 0, entry->limit - entry->base + 1)); 1651 } 1652 1653 if (!range_is_empty(pci_hole64)) { 1654 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1655 range_lob(pci_hole64), 1656 range_upb(pci_hole64)); 1657 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1658 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1659 aml_append(crs, 1660 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1661 AML_MAX_FIXED, 1662 AML_CACHEABLE, AML_READ_WRITE, 1663 0, entry->base, entry->limit, 1664 0, entry->limit - entry->base + 1)); 1665 } 1666 } 1667 1668 #ifdef CONFIG_TPM 1669 if (TPM_IS_TIS_ISA(tpm_find())) { 1670 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1671 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1672 } 1673 #endif 1674 aml_append(scope, aml_name_decl("_CRS", crs)); 1675 1676 /* reserve GPE0 block resources */ 1677 dev = aml_device("GPE0"); 1678 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1679 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1680 /* device present, functioning, decoding, not shown in UI */ 1681 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1682 crs = aml_resource_template(); 1683 aml_append(crs, 1684 aml_io( 1685 AML_DECODE16, 1686 pm->fadt.gpe0_blk.address, 1687 pm->fadt.gpe0_blk.address, 1688 1, 1689 pm->fadt.gpe0_blk.bit_width / 8) 1690 ); 1691 aml_append(dev, aml_name_decl("_CRS", crs)); 1692 aml_append(scope, dev); 1693 1694 crs_range_set_free(&crs_range_set); 1695 1696 /* reserve PCIHP resources */ 1697 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1698 dev = aml_device("PHPR"); 1699 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1700 aml_append(dev, 1701 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1702 /* device present, functioning, decoding, not shown in UI */ 1703 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1704 crs = aml_resource_template(); 1705 aml_append(crs, 1706 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1707 pm->pcihp_io_len) 1708 ); 1709 aml_append(dev, aml_name_decl("_CRS", crs)); 1710 aml_append(scope, dev); 1711 } 1712 aml_append(dsdt, scope); 1713 1714 /* create S3_ / S4_ / S5_ packages if necessary */ 1715 scope = aml_scope("\\"); 1716 if (!pm->s3_disabled) { 1717 pkg = aml_package(4); 1718 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1719 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1720 aml_append(pkg, aml_int(0)); /* reserved */ 1721 aml_append(pkg, aml_int(0)); /* reserved */ 1722 aml_append(scope, aml_name_decl("_S3", pkg)); 1723 } 1724 1725 if (!pm->s4_disabled) { 1726 pkg = aml_package(4); 1727 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1728 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1729 aml_append(pkg, aml_int(pm->s4_val)); 1730 aml_append(pkg, aml_int(0)); /* reserved */ 1731 aml_append(pkg, aml_int(0)); /* reserved */ 1732 aml_append(scope, aml_name_decl("_S4", pkg)); 1733 } 1734 1735 pkg = aml_package(4); 1736 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1737 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1738 aml_append(pkg, aml_int(0)); /* reserved */ 1739 aml_append(pkg, aml_int(0)); /* reserved */ 1740 aml_append(scope, aml_name_decl("_S5", pkg)); 1741 aml_append(dsdt, scope); 1742 1743 /* create fw_cfg node, unconditionally */ 1744 { 1745 scope = aml_scope("\\_SB.PCI0"); 1746 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1747 aml_append(dsdt, scope); 1748 } 1749 1750 if (misc->applesmc_io_base) { 1751 scope = aml_scope("\\_SB.PCI0.ISA"); 1752 dev = aml_device("SMC"); 1753 1754 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 1755 /* device present, functioning, decoding, not shown in UI */ 1756 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1757 1758 crs = aml_resource_template(); 1759 aml_append(crs, 1760 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 1761 0x01, APPLESMC_MAX_DATA_LENGTH) 1762 ); 1763 aml_append(crs, aml_irq_no_flags(6)); 1764 aml_append(dev, aml_name_decl("_CRS", crs)); 1765 1766 aml_append(scope, dev); 1767 aml_append(dsdt, scope); 1768 } 1769 1770 if (misc->pvpanic_port) { 1771 scope = aml_scope("\\_SB.PCI0.ISA"); 1772 1773 dev = aml_device("PEVT"); 1774 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 1775 1776 crs = aml_resource_template(); 1777 aml_append(crs, 1778 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 1779 ); 1780 aml_append(dev, aml_name_decl("_CRS", crs)); 1781 1782 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 1783 aml_int(misc->pvpanic_port), 1)); 1784 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1785 aml_append(field, aml_named_field("PEPT", 8)); 1786 aml_append(dev, field); 1787 1788 /* device present, functioning, decoding, shown in UI */ 1789 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1790 1791 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 1792 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 1793 aml_append(method, aml_return(aml_local(0))); 1794 aml_append(dev, method); 1795 1796 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 1797 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 1798 aml_append(dev, method); 1799 1800 aml_append(scope, dev); 1801 aml_append(dsdt, scope); 1802 } 1803 1804 sb_scope = aml_scope("\\_SB"); 1805 { 1806 Object *pci_host; 1807 PCIBus *bus = NULL; 1808 1809 pci_host = acpi_get_i386_pci_host(); 1810 1811 if (pci_host) { 1812 bus = PCI_HOST_BRIDGE(pci_host)->bus; 1813 } 1814 1815 if (bus) { 1816 Aml *scope = aml_scope("PCI0"); 1817 /* Scan all PCI buses. Generate tables to support hotplug. */ 1818 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 1819 1820 #ifdef CONFIG_TPM 1821 if (TPM_IS_TIS_ISA(tpm)) { 1822 if (misc->tpm_version == TPM_VERSION_2_0) { 1823 dev = aml_device("TPM"); 1824 aml_append(dev, aml_name_decl("_HID", 1825 aml_string("MSFT0101"))); 1826 aml_append(dev, 1827 aml_name_decl("_STR", 1828 aml_string("TPM 2.0 Device"))); 1829 } else { 1830 dev = aml_device("ISA.TPM"); 1831 aml_append(dev, aml_name_decl("_HID", 1832 aml_eisaid("PNP0C31"))); 1833 } 1834 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1835 1836 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 1837 crs = aml_resource_template(); 1838 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1839 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1840 /* 1841 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 1842 Rewrite to take IRQ from TPM device model and 1843 fix default IRQ value there to use some unused IRQ 1844 */ 1845 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 1846 aml_append(dev, aml_name_decl("_CRS", crs)); 1847 1848 tpm_build_ppi_acpi(tpm, dev); 1849 1850 aml_append(scope, dev); 1851 } 1852 #endif 1853 1854 aml_append(sb_scope, scope); 1855 } 1856 } 1857 1858 #ifdef CONFIG_TPM 1859 if (TPM_IS_CRB(tpm)) { 1860 dev = aml_device("TPM"); 1861 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1862 aml_append(dev, aml_name_decl("_STR", 1863 aml_string("TPM 2.0 Device"))); 1864 crs = aml_resource_template(); 1865 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1866 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1867 aml_append(dev, aml_name_decl("_CRS", crs)); 1868 1869 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1870 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1871 1872 tpm_build_ppi_acpi(tpm, dev); 1873 1874 aml_append(sb_scope, dev); 1875 } 1876 #endif 1877 1878 if (pcms->sgx_epc.size != 0) { 1879 uint64_t epc_base = pcms->sgx_epc.base; 1880 uint64_t epc_size = pcms->sgx_epc.size; 1881 1882 dev = aml_device("EPC"); 1883 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1884 aml_append(dev, aml_name_decl("_STR", 1885 aml_unicode("Enclave Page Cache 1.0"))); 1886 crs = aml_resource_template(); 1887 aml_append(crs, 1888 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1889 AML_MAX_FIXED, AML_NON_CACHEABLE, 1890 AML_READ_WRITE, 0, epc_base, 1891 epc_base + epc_size - 1, 0, epc_size)); 1892 aml_append(dev, aml_name_decl("_CRS", crs)); 1893 1894 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1895 aml_append(method, aml_return(aml_int(0x0f))); 1896 aml_append(dev, method); 1897 1898 aml_append(sb_scope, dev); 1899 } 1900 aml_append(dsdt, sb_scope); 1901 1902 /* copy AML table into ACPI tables blob and patch header there */ 1903 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1904 acpi_table_end(linker, &table); 1905 free_aml_allocator(); 1906 } 1907 1908 /* 1909 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1910 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1911 */ 1912 static void 1913 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1914 const char *oem_table_id) 1915 { 1916 AcpiTable table = { .sig = "HPET", .rev = 1, 1917 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1918 1919 acpi_table_begin(&table, table_data); 1920 /* Note timer_block_id value must be kept in sync with value advertised by 1921 * emulated hpet 1922 */ 1923 /* Event Timer Block ID */ 1924 build_append_int_noprefix(table_data, 0x8086a201, 4); 1925 /* BASE_ADDRESS */ 1926 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1927 /* HPET Number */ 1928 build_append_int_noprefix(table_data, 0, 1); 1929 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1930 build_append_int_noprefix(table_data, 0, 2); 1931 /* Page Protection And OEM Attribute */ 1932 build_append_int_noprefix(table_data, 0, 1); 1933 acpi_table_end(linker, &table); 1934 } 1935 1936 #ifdef CONFIG_TPM 1937 /* 1938 * TCPA Description Table 1939 * 1940 * Following Level 00, Rev 00.37 of specs: 1941 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1942 * 7.1.2 ACPI Table Layout 1943 */ 1944 static void 1945 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1946 const char *oem_id, const char *oem_table_id) 1947 { 1948 unsigned log_addr_offset; 1949 AcpiTable table = { .sig = "TCPA", .rev = 2, 1950 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1951 1952 acpi_table_begin(&table, table_data); 1953 /* Platform Class */ 1954 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1955 /* Log Area Minimum Length (LAML) */ 1956 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1957 /* Log Area Start Address (LASA) */ 1958 log_addr_offset = table_data->len; 1959 build_append_int_noprefix(table_data, 0, 8); 1960 1961 /* allocate/reserve space for TPM log area */ 1962 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1963 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1964 false /* high memory */); 1965 /* log area start address to be filled by Guest linker */ 1966 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1967 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1968 1969 acpi_table_end(linker, &table); 1970 } 1971 #endif 1972 1973 #define HOLE_640K_START (640 * KiB) 1974 #define HOLE_640K_END (1 * MiB) 1975 1976 /* 1977 * ACPI spec, Revision 3.0 1978 * 5.2.15 System Resource Affinity Table (SRAT) 1979 */ 1980 static void 1981 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1982 { 1983 int i; 1984 int numa_mem_start, slots; 1985 uint64_t mem_len, mem_base, next_base; 1986 MachineClass *mc = MACHINE_GET_CLASS(machine); 1987 X86MachineState *x86ms = X86_MACHINE(machine); 1988 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1989 PCMachineState *pcms = PC_MACHINE(machine); 1990 int nb_numa_nodes = machine->numa_state->num_nodes; 1991 NodeInfo *numa_info = machine->numa_state->nodes; 1992 ram_addr_t hotpluggable_address_space_size = 1993 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1994 NULL); 1995 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1996 .oem_table_id = x86ms->oem_table_id }; 1997 1998 acpi_table_begin(&table, table_data); 1999 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 2000 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 2001 2002 for (i = 0; i < apic_ids->len; i++) { 2003 int node_id = apic_ids->cpus[i].props.node_id; 2004 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2005 2006 if (apic_id < 255) { 2007 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 2008 build_append_int_noprefix(table_data, 0, 1); /* Type */ 2009 build_append_int_noprefix(table_data, 16, 1); /* Length */ 2010 /* Proximity Domain [7:0] */ 2011 build_append_int_noprefix(table_data, node_id, 1); 2012 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 2013 /* Flags, Table 5-36 */ 2014 build_append_int_noprefix(table_data, 1, 4); 2015 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 2016 /* Proximity Domain [31:8] */ 2017 build_append_int_noprefix(table_data, 0, 3); 2018 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 2019 } else { 2020 /* 2021 * ACPI spec, Revision 4.0 2022 * 5.2.16.3 Processor Local x2APIC Affinity Structure 2023 */ 2024 build_append_int_noprefix(table_data, 2, 1); /* Type */ 2025 build_append_int_noprefix(table_data, 24, 1); /* Length */ 2026 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2027 /* Proximity Domain */ 2028 build_append_int_noprefix(table_data, node_id, 4); 2029 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 2030 /* Flags, Table 5-39 */ 2031 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 2032 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 2033 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 2034 } 2035 } 2036 2037 /* the memory map is a bit tricky, it contains at least one hole 2038 * from 640k-1M and possibly another one from 3.5G-4G. 2039 */ 2040 next_base = 0; 2041 numa_mem_start = table_data->len; 2042 2043 for (i = 1; i < nb_numa_nodes + 1; ++i) { 2044 mem_base = next_base; 2045 mem_len = numa_info[i - 1].node_mem; 2046 next_base = mem_base + mem_len; 2047 2048 /* Cut out the 640K hole */ 2049 if (mem_base <= HOLE_640K_START && 2050 next_base > HOLE_640K_START) { 2051 mem_len -= next_base - HOLE_640K_START; 2052 if (mem_len > 0) { 2053 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2054 MEM_AFFINITY_ENABLED); 2055 } 2056 2057 /* Check for the rare case: 640K < RAM < 1M */ 2058 if (next_base <= HOLE_640K_END) { 2059 next_base = HOLE_640K_END; 2060 continue; 2061 } 2062 mem_base = HOLE_640K_END; 2063 mem_len = next_base - HOLE_640K_END; 2064 } 2065 2066 /* Cut out the ACPI_PCI hole */ 2067 if (mem_base <= x86ms->below_4g_mem_size && 2068 next_base > x86ms->below_4g_mem_size) { 2069 mem_len -= next_base - x86ms->below_4g_mem_size; 2070 if (mem_len > 0) { 2071 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2072 MEM_AFFINITY_ENABLED); 2073 } 2074 mem_base = 1ULL << 32; 2075 mem_len = next_base - x86ms->below_4g_mem_size; 2076 next_base = mem_base + mem_len; 2077 } 2078 2079 if (mem_len > 0) { 2080 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2081 MEM_AFFINITY_ENABLED); 2082 } 2083 } 2084 2085 if (machine->nvdimms_state->is_enabled) { 2086 nvdimm_build_srat(table_data); 2087 } 2088 2089 sgx_epc_build_srat(table_data); 2090 2091 /* 2092 * TODO: this part is not in ACPI spec and current linux kernel boots fine 2093 * without these entries. But I recall there were issues the last time I 2094 * tried to remove it with some ancient guest OS, however I can't remember 2095 * what that was so keep this around for now 2096 */ 2097 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 2098 for (; slots < nb_numa_nodes + 2; slots++) { 2099 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2100 } 2101 2102 /* 2103 * Entry is required for Windows to enable memory hotplug in OS 2104 * and for Linux to enable SWIOTLB when booted with less than 2105 * 4G of RAM. Windows works better if the entry sets proximity 2106 * to the highest NUMA node in the machine. 2107 * Memory devices may override proximity set by this entry, 2108 * providing _PXM method if necessary. 2109 */ 2110 if (hotpluggable_address_space_size) { 2111 build_srat_memory(table_data, machine->device_memory->base, 2112 hotpluggable_address_space_size, nb_numa_nodes - 1, 2113 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2114 } 2115 2116 acpi_table_end(linker, &table); 2117 } 2118 2119 /* 2120 * Insert DMAR scope for PCI bridges and endpoint devcie 2121 */ 2122 static void 2123 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2124 { 2125 const size_t device_scope_size = 6 /* device scope structure */ + 2126 2 /* 1 path entry */; 2127 GArray *scope_blob = opaque; 2128 2129 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2130 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2131 build_append_int_noprefix(scope_blob, 0x02, 1); 2132 } else { 2133 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2134 build_append_int_noprefix(scope_blob, 0x01, 1); 2135 } 2136 2137 /* length */ 2138 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2139 /* reserved */ 2140 build_append_int_noprefix(scope_blob, 0, 2); 2141 /* enumeration_id */ 2142 build_append_int_noprefix(scope_blob, 0, 1); 2143 /* bus */ 2144 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2145 /* device */ 2146 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2147 /* function */ 2148 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2149 } 2150 2151 /* For a given PCI host bridge, walk and insert DMAR scope */ 2152 static int 2153 dmar_host_bridges(Object *obj, void *opaque) 2154 { 2155 GArray *scope_blob = opaque; 2156 2157 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2158 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2159 2160 if (bus && !pci_bus_bypass_iommu(bus)) { 2161 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2162 } 2163 } 2164 2165 return 0; 2166 } 2167 2168 /* 2169 * Intel ® Virtualization Technology for Directed I/O 2170 * Architecture Specification. Revision 3.3 2171 * 8.1 DMA Remapping Reporting Structure 2172 */ 2173 static void 2174 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2175 const char *oem_table_id) 2176 { 2177 uint8_t dmar_flags = 0; 2178 uint8_t rsvd10[10] = {}; 2179 /* Root complex IOAPIC uses one path only */ 2180 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2181 2 /* 1 path entry */; 2182 X86IOMMUState *iommu = x86_iommu_get_default(); 2183 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2184 GArray *scope_blob = g_array_new(false, true, 1); 2185 2186 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2187 .oem_table_id = oem_table_id }; 2188 2189 /* 2190 * A PCI bus walk, for each PCI host bridge. 2191 * Insert scope for each PCI bridge and endpoint device which 2192 * is attached to a bus with iommu enabled. 2193 */ 2194 object_child_foreach_recursive(object_get_root(), 2195 dmar_host_bridges, scope_blob); 2196 2197 assert(iommu); 2198 if (x86_iommu_ir_supported(iommu)) { 2199 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2200 } 2201 2202 acpi_table_begin(&table, table_data); 2203 /* Host Address Width */ 2204 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2205 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2206 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2207 2208 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2209 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2210 /* Length */ 2211 build_append_int_noprefix(table_data, 2212 16 + ioapic_scope_size + scope_blob->len, 2); 2213 /* Flags */ 2214 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2215 1); 2216 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2217 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2218 /* Register Base Address */ 2219 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2220 2221 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2222 * 8.3.1 (version Oct. 2014 or later). */ 2223 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2224 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2225 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2226 /* Enumeration ID */ 2227 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2228 /* Start Bus Number */ 2229 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2230 /* Path, {Device, Function} pair */ 2231 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2232 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2233 2234 /* Add scope found above */ 2235 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2236 g_array_free(scope_blob, true); 2237 2238 if (iommu->dt_supported) { 2239 /* 8.5 Root Port ATS Capability Reporting Structure */ 2240 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2241 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2242 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2243 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2244 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2245 } 2246 2247 acpi_table_end(linker, &table); 2248 } 2249 2250 /* 2251 * Windows ACPI Emulated Devices Table 2252 * (Version 1.0 - April 6, 2009) 2253 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2254 * 2255 * Helpful to speedup Windows guests and ignored by others. 2256 */ 2257 static void 2258 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2259 const char *oem_table_id) 2260 { 2261 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2262 .oem_table_id = oem_table_id }; 2263 2264 acpi_table_begin(&table, table_data); 2265 /* 2266 * Set "ACPI PM timer good" flag. 2267 * 2268 * Tells Windows guests that our ACPI PM timer is reliable in the 2269 * sense that guest can read it only once to obtain a reliable value. 2270 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2271 */ 2272 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2273 acpi_table_end(linker, &table); 2274 } 2275 2276 /* 2277 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2278 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2279 */ 2280 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2281 2282 /* 2283 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2284 * necessary for the PCI topology. 2285 */ 2286 static void 2287 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2288 { 2289 GArray *table_data = opaque; 2290 uint32_t entry; 2291 2292 /* "Select" IVHD entry, type 0x2 */ 2293 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2294 build_append_int_noprefix(table_data, entry, 4); 2295 2296 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2297 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2298 uint8_t sec = pci_bus_num(sec_bus); 2299 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2300 2301 if (pci_bus_is_express(sec_bus)) { 2302 /* 2303 * Walk the bus if there are subordinates, otherwise use a range 2304 * to cover an entire leaf bus. We could potentially also use a 2305 * range for traversed buses, but we'd need to take care not to 2306 * create both Select and Range entries covering the same device. 2307 * This is easier and potentially more compact. 2308 * 2309 * An example bare metal system seems to use Select entries for 2310 * root ports without a slot (ie. built-ins) and Range entries 2311 * when there is a slot. The same system also only hard-codes 2312 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2313 * making no effort to support nested bridges. We attempt to 2314 * be more thorough here. 2315 */ 2316 if (sec == sub) { /* leaf bus */ 2317 /* "Start of Range" IVHD entry, type 0x3 */ 2318 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2319 build_append_int_noprefix(table_data, entry, 4); 2320 /* "End of Range" IVHD entry, type 0x4 */ 2321 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2322 build_append_int_noprefix(table_data, entry, 4); 2323 } else { 2324 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2325 } 2326 } else { 2327 /* 2328 * If the secondary bus is conventional, then we need to create an 2329 * Alias range for everything downstream. The range covers the 2330 * first devfn on the secondary bus to the last devfn on the 2331 * subordinate bus. The alias target depends on legacy versus 2332 * express bridges, just as in pci_device_iommu_address_space(). 2333 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2334 */ 2335 uint16_t dev_id_a, dev_id_b; 2336 2337 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2338 2339 if (pci_is_express(dev) && 2340 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2341 dev_id_b = dev_id_a; 2342 } else { 2343 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2344 } 2345 2346 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2347 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2348 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2349 2350 /* "End of Range" IVHD entry, type 0x4 */ 2351 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2352 build_append_int_noprefix(table_data, entry, 4); 2353 } 2354 } 2355 } 2356 2357 /* For all PCI host bridges, walk and insert IVHD entries */ 2358 static int 2359 ivrs_host_bridges(Object *obj, void *opaque) 2360 { 2361 GArray *ivhd_blob = opaque; 2362 2363 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2364 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2365 2366 if (bus && !pci_bus_bypass_iommu(bus)) { 2367 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2368 } 2369 } 2370 2371 return 0; 2372 } 2373 2374 static void 2375 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2376 const char *oem_table_id) 2377 { 2378 int ivhd_table_len = 24; 2379 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2380 GArray *ivhd_blob = g_array_new(false, true, 1); 2381 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2382 .oem_table_id = oem_table_id }; 2383 2384 acpi_table_begin(&table, table_data); 2385 /* IVinfo - IO virtualization information common to all 2386 * IOMMU units in a system 2387 */ 2388 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2389 /* reserved */ 2390 build_append_int_noprefix(table_data, 0, 8); 2391 2392 /* IVHD definition - type 10h */ 2393 build_append_int_noprefix(table_data, 0x10, 1); 2394 /* virtualization flags */ 2395 build_append_int_noprefix(table_data, 2396 (1UL << 0) | /* HtTunEn */ 2397 (1UL << 4) | /* iotblSup */ 2398 (1UL << 6) | /* PrefSup */ 2399 (1UL << 7), /* PPRSup */ 2400 1); 2401 2402 /* 2403 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2404 * complete set of IVHD entries. Do this into a separate blob so that we 2405 * can calculate the total IVRS table length here and then append the new 2406 * blob further below. Fall back to an entry covering all devices, which 2407 * is sufficient when no aliases are present. 2408 */ 2409 object_child_foreach_recursive(object_get_root(), 2410 ivrs_host_bridges, ivhd_blob); 2411 2412 if (!ivhd_blob->len) { 2413 /* 2414 * Type 1 device entry reporting all devices 2415 * These are 4-byte device entries currently reporting the range of 2416 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2417 */ 2418 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2419 } 2420 2421 ivhd_table_len += ivhd_blob->len; 2422 2423 /* 2424 * When interrupt remapping is supported, we add a special IVHD device 2425 * for type IO-APIC. 2426 */ 2427 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2428 ivhd_table_len += 8; 2429 } 2430 2431 /* IVHD length */ 2432 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2433 /* DeviceID */ 2434 build_append_int_noprefix(table_data, s->devid, 2); 2435 /* Capability offset */ 2436 build_append_int_noprefix(table_data, s->capab_offset, 2); 2437 /* IOMMU base address */ 2438 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2439 /* PCI Segment Group */ 2440 build_append_int_noprefix(table_data, 0, 2); 2441 /* IOMMU info */ 2442 build_append_int_noprefix(table_data, 0, 2); 2443 /* IOMMU Feature Reporting */ 2444 build_append_int_noprefix(table_data, 2445 (48UL << 30) | /* HATS */ 2446 (48UL << 28) | /* GATS */ 2447 (1UL << 2) | /* GTSup */ 2448 (1UL << 6), /* GASup */ 2449 4); 2450 2451 /* IVHD entries as found above */ 2452 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2453 g_array_free(ivhd_blob, TRUE); 2454 2455 /* 2456 * Add a special IVHD device type. 2457 * Refer to spec - Table 95: IVHD device entry type codes 2458 * 2459 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2460 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2461 */ 2462 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2463 build_append_int_noprefix(table_data, 2464 (0x1ull << 56) | /* type IOAPIC */ 2465 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2466 0x48, /* special device */ 2467 8); 2468 } 2469 acpi_table_end(linker, &table); 2470 } 2471 2472 typedef 2473 struct AcpiBuildState { 2474 /* Copy of table in RAM (for patching). */ 2475 MemoryRegion *table_mr; 2476 /* Is table patched? */ 2477 uint8_t patched; 2478 void *rsdp; 2479 MemoryRegion *rsdp_mr; 2480 MemoryRegion *linker_mr; 2481 } AcpiBuildState; 2482 2483 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2484 { 2485 Object *pci_host; 2486 QObject *o; 2487 2488 pci_host = acpi_get_i386_pci_host(); 2489 if (!pci_host) { 2490 return false; 2491 } 2492 2493 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2494 if (!o) { 2495 return false; 2496 } 2497 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2498 qobject_unref(o); 2499 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2500 return false; 2501 } 2502 2503 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2504 assert(o); 2505 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2506 qobject_unref(o); 2507 return true; 2508 } 2509 2510 static 2511 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2512 { 2513 PCMachineState *pcms = PC_MACHINE(machine); 2514 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2515 X86MachineState *x86ms = X86_MACHINE(machine); 2516 DeviceState *iommu = pcms->iommu; 2517 GArray *table_offsets; 2518 unsigned facs, dsdt, rsdt, fadt; 2519 AcpiPmInfo pm; 2520 AcpiMiscInfo misc; 2521 AcpiMcfgInfo mcfg; 2522 Range pci_hole = {}, pci_hole64 = {}; 2523 uint8_t *u; 2524 size_t aml_len = 0; 2525 GArray *tables_blob = tables->table_data; 2526 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2527 Object *vmgenid_dev; 2528 char *oem_id; 2529 char *oem_table_id; 2530 2531 acpi_get_pm_info(machine, &pm); 2532 acpi_get_misc_info(&misc); 2533 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2534 acpi_get_slic_oem(&slic_oem); 2535 2536 if (slic_oem.id) { 2537 oem_id = slic_oem.id; 2538 } else { 2539 oem_id = x86ms->oem_id; 2540 } 2541 2542 if (slic_oem.table_id) { 2543 oem_table_id = slic_oem.table_id; 2544 } else { 2545 oem_table_id = x86ms->oem_table_id; 2546 } 2547 2548 table_offsets = g_array_new(false, true /* clear */, 2549 sizeof(uint32_t)); 2550 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2551 2552 bios_linker_loader_alloc(tables->linker, 2553 ACPI_BUILD_TABLE_FILE, tables_blob, 2554 64 /* Ensure FACS is aligned */, 2555 false /* high memory */); 2556 2557 /* 2558 * FACS is pointed to by FADT. 2559 * We place it first since it's the only table that has alignment 2560 * requirements. 2561 */ 2562 facs = tables_blob->len; 2563 build_facs(tables_blob); 2564 2565 /* DSDT is pointed to by FADT */ 2566 dsdt = tables_blob->len; 2567 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2568 &pci_hole, &pci_hole64, machine); 2569 2570 /* Count the size of the DSDT and SSDT, we will need it for legacy 2571 * sizing of ACPI tables. 2572 */ 2573 aml_len += tables_blob->len - dsdt; 2574 2575 /* ACPI tables pointed to by RSDT */ 2576 fadt = tables_blob->len; 2577 acpi_add_table(table_offsets, tables_blob); 2578 pm.fadt.facs_tbl_offset = &facs; 2579 pm.fadt.dsdt_tbl_offset = &dsdt; 2580 pm.fadt.xdsdt_tbl_offset = &dsdt; 2581 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2582 aml_len += tables_blob->len - fadt; 2583 2584 acpi_add_table(table_offsets, tables_blob); 2585 acpi_build_madt(tables_blob, tables->linker, x86ms, 2586 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2587 x86ms->oem_table_id); 2588 2589 #ifdef CONFIG_ACPI_ERST 2590 { 2591 Object *erst_dev; 2592 erst_dev = find_erst_dev(); 2593 if (erst_dev) { 2594 acpi_add_table(table_offsets, tables_blob); 2595 build_erst(tables_blob, tables->linker, erst_dev, 2596 x86ms->oem_id, x86ms->oem_table_id); 2597 } 2598 } 2599 #endif 2600 2601 vmgenid_dev = find_vmgenid_dev(); 2602 if (vmgenid_dev) { 2603 acpi_add_table(table_offsets, tables_blob); 2604 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2605 tables->vmgenid, tables->linker, x86ms->oem_id); 2606 } 2607 2608 if (misc.has_hpet) { 2609 acpi_add_table(table_offsets, tables_blob); 2610 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2611 x86ms->oem_table_id); 2612 } 2613 #ifdef CONFIG_TPM 2614 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2615 if (misc.tpm_version == TPM_VERSION_1_2) { 2616 acpi_add_table(table_offsets, tables_blob); 2617 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2618 x86ms->oem_id, x86ms->oem_table_id); 2619 } else { /* TPM_VERSION_2_0 */ 2620 acpi_add_table(table_offsets, tables_blob); 2621 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2622 x86ms->oem_id, x86ms->oem_table_id); 2623 } 2624 } 2625 #endif 2626 if (machine->numa_state->num_nodes) { 2627 acpi_add_table(table_offsets, tables_blob); 2628 build_srat(tables_blob, tables->linker, machine); 2629 if (machine->numa_state->have_numa_distance) { 2630 acpi_add_table(table_offsets, tables_blob); 2631 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2632 x86ms->oem_table_id); 2633 } 2634 if (machine->numa_state->hmat_enabled) { 2635 acpi_add_table(table_offsets, tables_blob); 2636 build_hmat(tables_blob, tables->linker, machine->numa_state, 2637 x86ms->oem_id, x86ms->oem_table_id); 2638 } 2639 } 2640 if (acpi_get_mcfg(&mcfg)) { 2641 acpi_add_table(table_offsets, tables_blob); 2642 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2643 x86ms->oem_table_id); 2644 } 2645 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2646 acpi_add_table(table_offsets, tables_blob); 2647 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2648 x86ms->oem_table_id); 2649 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2650 acpi_add_table(table_offsets, tables_blob); 2651 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2652 x86ms->oem_table_id); 2653 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2654 PCIDevice *pdev = PCI_DEVICE(iommu); 2655 2656 acpi_add_table(table_offsets, tables_blob); 2657 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2658 x86ms->oem_id, x86ms->oem_table_id); 2659 } 2660 if (machine->nvdimms_state->is_enabled) { 2661 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2662 machine->nvdimms_state, machine->ram_slots, 2663 x86ms->oem_id, x86ms->oem_table_id); 2664 } 2665 2666 acpi_add_table(table_offsets, tables_blob); 2667 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2668 2669 /* Add tables supplied by user (if any) */ 2670 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2671 unsigned len = acpi_table_len(u); 2672 2673 acpi_add_table(table_offsets, tables_blob); 2674 g_array_append_vals(tables_blob, u, len); 2675 } 2676 2677 /* RSDT is pointed to by RSDP */ 2678 rsdt = tables_blob->len; 2679 build_rsdt(tables_blob, tables->linker, table_offsets, 2680 oem_id, oem_table_id); 2681 2682 /* RSDP is in FSEG memory, so allocate it separately */ 2683 { 2684 AcpiRsdpData rsdp_data = { 2685 .revision = 0, 2686 .oem_id = x86ms->oem_id, 2687 .xsdt_tbl_offset = NULL, 2688 .rsdt_tbl_offset = &rsdt, 2689 }; 2690 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2691 if (!pcmc->rsdp_in_ram) { 2692 /* We used to allocate some extra space for RSDP revision 2 but 2693 * only used the RSDP revision 0 space. The extra bytes were 2694 * zeroed out and not used. 2695 * Here we continue wasting those extra 16 bytes to make sure we 2696 * don't break migration for machine types 2.2 and older due to 2697 * RSDP blob size mismatch. 2698 */ 2699 build_append_int_noprefix(tables->rsdp, 0, 16); 2700 } 2701 } 2702 2703 /* We'll expose it all to Guest so we want to reduce 2704 * chance of size changes. 2705 * 2706 * We used to align the tables to 4k, but of course this would 2707 * too simple to be enough. 4k turned out to be too small an 2708 * alignment very soon, and in fact it is almost impossible to 2709 * keep the table size stable for all (max_cpus, max_memory_slots) 2710 * combinations. So the table size is always 64k for pc-i440fx-2.1 2711 * and we give an error if the table grows beyond that limit. 2712 * 2713 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2714 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2715 * than 2.0 and we can always pad the smaller tables with zeros. We can 2716 * then use the exact size of the 2.0 tables. 2717 * 2718 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2719 */ 2720 if (pcmc->legacy_acpi_table_size) { 2721 /* Subtracting aml_len gives the size of fixed tables. Then add the 2722 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2723 */ 2724 int legacy_aml_len = 2725 pcmc->legacy_acpi_table_size + 2726 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2727 int legacy_table_size = 2728 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2729 ACPI_BUILD_ALIGN_SIZE); 2730 if (tables_blob->len > legacy_table_size) { 2731 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2732 warn_report("ACPI table size %u exceeds %d bytes," 2733 " migration may not work", 2734 tables_blob->len, legacy_table_size); 2735 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2736 " or PCI bridges."); 2737 } 2738 g_array_set_size(tables_blob, legacy_table_size); 2739 } else { 2740 /* Make sure we have a buffer in case we need to resize the tables. */ 2741 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2742 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2743 warn_report("ACPI table size %u exceeds %d bytes," 2744 " migration may not work", 2745 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2746 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2747 " or PCI bridges."); 2748 } 2749 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2750 } 2751 2752 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2753 2754 /* Cleanup memory that's no longer used. */ 2755 g_array_free(table_offsets, true); 2756 g_free(slic_oem.id); 2757 g_free(slic_oem.table_id); 2758 } 2759 2760 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2761 { 2762 uint32_t size = acpi_data_len(data); 2763 2764 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2765 memory_region_ram_resize(mr, size, &error_abort); 2766 2767 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2768 memory_region_set_dirty(mr, 0, size); 2769 } 2770 2771 static void acpi_build_update(void *build_opaque) 2772 { 2773 AcpiBuildState *build_state = build_opaque; 2774 AcpiBuildTables tables; 2775 2776 /* No state to update or already patched? Nothing to do. */ 2777 if (!build_state || build_state->patched) { 2778 return; 2779 } 2780 build_state->patched = 1; 2781 2782 acpi_build_tables_init(&tables); 2783 2784 acpi_build(&tables, MACHINE(qdev_get_machine())); 2785 2786 acpi_ram_update(build_state->table_mr, tables.table_data); 2787 2788 if (build_state->rsdp) { 2789 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2790 } else { 2791 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2792 } 2793 2794 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2795 acpi_build_tables_cleanup(&tables, true); 2796 } 2797 2798 static void acpi_build_reset(void *build_opaque) 2799 { 2800 AcpiBuildState *build_state = build_opaque; 2801 build_state->patched = 0; 2802 } 2803 2804 static const VMStateDescription vmstate_acpi_build = { 2805 .name = "acpi_build", 2806 .version_id = 1, 2807 .minimum_version_id = 1, 2808 .fields = (VMStateField[]) { 2809 VMSTATE_UINT8(patched, AcpiBuildState), 2810 VMSTATE_END_OF_LIST() 2811 }, 2812 }; 2813 2814 void acpi_setup(void) 2815 { 2816 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2817 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2818 X86MachineState *x86ms = X86_MACHINE(pcms); 2819 AcpiBuildTables tables; 2820 AcpiBuildState *build_state; 2821 Object *vmgenid_dev; 2822 #ifdef CONFIG_TPM 2823 TPMIf *tpm; 2824 static FwCfgTPMConfig tpm_config; 2825 #endif 2826 2827 if (!x86ms->fw_cfg) { 2828 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2829 return; 2830 } 2831 2832 if (!pcms->acpi_build_enabled) { 2833 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2834 return; 2835 } 2836 2837 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2838 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2839 return; 2840 } 2841 2842 build_state = g_malloc0(sizeof *build_state); 2843 2844 acpi_build_tables_init(&tables); 2845 acpi_build(&tables, MACHINE(pcms)); 2846 2847 /* Now expose it all to Guest */ 2848 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2849 build_state, tables.table_data, 2850 ACPI_BUILD_TABLE_FILE); 2851 assert(build_state->table_mr != NULL); 2852 2853 build_state->linker_mr = 2854 acpi_add_rom_blob(acpi_build_update, build_state, 2855 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2856 2857 #ifdef CONFIG_TPM 2858 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2859 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2860 2861 tpm = tpm_find(); 2862 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2863 tpm_config = (FwCfgTPMConfig) { 2864 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2865 .tpm_version = tpm_get_version(tpm), 2866 .tpmppi_version = TPM_PPI_VERSION_1_30 2867 }; 2868 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2869 &tpm_config, sizeof tpm_config); 2870 } 2871 #endif 2872 2873 vmgenid_dev = find_vmgenid_dev(); 2874 if (vmgenid_dev) { 2875 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2876 tables.vmgenid); 2877 } 2878 2879 if (!pcmc->rsdp_in_ram) { 2880 /* 2881 * Keep for compatibility with old machine types. 2882 * Though RSDP is small, its contents isn't immutable, so 2883 * we'll update it along with the rest of tables on guest access. 2884 */ 2885 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2886 2887 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2888 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2889 acpi_build_update, NULL, build_state, 2890 build_state->rsdp, rsdp_size, true); 2891 build_state->rsdp_mr = NULL; 2892 } else { 2893 build_state->rsdp = NULL; 2894 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2895 build_state, tables.rsdp, 2896 ACPI_BUILD_RSDP_FILE); 2897 } 2898 2899 qemu_register_reset(acpi_build_reset, build_state); 2900 acpi_build_reset(build_state); 2901 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2902 2903 /* Cleanup tables but don't free the memory: we track it 2904 * in build_state. 2905 */ 2906 acpi_build_tables_cleanup(&tables, false); 2907 } 2908