1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "acpi-common.h" 28 #include "qemu/bitmap.h" 29 #include "qemu/error-report.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/cxl/cxl.h" 32 #include "hw/core/cpu.h" 33 #include "target/i386/cpu.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/acpi/acpi-defs.h" 36 #include "hw/acpi/acpi.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/acpi/acpi_aml_interface.h" 41 #include "hw/input/i8042.h" 42 #include "hw/acpi/memory_hotplug.h" 43 #include "sysemu/tpm.h" 44 #include "hw/acpi/tpm.h" 45 #include "hw/acpi/vmgenid.h" 46 #include "hw/acpi/erst.h" 47 #include "hw/acpi/piix4.h" 48 #include "sysemu/tpm_backend.h" 49 #include "hw/rtc/mc146818rtc_regs.h" 50 #include "migration/vmstate.h" 51 #include "hw/mem/memory-device.h" 52 #include "hw/mem/nvdimm.h" 53 #include "sysemu/numa.h" 54 #include "sysemu/reset.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 57 /* Supported chipsets: */ 58 #include "hw/southbridge/ich9.h" 59 #include "hw/southbridge/piix.h" 60 #include "hw/acpi/pcihp.h" 61 #include "hw/i386/fw_cfg.h" 62 #include "hw/i386/pc.h" 63 #include "hw/pci/pci_bus.h" 64 #include "hw/pci-host/i440fx.h" 65 #include "hw/pci-host/q35.h" 66 #include "hw/i386/x86-iommu.h" 67 68 #include "hw/acpi/aml-build.h" 69 #include "hw/acpi/utils.h" 70 #include "hw/acpi/pci.h" 71 #include "hw/acpi/cxl.h" 72 73 #include "qom/qom-qobject.h" 74 #include "hw/i386/amd_iommu.h" 75 #include "hw/i386/intel_iommu.h" 76 #include "hw/virtio/virtio-iommu.h" 77 78 #include "hw/acpi/hmat.h" 79 #include "hw/acpi/viot.h" 80 81 #include CONFIG_DEVICES 82 83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 85 * a little bit, there should be plenty of free space since the DSDT 86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 87 */ 88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 89 #define ACPI_BUILD_ALIGN_SIZE 0x1000 90 91 #define ACPI_BUILD_TABLE_SIZE 0x20000 92 93 /* #define DEBUG_ACPI_BUILD */ 94 #ifdef DEBUG_ACPI_BUILD 95 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 97 #else 98 #define ACPI_BUILD_DPRINTF(fmt, ...) 99 #endif 100 101 typedef struct AcpiPmInfo { 102 bool s3_disabled; 103 bool s4_disabled; 104 bool pcihp_bridge_en; 105 bool smi_on_cpuhp; 106 bool smi_on_cpu_unplug; 107 bool pcihp_root_en; 108 uint8_t s4_val; 109 AcpiFadtData fadt; 110 uint16_t cpu_hp_io_base; 111 uint16_t pcihp_io_base; 112 uint16_t pcihp_io_len; 113 } AcpiPmInfo; 114 115 typedef struct AcpiMiscInfo { 116 bool has_hpet; 117 #ifdef CONFIG_TPM 118 TPMVersion tpm_version; 119 #endif 120 } AcpiMiscInfo; 121 122 typedef struct FwCfgTPMConfig { 123 uint32_t tpmppi_address; 124 uint8_t tpm_version; 125 uint8_t tpmppi_version; 126 } QEMU_PACKED FwCfgTPMConfig; 127 128 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); 129 130 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { 131 .space_id = AML_AS_SYSTEM_IO, 132 .address = NVDIMM_ACPI_IO_BASE, 133 .bit_width = NVDIMM_ACPI_IO_LEN << 3 134 }; 135 136 static void init_common_fadt_data(MachineState *ms, Object *o, 137 AcpiFadtData *data) 138 { 139 X86MachineState *x86ms = X86_MACHINE(ms); 140 /* 141 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old 142 * behavior for compatibility irrelevant to smm_enabled, which doesn't 143 * comforms to ACPI spec. 144 */ 145 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? 146 true : x86_machine_is_smm_enabled(x86ms); 147 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 148 AmlAddressSpace as = AML_AS_SYSTEM_IO; 149 AcpiFadtData fadt = { 150 .rev = 3, 151 .flags = 152 (1 << ACPI_FADT_F_WBINVD) | 153 (1 << ACPI_FADT_F_PROC_C1) | 154 (1 << ACPI_FADT_F_SLP_BUTTON) | 155 (1 << ACPI_FADT_F_RTC_S4) | 156 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 157 /* APIC destination mode ("Flat Logical") has an upper limit of 8 158 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 159 * used 160 */ 161 ((ms->smp.max_cpus > 8) ? 162 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 163 .int_model = 1 /* Multiple APIC */, 164 .rtc_century = RTC_CENTURY, 165 .plvl2_lat = 0xfff /* C2 state not supported */, 166 .plvl3_lat = 0xfff /* C3 state not supported */, 167 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, 168 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 169 .acpi_enable_cmd = 170 smm_enabled ? 171 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : 172 0, 173 .acpi_disable_cmd = 174 smm_enabled ? 175 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : 176 0, 177 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 178 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 179 .address = io + 0x04 }, 180 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 181 .gpe0_blk = { .space_id = as, .bit_width = 182 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 183 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 184 }, 185 }; 186 187 /* 188 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 189 * Flags, bit offset 1 - 8042. 190 */ 191 fadt.iapc_boot_arch = iapc_boot_arch_8042(); 192 193 *data = fadt; 194 } 195 196 static Object *object_resolve_type_unambiguous(const char *typename) 197 { 198 bool ambig; 199 Object *o = object_resolve_path_type("", typename, &ambig); 200 201 if (ambig || !o) { 202 return NULL; 203 } 204 return o; 205 } 206 207 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 208 { 209 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 210 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 211 Object *obj = piix ? piix : lpc; 212 QObject *o; 213 pm->cpu_hp_io_base = 0; 214 pm->pcihp_io_base = 0; 215 pm->pcihp_io_len = 0; 216 pm->smi_on_cpuhp = false; 217 pm->smi_on_cpu_unplug = false; 218 219 assert(obj); 220 init_common_fadt_data(machine, obj, &pm->fadt); 221 if (piix) { 222 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 223 pm->fadt.rev = 1; 224 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 225 } 226 if (lpc) { 227 uint64_t smi_features = object_property_get_uint(lpc, 228 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); 229 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 230 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 231 pm->fadt.reset_reg = r; 232 pm->fadt.reset_val = 0xf; 233 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 234 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 235 pm->smi_on_cpuhp = 236 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); 237 pm->smi_on_cpu_unplug = 238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 239 } 240 pm->pcihp_io_base = 241 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 242 pm->pcihp_io_len = 243 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 244 245 /* The above need not be conditional on machine type because the reset port 246 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 247 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); 248 249 /* Fill in optional s3/s4 related properties */ 250 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 251 if (o) { 252 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 253 } else { 254 pm->s3_disabled = false; 255 } 256 qobject_unref(o); 257 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 258 if (o) { 259 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 260 } else { 261 pm->s4_disabled = false; 262 } 263 qobject_unref(o); 264 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 265 if (o) { 266 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 267 } else { 268 pm->s4_val = false; 269 } 270 qobject_unref(o); 271 272 pm->pcihp_bridge_en = 273 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 274 NULL); 275 pm->pcihp_root_en = 276 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP, 277 NULL); 278 } 279 280 static void acpi_get_misc_info(AcpiMiscInfo *info) 281 { 282 info->has_hpet = hpet_find(); 283 #ifdef CONFIG_TPM 284 info->tpm_version = tpm_get_version(tpm_find()); 285 #endif 286 } 287 288 /* 289 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 290 * On i386 arch we only have two pci hosts, so we can look only for them. 291 */ 292 Object *acpi_get_i386_pci_host(void) 293 { 294 PCIHostState *host; 295 296 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL)); 297 if (!host) { 298 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL)); 299 } 300 301 return OBJECT(host); 302 } 303 304 static void acpi_get_pci_holes(Range *hole, Range *hole64) 305 { 306 Object *pci_host; 307 308 pci_host = acpi_get_i386_pci_host(); 309 310 if (!pci_host) { 311 return; 312 } 313 314 range_set_bounds1(hole, 315 object_property_get_uint(pci_host, 316 PCI_HOST_PROP_PCI_HOLE_START, 317 NULL), 318 object_property_get_uint(pci_host, 319 PCI_HOST_PROP_PCI_HOLE_END, 320 NULL)); 321 range_set_bounds1(hole64, 322 object_property_get_uint(pci_host, 323 PCI_HOST_PROP_PCI_HOLE64_START, 324 NULL), 325 object_property_get_uint(pci_host, 326 PCI_HOST_PROP_PCI_HOLE64_END, 327 NULL)); 328 } 329 330 static void acpi_align_size(GArray *blob, unsigned align) 331 { 332 /* Align size to multiple of given size. This reduces the chance 333 * we need to change size in the future (breaking cross version migration). 334 */ 335 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 336 } 337 338 /* 339 * ACPI spec 1.0b, 340 * 5.2.6 Firmware ACPI Control Structure 341 */ 342 static void 343 build_facs(GArray *table_data) 344 { 345 const char *sig = "FACS"; 346 const uint8_t reserved[40] = {}; 347 348 g_array_append_vals(table_data, sig, 4); /* Signature */ 349 build_append_int_noprefix(table_data, 64, 4); /* Length */ 350 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 351 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 352 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 353 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 354 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 355 } 356 357 Aml *aml_pci_device_dsm(void) 358 { 359 Aml *method; 360 361 method = aml_method("_DSM", 4, AML_SERIALIZED); 362 { 363 Aml *params = aml_local(0); 364 Aml *pkg = aml_package(2); 365 aml_append(pkg, aml_name("BSEL")); 366 aml_append(pkg, aml_name("ASUN")); 367 aml_append(method, aml_store(pkg, params)); 368 aml_append(method, 369 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), 370 aml_arg(2), aml_arg(3), params)) 371 ); 372 } 373 return method; 374 } 375 376 static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar) 377 { 378 Aml *UUID, *ifctx1; 379 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */ 380 381 aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar)); 382 /* 383 * PCI Firmware Specification 3.1 384 * 4.6. _DSM Definitions for PCI 385 */ 386 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 387 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); 388 { 389 /* call is for unsupported UUID, bail out */ 390 aml_append(ifctx1, aml_return(retvar)); 391 } 392 aml_append(ctx, ifctx1); 393 394 ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2))); 395 { 396 /* call is for unsupported REV, bail out */ 397 aml_append(ifctx1, aml_return(retvar)); 398 } 399 aml_append(ctx, ifctx1); 400 } 401 402 static Aml *aml_pci_edsm(void) 403 { 404 Aml *method, *ifctx; 405 Aml *zero = aml_int(0); 406 Aml *func = aml_arg(2); 407 Aml *ret = aml_local(0); 408 Aml *aidx = aml_local(1); 409 Aml *params = aml_arg(4); 410 411 method = aml_method("EDSM", 5, AML_SERIALIZED); 412 413 /* get supported functions */ 414 ifctx = aml_if(aml_equal(func, zero)); 415 { 416 /* 1: have supported functions */ 417 /* 7: support for function 7 */ 418 const uint8_t caps = 1 | BIT(7); 419 build_append_pci_dsm_func0_common(ifctx, ret); 420 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); 421 aml_append(ifctx, aml_return(ret)); 422 } 423 aml_append(method, ifctx); 424 425 /* handle specific functions requests */ 426 /* 427 * PCI Firmware Specification 3.1 428 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 429 * Operating Systems 430 */ 431 ifctx = aml_if(aml_equal(func, aml_int(7))); 432 { 433 Aml *pkg = aml_package(2); 434 aml_append(pkg, zero); 435 /* optional, if not impl. should return null string */ 436 aml_append(pkg, aml_string("%s", "")); 437 aml_append(ifctx, aml_store(pkg, ret)); 438 439 /* 440 * IASL is fine when initializing Package with computational data, 441 * however it makes guest unhappy /it fails to process such AML/. 442 * So use runtime assignment to set acpi-index after initializer 443 * to make OSPM happy. 444 */ 445 aml_append(ifctx, 446 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); 447 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); 448 aml_append(ifctx, aml_return(ret)); 449 } 450 aml_append(method, ifctx); 451 452 return method; 453 } 454 455 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev) 456 { 457 Aml *method; 458 459 g_assert(pdev->acpi_index != 0); 460 method = aml_method("_DSM", 4, AML_SERIALIZED); 461 { 462 Aml *params = aml_local(0); 463 Aml *pkg = aml_package(1); 464 aml_append(pkg, aml_int(pdev->acpi_index)); 465 aml_append(method, aml_store(pkg, params)); 466 aml_append(method, 467 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1), 468 aml_arg(2), aml_arg(3), params)) 469 ); 470 } 471 return method; 472 } 473 474 static void build_append_pcihp_notify_entry(Aml *method, int slot) 475 { 476 Aml *if_ctx; 477 int32_t devfn = PCI_DEVFN(slot, 0); 478 479 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 480 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 481 aml_append(method, if_ctx); 482 } 483 484 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) 485 { 486 const PCIDevice *pdev = bus->devices[devfn]; 487 488 if (PCI_FUNC(devfn)) { 489 if (IS_PCI_BRIDGE(pdev)) { 490 /* 491 * Ignore only hotplugged PCI bridges on !0 functions, but 492 * allow describing cold plugged bridges on all functions 493 */ 494 if (DEVICE(pdev)->hotplugged) { 495 return true; 496 } 497 } 498 } 499 return false; 500 } 501 502 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) 503 { 504 PCIDevice *pdev = bus->devices[devfn]; 505 if (pdev) { 506 return is_devfn_ignored_generic(devfn, bus) || 507 !DEVICE_GET_CLASS(pdev)->hotpluggable || 508 /* Cold plugged bridges aren't themselves hot-pluggable */ 509 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); 510 } else { /* non populated slots */ 511 /* 512 * hotplug is supported only for non-multifunction device 513 * so generate device description only for function 0 514 */ 515 if (PCI_FUNC(devfn) || 516 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { 517 return true; 518 } 519 } 520 return false; 521 } 522 523 static void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus, 524 QObject *bsel) 525 { 526 int devfn; 527 Aml *dev, *notify_method = NULL, *method; 528 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 529 530 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 531 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 532 533 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 534 int slot = PCI_SLOT(devfn); 535 int adr = slot << 16 | PCI_FUNC(devfn); 536 537 if (is_devfn_ignored_hotplug(devfn, bus)) { 538 continue; 539 } 540 541 if (bus->devices[devfn]) { 542 dev = aml_scope("S%.02X", devfn); 543 } else { 544 dev = aml_device("S%.02X", devfn); 545 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 546 } 547 548 /* 549 * Can't declare _SUN here for every device as it changes 'slot' 550 * enumeration order in linux kernel, so use another variable for it 551 */ 552 aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); 553 aml_append(dev, aml_pci_device_dsm()); 554 555 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 556 /* add _EJ0 to make slot hotpluggable */ 557 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 558 aml_append(method, 559 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 560 ); 561 aml_append(dev, method); 562 563 build_append_pcihp_notify_entry(notify_method, slot); 564 565 /* device descriptor has been composed, add it into parent context */ 566 aml_append(parent_scope, dev); 567 } 568 aml_append(parent_scope, notify_method); 569 } 570 571 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) 572 { 573 QObject *bsel; 574 int devfn; 575 Aml *dev; 576 577 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 578 579 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 580 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ 581 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); 582 PCIDevice *pdev = bus->devices[devfn]; 583 584 if (!pdev || is_devfn_ignored_generic(devfn, bus)) { 585 continue; 586 } 587 588 /* start to compose PCI device descriptor */ 589 dev = aml_device("S%.02X", devfn); 590 aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); 591 592 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); 593 /* add _DSM if device has acpi-index set */ 594 if (pdev->acpi_index && !bsel && 595 !object_property_get_bool(OBJECT(pdev), "hotpluggable", 596 &error_abort)) { 597 aml_append(dev, aml_pci_static_endpoint_dsm(pdev)); 598 } 599 600 /* device descriptor has been composed, add it into parent context */ 601 aml_append(parent_scope, dev); 602 } 603 604 if (bsel) { 605 build_append_pcihp_slots(parent_scope, bus, bsel); 606 } 607 608 qobject_unref(bsel); 609 } 610 611 static bool build_append_notfication_callback(Aml *parent_scope, 612 const PCIBus *bus) 613 { 614 Aml *method; 615 PCIBus *sec; 616 QObject *bsel; 617 int nr_notifiers = 0; 618 GQueue *pcnt_bus_list = g_queue_new(); 619 620 QLIST_FOREACH(sec, &bus->child, sibling) { 621 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn); 622 if (pci_bus_is_root(sec)) { 623 continue; 624 } 625 nr_notifiers = nr_notifiers + 626 build_append_notfication_callback(br_scope, sec); 627 /* 628 * add new child scope to parent 629 * and keep track of bus that have PCNT, 630 * bus list is used later to call children PCNTs from this level PCNT 631 */ 632 if (nr_notifiers) { 633 g_queue_push_tail(pcnt_bus_list, sec); 634 aml_append(parent_scope, br_scope); 635 } 636 } 637 638 /* 639 * Append PCNT method to notify about events on local and child buses. 640 * ps: hostbridge might not have hotplug (bsel) enabled but might have 641 * child bridges that do have bsel. 642 */ 643 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 644 645 /* If bus supports hotplug select it and notify about local events */ 646 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 647 if (bsel) { 648 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 649 650 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 651 aml_append(method, aml_call2("DVNT", aml_name("PCIU"), 652 aml_int(1))); /* Device Check */ 653 aml_append(method, aml_call2("DVNT", aml_name("PCID"), 654 aml_int(3))); /* Eject Request */ 655 nr_notifiers++; 656 } 657 658 /* Notify about child bus events in any case */ 659 while ((sec = g_queue_pop_head(pcnt_bus_list))) { 660 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn)); 661 } 662 663 aml_append(parent_scope, method); 664 qobject_unref(bsel); 665 g_queue_free(pcnt_bus_list); 666 return !!nr_notifiers; 667 } 668 669 static Aml *aml_pci_pdsm(void) 670 { 671 Aml *method, *ifctx, *ifctx1; 672 Aml *ret = aml_local(0); 673 Aml *caps = aml_local(1); 674 Aml *acpi_index = aml_local(2); 675 Aml *zero = aml_int(0); 676 Aml *one = aml_int(1); 677 Aml *func = aml_arg(2); 678 Aml *params = aml_arg(4); 679 Aml *bnum = aml_derefof(aml_index(params, aml_int(0))); 680 Aml *sunum = aml_derefof(aml_index(params, aml_int(1))); 681 682 method = aml_method("PDSM", 5, AML_SERIALIZED); 683 684 /* get supported functions */ 685 ifctx = aml_if(aml_equal(func, zero)); 686 { 687 build_append_pci_dsm_func0_common(ifctx, ret); 688 689 aml_append(ifctx, aml_store(zero, caps)); 690 aml_append(ifctx, 691 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 692 /* 693 * advertise function 7 if device has acpi-index 694 * acpi_index values: 695 * 0: not present (default value) 696 * FFFFFFFF: not supported (old QEMU without PIDX reg) 697 * other: device's acpi-index 698 */ 699 ifctx1 = aml_if(aml_lnot( 700 aml_or(aml_equal(acpi_index, zero), 701 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL) 702 )); 703 { 704 /* have supported functions */ 705 aml_append(ifctx1, aml_or(caps, one, caps)); 706 /* support for function 7 */ 707 aml_append(ifctx1, 708 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); 709 } 710 aml_append(ifctx, ifctx1); 711 712 aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); 713 aml_append(ifctx, aml_return(ret)); 714 } 715 aml_append(method, ifctx); 716 717 /* handle specific functions requests */ 718 /* 719 * PCI Firmware Specification 3.1 720 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under 721 * Operating Systems 722 */ 723 ifctx = aml_if(aml_equal(func, aml_int(7))); 724 { 725 Aml *pkg = aml_package(2); 726 727 aml_append(pkg, zero); 728 /* 729 * optional, if not impl. should return null string 730 */ 731 aml_append(pkg, aml_string("%s", "")); 732 aml_append(ifctx, aml_store(pkg, ret)); 733 734 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); 735 /* 736 * update acpi-index to actual value 737 */ 738 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero))); 739 aml_append(ifctx, aml_return(ret)); 740 } 741 742 aml_append(method, ifctx); 743 return method; 744 } 745 746 /** 747 * build_prt_entry: 748 * @link_name: link name for PCI route entry 749 * 750 * build AML package containing a PCI route entry for @link_name 751 */ 752 static Aml *build_prt_entry(const char *link_name) 753 { 754 Aml *a_zero = aml_int(0); 755 Aml *pkg = aml_package(4); 756 aml_append(pkg, a_zero); 757 aml_append(pkg, a_zero); 758 aml_append(pkg, aml_name("%s", link_name)); 759 aml_append(pkg, a_zero); 760 return pkg; 761 } 762 763 /* 764 * initialize_route - Initialize the interrupt routing rule 765 * through a specific LINK: 766 * if (lnk_idx == idx) 767 * route using link 'link_name' 768 */ 769 static Aml *initialize_route(Aml *route, const char *link_name, 770 Aml *lnk_idx, int idx) 771 { 772 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 773 Aml *pkg = build_prt_entry(link_name); 774 775 aml_append(if_ctx, aml_store(pkg, route)); 776 777 return if_ctx; 778 } 779 780 /* 781 * build_prt - Define interrupt rounting rules 782 * 783 * Returns an array of 128 routes, one for each device, 784 * based on device location. 785 * The main goal is to equaly distribute the interrupts 786 * over the 4 existing ACPI links (works only for i440fx). 787 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 788 * 789 */ 790 static Aml *build_prt(bool is_pci0_prt) 791 { 792 Aml *method, *while_ctx, *pin, *res; 793 794 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 795 res = aml_local(0); 796 pin = aml_local(1); 797 aml_append(method, aml_store(aml_package(128), res)); 798 aml_append(method, aml_store(aml_int(0), pin)); 799 800 /* while (pin < 128) */ 801 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 802 { 803 Aml *slot = aml_local(2); 804 Aml *lnk_idx = aml_local(3); 805 Aml *route = aml_local(4); 806 807 /* slot = pin >> 2 */ 808 aml_append(while_ctx, 809 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 810 /* lnk_idx = (slot + pin) & 3 */ 811 aml_append(while_ctx, 812 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 813 lnk_idx)); 814 815 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 816 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 817 if (is_pci0_prt) { 818 Aml *if_device_1, *if_pin_4, *else_pin_4; 819 820 /* device 1 is the power-management device, needs SCI */ 821 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 822 { 823 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 824 { 825 aml_append(if_pin_4, 826 aml_store(build_prt_entry("LNKS"), route)); 827 } 828 aml_append(if_device_1, if_pin_4); 829 else_pin_4 = aml_else(); 830 { 831 aml_append(else_pin_4, 832 aml_store(build_prt_entry("LNKA"), route)); 833 } 834 aml_append(if_device_1, else_pin_4); 835 } 836 aml_append(while_ctx, if_device_1); 837 } else { 838 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 839 } 840 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 841 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 842 843 /* route[0] = 0x[slot]FFFF */ 844 aml_append(while_ctx, 845 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 846 NULL), 847 aml_index(route, aml_int(0)))); 848 /* route[1] = pin & 3 */ 849 aml_append(while_ctx, 850 aml_store(aml_and(pin, aml_int(3), NULL), 851 aml_index(route, aml_int(1)))); 852 /* res[pin] = route */ 853 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 854 /* pin++ */ 855 aml_append(while_ctx, aml_increment(pin)); 856 } 857 aml_append(method, while_ctx); 858 /* return res*/ 859 aml_append(method, aml_return(res)); 860 861 return method; 862 } 863 864 static void build_hpet_aml(Aml *table) 865 { 866 Aml *crs; 867 Aml *field; 868 Aml *method; 869 Aml *if_ctx; 870 Aml *scope = aml_scope("_SB"); 871 Aml *dev = aml_device("HPET"); 872 Aml *zero = aml_int(0); 873 Aml *id = aml_local(0); 874 Aml *period = aml_local(1); 875 876 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 877 aml_append(dev, aml_name_decl("_UID", zero)); 878 879 aml_append(dev, 880 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 881 HPET_LEN)); 882 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 883 aml_append(field, aml_named_field("VEND", 32)); 884 aml_append(field, aml_named_field("PRD", 32)); 885 aml_append(dev, field); 886 887 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 888 aml_append(method, aml_store(aml_name("VEND"), id)); 889 aml_append(method, aml_store(aml_name("PRD"), period)); 890 aml_append(method, aml_shiftright(id, aml_int(16), id)); 891 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 892 aml_equal(id, aml_int(0xffff)))); 893 { 894 aml_append(if_ctx, aml_return(zero)); 895 } 896 aml_append(method, if_ctx); 897 898 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 899 aml_lgreater(period, aml_int(100000000)))); 900 { 901 aml_append(if_ctx, aml_return(zero)); 902 } 903 aml_append(method, if_ctx); 904 905 aml_append(method, aml_return(aml_int(0x0F))); 906 aml_append(dev, method); 907 908 crs = aml_resource_template(); 909 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 910 aml_append(dev, aml_name_decl("_CRS", crs)); 911 912 aml_append(scope, dev); 913 aml_append(table, scope); 914 } 915 916 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge) 917 { 918 Aml *dev; 919 Aml *method; 920 Aml *crs; 921 922 dev = aml_device("VMBS"); 923 aml_append(dev, aml_name_decl("STA", aml_int(0xF))); 924 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus"))); 925 aml_append(dev, aml_name_decl("_UID", aml_int(0x0))); 926 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS"))); 927 928 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 929 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL), 930 aml_name("STA"))); 931 aml_append(dev, method); 932 933 method = aml_method("_PS0", 0, AML_NOTSERIALIZED); 934 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL), 935 aml_name("STA"))); 936 aml_append(dev, method); 937 938 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 939 aml_append(method, aml_return(aml_name("STA"))); 940 aml_append(dev, method); 941 942 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0))); 943 944 crs = aml_resource_template(); 945 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); 946 aml_append(dev, aml_name_decl("_CRS", crs)); 947 948 return dev; 949 } 950 951 static void build_dbg_aml(Aml *table) 952 { 953 Aml *field; 954 Aml *method; 955 Aml *while_ctx; 956 Aml *scope = aml_scope("\\"); 957 Aml *buf = aml_local(0); 958 Aml *len = aml_local(1); 959 Aml *idx = aml_local(2); 960 961 aml_append(scope, 962 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 963 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 964 aml_append(field, aml_named_field("DBGB", 8)); 965 aml_append(scope, field); 966 967 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 968 969 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 970 aml_append(method, aml_to_buffer(buf, buf)); 971 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 972 aml_append(method, aml_store(aml_int(0), idx)); 973 974 while_ctx = aml_while(aml_lless(idx, len)); 975 aml_append(while_ctx, 976 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 977 aml_append(while_ctx, aml_increment(idx)); 978 aml_append(method, while_ctx); 979 980 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 981 aml_append(scope, method); 982 983 aml_append(table, scope); 984 } 985 986 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 987 { 988 Aml *dev; 989 Aml *crs; 990 Aml *method; 991 uint32_t irqs[] = {5, 10, 11}; 992 993 dev = aml_device("%s", name); 994 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 995 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 996 997 crs = aml_resource_template(); 998 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 999 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1000 aml_append(dev, aml_name_decl("_PRS", crs)); 1001 1002 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1003 aml_append(method, aml_return(aml_call1("IQST", reg))); 1004 aml_append(dev, method); 1005 1006 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1007 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1008 aml_append(dev, method); 1009 1010 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1011 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1012 aml_append(dev, method); 1013 1014 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1015 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1016 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1017 aml_append(dev, method); 1018 1019 return dev; 1020 } 1021 1022 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1023 { 1024 Aml *dev; 1025 Aml *crs; 1026 Aml *method; 1027 uint32_t irqs; 1028 1029 dev = aml_device("%s", name); 1030 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1031 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1032 1033 crs = aml_resource_template(); 1034 irqs = gsi; 1035 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1036 AML_SHARED, &irqs, 1)); 1037 aml_append(dev, aml_name_decl("_PRS", crs)); 1038 1039 aml_append(dev, aml_name_decl("_CRS", crs)); 1040 1041 /* 1042 * _DIS can be no-op because the interrupt cannot be disabled. 1043 */ 1044 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1045 aml_append(dev, method); 1046 1047 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1048 aml_append(dev, method); 1049 1050 return dev; 1051 } 1052 1053 /* _CRS method - get current settings */ 1054 static Aml *build_iqcr_method(bool is_piix4) 1055 { 1056 Aml *if_ctx; 1057 uint32_t irqs; 1058 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1059 Aml *crs = aml_resource_template(); 1060 1061 irqs = 0; 1062 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1063 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1064 aml_append(method, aml_name_decl("PRR0", crs)); 1065 1066 aml_append(method, 1067 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1068 1069 if (is_piix4) { 1070 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1071 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1072 aml_append(method, if_ctx); 1073 } else { 1074 aml_append(method, 1075 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1076 aml_name("PRRI"))); 1077 } 1078 1079 aml_append(method, aml_return(aml_name("PRR0"))); 1080 return method; 1081 } 1082 1083 /* _STA method - get status */ 1084 static Aml *build_irq_status_method(void) 1085 { 1086 Aml *if_ctx; 1087 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1088 1089 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1090 aml_append(if_ctx, aml_return(aml_int(0x09))); 1091 aml_append(method, if_ctx); 1092 aml_append(method, aml_return(aml_int(0x0B))); 1093 return method; 1094 } 1095 1096 static void build_piix4_pci0_int(Aml *table) 1097 { 1098 Aml *dev; 1099 Aml *crs; 1100 Aml *method; 1101 uint32_t irqs; 1102 Aml *sb_scope = aml_scope("_SB"); 1103 Aml *pci0_scope = aml_scope("PCI0"); 1104 1105 aml_append(pci0_scope, build_prt(true)); 1106 aml_append(sb_scope, pci0_scope); 1107 1108 aml_append(sb_scope, build_irq_status_method()); 1109 aml_append(sb_scope, build_iqcr_method(true)); 1110 1111 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1112 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1113 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1114 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1115 1116 dev = aml_device("LNKS"); 1117 { 1118 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1119 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1120 1121 crs = aml_resource_template(); 1122 irqs = 9; 1123 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1124 AML_ACTIVE_HIGH, AML_SHARED, 1125 &irqs, 1)); 1126 aml_append(dev, aml_name_decl("_PRS", crs)); 1127 1128 /* The SCI cannot be disabled and is always attached to GSI 9, 1129 * so these are no-ops. We only need this link to override the 1130 * polarity to active high and match the content of the MADT. 1131 */ 1132 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1133 aml_append(method, aml_return(aml_int(0x0b))); 1134 aml_append(dev, method); 1135 1136 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1137 aml_append(dev, method); 1138 1139 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1140 aml_append(method, aml_return(aml_name("_PRS"))); 1141 aml_append(dev, method); 1142 1143 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1144 aml_append(dev, method); 1145 } 1146 aml_append(sb_scope, dev); 1147 1148 aml_append(table, sb_scope); 1149 } 1150 1151 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1152 { 1153 int i; 1154 int head; 1155 Aml *pkg; 1156 char base = name[3] < 'E' ? 'A' : 'E'; 1157 char *s = g_strdup(name); 1158 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1159 1160 assert(strlen(s) == 4); 1161 1162 head = name[3] - base; 1163 for (i = 0; i < 4; i++) { 1164 if (head + i > 3) { 1165 head = i * -1; 1166 } 1167 s[3] = base + head + i; 1168 pkg = aml_package(4); 1169 aml_append(pkg, a_nr); 1170 aml_append(pkg, aml_int(i)); 1171 aml_append(pkg, aml_name("%s", s)); 1172 aml_append(pkg, aml_int(0)); 1173 aml_append(ctx, pkg); 1174 } 1175 g_free(s); 1176 } 1177 1178 static Aml *build_q35_routing_table(const char *str) 1179 { 1180 int i; 1181 Aml *pkg; 1182 char *name = g_strdup_printf("%s ", str); 1183 1184 pkg = aml_package(128); 1185 for (i = 0; i < 0x18; i++) { 1186 name[3] = 'E' + (i & 0x3); 1187 append_q35_prt_entry(pkg, i, name); 1188 } 1189 1190 name[3] = 'E'; 1191 append_q35_prt_entry(pkg, 0x18, name); 1192 1193 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1194 for (i = 0x0019; i < 0x1e; i++) { 1195 name[3] = 'A'; 1196 append_q35_prt_entry(pkg, i, name); 1197 } 1198 1199 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1200 name[3] = 'E'; 1201 append_q35_prt_entry(pkg, 0x1e, name); 1202 name[3] = 'A'; 1203 append_q35_prt_entry(pkg, 0x1f, name); 1204 1205 g_free(name); 1206 return pkg; 1207 } 1208 1209 static void build_q35_pci0_int(Aml *table) 1210 { 1211 Aml *method; 1212 Aml *sb_scope = aml_scope("_SB"); 1213 Aml *pci0_scope = aml_scope("PCI0"); 1214 1215 /* Zero => PIC mode, One => APIC Mode */ 1216 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1217 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1218 { 1219 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1220 } 1221 aml_append(table, method); 1222 1223 aml_append(pci0_scope, 1224 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1225 aml_append(pci0_scope, 1226 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1227 1228 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1229 { 1230 Aml *if_ctx; 1231 Aml *else_ctx; 1232 1233 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1234 section 6.2.8.1 */ 1235 /* Note: we provide the same info as the PCI routing 1236 table of the Bochs BIOS */ 1237 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1238 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1239 aml_append(method, if_ctx); 1240 else_ctx = aml_else(); 1241 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1242 aml_append(method, else_ctx); 1243 } 1244 aml_append(pci0_scope, method); 1245 aml_append(sb_scope, pci0_scope); 1246 1247 aml_append(sb_scope, build_irq_status_method()); 1248 aml_append(sb_scope, build_iqcr_method(false)); 1249 1250 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1251 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1252 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1253 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1254 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1255 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1256 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1257 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1258 1259 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1260 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1261 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1262 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1263 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1264 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1265 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1266 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1267 1268 aml_append(table, sb_scope); 1269 } 1270 1271 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) 1272 { 1273 Aml *dev; 1274 Aml *resource_template; 1275 1276 /* DRAM controller */ 1277 dev = aml_device("DRAC"); 1278 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); 1279 1280 resource_template = aml_resource_template(); 1281 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { 1282 aml_append(resource_template, 1283 aml_qword_memory(AML_POS_DECODE, 1284 AML_MIN_FIXED, 1285 AML_MAX_FIXED, 1286 AML_NON_CACHEABLE, 1287 AML_READ_WRITE, 1288 0x0000000000000000, 1289 mcfg->base, 1290 mcfg->base + mcfg->size - 1, 1291 0x0000000000000000, 1292 mcfg->size)); 1293 } else { 1294 aml_append(resource_template, 1295 aml_dword_memory(AML_POS_DECODE, 1296 AML_MIN_FIXED, 1297 AML_MAX_FIXED, 1298 AML_NON_CACHEABLE, 1299 AML_READ_WRITE, 1300 0x0000000000000000, 1301 mcfg->base, 1302 mcfg->base + mcfg->size - 1, 1303 0x0000000000000000, 1304 mcfg->size)); 1305 } 1306 aml_append(dev, aml_name_decl("_CRS", resource_template)); 1307 1308 return dev; 1309 } 1310 1311 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) 1312 { 1313 Aml *scope; 1314 Aml *field; 1315 Aml *method; 1316 1317 scope = aml_scope("_SB.PCI0"); 1318 1319 aml_append(scope, 1320 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); 1321 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1322 aml_append(field, aml_named_field("PCIU", 32)); 1323 aml_append(field, aml_named_field("PCID", 32)); 1324 aml_append(scope, field); 1325 1326 aml_append(scope, 1327 aml_operation_region("SEJ", AML_SYSTEM_IO, 1328 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); 1329 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1330 aml_append(field, aml_named_field("B0EJ", 32)); 1331 aml_append(scope, field); 1332 1333 aml_append(scope, 1334 aml_operation_region("BNMR", AML_SYSTEM_IO, 1335 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); 1336 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1337 aml_append(field, aml_named_field("BNUM", 32)); 1338 aml_append(field, aml_named_field("PIDX", 32)); 1339 aml_append(scope, field); 1340 1341 aml_append(scope, aml_mutex("BLCK", 0)); 1342 1343 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1344 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1345 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1346 aml_append(method, 1347 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1348 aml_append(method, aml_release(aml_name("BLCK"))); 1349 aml_append(method, aml_return(aml_int(0))); 1350 aml_append(scope, method); 1351 1352 method = aml_method("AIDX", 2, AML_NOTSERIALIZED); 1353 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1354 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1355 aml_append(method, 1356 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))); 1357 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); 1358 aml_append(method, aml_release(aml_name("BLCK"))); 1359 aml_append(method, aml_return(aml_local(0))); 1360 aml_append(scope, method); 1361 1362 aml_append(scope, aml_pci_pdsm()); 1363 1364 aml_append(table, scope); 1365 } 1366 1367 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) 1368 { 1369 Aml *if_ctx; 1370 Aml *if_ctx2; 1371 Aml *else_ctx; 1372 Aml *method; 1373 Aml *a_cwd1 = aml_name("CDW1"); 1374 Aml *a_ctrl = aml_local(0); 1375 1376 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1377 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1378 1379 if_ctx = aml_if(aml_equal( 1380 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1381 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1382 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1383 1384 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1385 1386 /* 1387 * Always allow native PME, AER (no dependencies) 1388 * Allow SHPC (PCI bridges can have SHPC controller) 1389 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. 1390 */ 1391 aml_append(if_ctx, aml_and(a_ctrl, 1392 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); 1393 1394 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1395 /* Unknown revision */ 1396 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1397 aml_append(if_ctx, if_ctx2); 1398 1399 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1400 /* Capabilities bits were masked */ 1401 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1402 aml_append(if_ctx, if_ctx2); 1403 1404 /* Update DWORD3 in the buffer */ 1405 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1406 aml_append(method, if_ctx); 1407 1408 else_ctx = aml_else(); 1409 /* Unrecognized UUID */ 1410 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1411 aml_append(method, else_ctx); 1412 1413 aml_append(method, aml_return(aml_arg(3))); 1414 return method; 1415 } 1416 1417 static void build_acpi0017(Aml *table) 1418 { 1419 Aml *dev, *scope, *method; 1420 1421 scope = aml_scope("_SB"); 1422 dev = aml_device("CXLM"); 1423 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); 1424 1425 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1426 aml_append(method, aml_return(aml_int(0x01))); 1427 aml_append(dev, method); 1428 1429 aml_append(scope, dev); 1430 aml_append(table, scope); 1431 } 1432 1433 static void 1434 build_dsdt(GArray *table_data, BIOSLinker *linker, 1435 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1436 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1437 { 1438 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); 1439 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); 1440 CrsRangeEntry *entry; 1441 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1442 CrsRangeSet crs_range_set; 1443 PCMachineState *pcms = PC_MACHINE(machine); 1444 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1445 X86MachineState *x86ms = X86_MACHINE(machine); 1446 AcpiMcfgInfo mcfg; 1447 bool mcfg_valid = !!acpi_get_mcfg(&mcfg); 1448 uint32_t nr_mem = machine->ram_slots; 1449 int root_bus_limit = 0xFF; 1450 PCIBus *bus = NULL; 1451 #ifdef CONFIG_TPM 1452 TPMIf *tpm = tpm_find(); 1453 #endif 1454 bool cxl_present = false; 1455 int i; 1456 VMBusBridge *vmbus_bridge = vmbus_bridge_find(); 1457 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, 1458 .oem_table_id = x86ms->oem_table_id }; 1459 1460 assert(!!i440fx != !!q35); 1461 1462 acpi_table_begin(&table, table_data); 1463 dsdt = init_aml_allocator(); 1464 1465 build_dbg_aml(dsdt); 1466 if (i440fx) { 1467 sb_scope = aml_scope("_SB"); 1468 dev = aml_device("PCI0"); 1469 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1470 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1471 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1472 aml_append(dev, aml_pci_edsm()); 1473 aml_append(sb_scope, dev); 1474 aml_append(dsdt, sb_scope); 1475 1476 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1477 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1478 } 1479 build_piix4_pci0_int(dsdt); 1480 } else if (q35) { 1481 sb_scope = aml_scope("_SB"); 1482 dev = aml_device("PCI0"); 1483 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1484 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1485 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1486 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); 1487 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); 1488 aml_append(dev, aml_pci_edsm()); 1489 aml_append(sb_scope, dev); 1490 if (mcfg_valid) { 1491 aml_append(sb_scope, build_q35_dram_controller(&mcfg)); 1492 } 1493 1494 if (pm->smi_on_cpuhp) { 1495 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ 1496 dev = aml_device("PCI0.SMI0"); 1497 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); 1498 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); 1499 crs = aml_resource_template(); 1500 aml_append(crs, 1501 aml_io( 1502 AML_DECODE16, 1503 ACPI_PORT_SMI_CMD, 1504 ACPI_PORT_SMI_CMD, 1505 1, 1506 2) 1507 ); 1508 aml_append(dev, aml_name_decl("_CRS", crs)); 1509 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, 1510 aml_int(ACPI_PORT_SMI_CMD), 2)); 1511 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, 1512 AML_WRITE_AS_ZEROS); 1513 aml_append(field, aml_named_field("SMIC", 8)); 1514 aml_append(field, aml_reserved_field(8)); 1515 aml_append(dev, field); 1516 aml_append(sb_scope, dev); 1517 } 1518 1519 aml_append(dsdt, sb_scope); 1520 1521 if (pm->pcihp_bridge_en) { 1522 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); 1523 } 1524 build_q35_pci0_int(dsdt); 1525 } 1526 1527 if (misc->has_hpet) { 1528 build_hpet_aml(dsdt); 1529 } 1530 1531 if (vmbus_bridge) { 1532 sb_scope = aml_scope("_SB"); 1533 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge)); 1534 aml_append(dsdt, sb_scope); 1535 } 1536 1537 scope = aml_scope("_GPE"); 1538 { 1539 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1540 if (machine->nvdimms_state->is_enabled) { 1541 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1542 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1543 aml_int(0x80))); 1544 aml_append(scope, method); 1545 } 1546 } 1547 aml_append(dsdt, scope); 1548 1549 if (pcmc->legacy_cpu_hotplug) { 1550 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1551 } else { 1552 CPUHotplugFeatures opts = { 1553 .acpi_1_compatible = true, .has_legacy_cphp = true, 1554 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, 1555 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, 1556 }; 1557 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1558 "\\_SB.PCI0", "\\_GPE._E02"); 1559 } 1560 1561 if (pcms->memhp_io_base && nr_mem) { 1562 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", 1563 "\\_GPE._E03", AML_SYSTEM_IO, 1564 pcms->memhp_io_base); 1565 } 1566 1567 crs_range_set_init(&crs_range_set); 1568 bus = PC_MACHINE(machine)->bus; 1569 if (bus) { 1570 QLIST_FOREACH(bus, &bus->child, sibling) { 1571 uint8_t bus_num = pci_bus_num(bus); 1572 uint8_t numa_node = pci_bus_numa_node(bus); 1573 1574 /* look only for expander root buses */ 1575 if (!pci_bus_is_root(bus)) { 1576 continue; 1577 } 1578 1579 if (bus_num < root_bus_limit) { 1580 root_bus_limit = bus_num - 1; 1581 } 1582 1583 scope = aml_scope("\\_SB"); 1584 1585 if (pci_bus_is_cxl(bus)) { 1586 dev = aml_device("CL%.02X", bus_num); 1587 } else { 1588 dev = aml_device("PC%.02X", bus_num); 1589 } 1590 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1591 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1592 if (pci_bus_is_cxl(bus)) { 1593 struct Aml *pkg = aml_package(2); 1594 1595 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 1596 aml_append(pkg, aml_eisaid("PNP0A08")); 1597 aml_append(pkg, aml_eisaid("PNP0A03")); 1598 aml_append(dev, aml_name_decl("_CID", pkg)); 1599 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1600 build_cxl_osc_method(dev); 1601 } else if (pci_bus_is_express(bus)) { 1602 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1603 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1604 1605 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ 1606 aml_append(dev, build_q35_osc_method(true)); 1607 } else { 1608 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1609 } 1610 1611 if (numa_node != NUMA_NODE_UNASSIGNED) { 1612 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1613 } 1614 1615 aml_append(dev, build_prt(false)); 1616 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 1617 0, 0, 0, 0); 1618 aml_append(dev, aml_name_decl("_CRS", crs)); 1619 aml_append(scope, dev); 1620 aml_append(dsdt, scope); 1621 1622 /* Handle the ranges for the PXB expanders */ 1623 if (pci_bus_is_cxl(bus)) { 1624 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1625 uint64_t base = mr->addr; 1626 1627 cxl_present = true; 1628 crs_range_insert(crs_range_set.mem_ranges, base, 1629 base + memory_region_size(mr) - 1); 1630 } 1631 } 1632 } 1633 1634 if (cxl_present) { 1635 build_acpi0017(dsdt); 1636 } 1637 1638 /* 1639 * At this point crs_range_set has all the ranges used by pci 1640 * busses *other* than PCI0. These ranges will be excluded from 1641 * the PCI0._CRS. Add mmconfig to the set so it will be excluded 1642 * too. 1643 */ 1644 if (mcfg_valid) { 1645 crs_range_insert(crs_range_set.mem_ranges, 1646 mcfg.base, mcfg.base + mcfg.size - 1); 1647 } 1648 1649 scope = aml_scope("\\_SB.PCI0"); 1650 /* build PCI0._CRS */ 1651 crs = aml_resource_template(); 1652 aml_append(crs, 1653 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1654 0x0000, 0x0, root_bus_limit, 1655 0x0000, root_bus_limit + 1)); 1656 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1657 1658 aml_append(crs, 1659 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1660 AML_POS_DECODE, AML_ENTIRE_RANGE, 1661 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1662 1663 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1664 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1665 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1666 aml_append(crs, 1667 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1668 AML_POS_DECODE, AML_ENTIRE_RANGE, 1669 0x0000, entry->base, entry->limit, 1670 0x0000, entry->limit - entry->base + 1)); 1671 } 1672 1673 aml_append(crs, 1674 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1675 AML_CACHEABLE, AML_READ_WRITE, 1676 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1677 1678 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1679 range_lob(pci_hole), 1680 range_upb(pci_hole)); 1681 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1682 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1683 aml_append(crs, 1684 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1685 AML_NON_CACHEABLE, AML_READ_WRITE, 1686 0, entry->base, entry->limit, 1687 0, entry->limit - entry->base + 1)); 1688 } 1689 1690 if (!range_is_empty(pci_hole64)) { 1691 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1692 range_lob(pci_hole64), 1693 range_upb(pci_hole64)); 1694 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1695 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1696 aml_append(crs, 1697 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1698 AML_MAX_FIXED, 1699 AML_CACHEABLE, AML_READ_WRITE, 1700 0, entry->base, entry->limit, 1701 0, entry->limit - entry->base + 1)); 1702 } 1703 } 1704 1705 #ifdef CONFIG_TPM 1706 if (TPM_IS_TIS_ISA(tpm_find())) { 1707 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1708 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1709 } 1710 #endif 1711 aml_append(scope, aml_name_decl("_CRS", crs)); 1712 1713 /* reserve GPE0 block resources */ 1714 dev = aml_device("GPE0"); 1715 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1716 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1717 /* device present, functioning, decoding, not shown in UI */ 1718 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1719 crs = aml_resource_template(); 1720 aml_append(crs, 1721 aml_io( 1722 AML_DECODE16, 1723 pm->fadt.gpe0_blk.address, 1724 pm->fadt.gpe0_blk.address, 1725 1, 1726 pm->fadt.gpe0_blk.bit_width / 8) 1727 ); 1728 aml_append(dev, aml_name_decl("_CRS", crs)); 1729 aml_append(scope, dev); 1730 1731 crs_range_set_free(&crs_range_set); 1732 1733 /* reserve PCIHP resources */ 1734 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { 1735 dev = aml_device("PHPR"); 1736 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1737 aml_append(dev, 1738 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 1739 /* device present, functioning, decoding, not shown in UI */ 1740 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1741 crs = aml_resource_template(); 1742 aml_append(crs, 1743 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 1744 pm->pcihp_io_len) 1745 ); 1746 aml_append(dev, aml_name_decl("_CRS", crs)); 1747 aml_append(scope, dev); 1748 } 1749 aml_append(dsdt, scope); 1750 1751 /* create S3_ / S4_ / S5_ packages if necessary */ 1752 scope = aml_scope("\\"); 1753 if (!pm->s3_disabled) { 1754 pkg = aml_package(4); 1755 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 1756 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1757 aml_append(pkg, aml_int(0)); /* reserved */ 1758 aml_append(pkg, aml_int(0)); /* reserved */ 1759 aml_append(scope, aml_name_decl("_S3", pkg)); 1760 } 1761 1762 if (!pm->s4_disabled) { 1763 pkg = aml_package(4); 1764 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 1765 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 1766 aml_append(pkg, aml_int(pm->s4_val)); 1767 aml_append(pkg, aml_int(0)); /* reserved */ 1768 aml_append(pkg, aml_int(0)); /* reserved */ 1769 aml_append(scope, aml_name_decl("_S4", pkg)); 1770 } 1771 1772 pkg = aml_package(4); 1773 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 1774 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 1775 aml_append(pkg, aml_int(0)); /* reserved */ 1776 aml_append(pkg, aml_int(0)); /* reserved */ 1777 aml_append(scope, aml_name_decl("_S5", pkg)); 1778 aml_append(dsdt, scope); 1779 1780 /* create fw_cfg node, unconditionally */ 1781 { 1782 scope = aml_scope("\\_SB.PCI0"); 1783 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); 1784 aml_append(dsdt, scope); 1785 } 1786 1787 sb_scope = aml_scope("\\_SB"); 1788 { 1789 Object *pci_host = acpi_get_i386_pci_host(); 1790 1791 if (pci_host) { 1792 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1793 Aml *scope = aml_scope("PCI0"); 1794 /* Scan all PCI buses. Generate tables to support hotplug. */ 1795 build_append_pci_bus_devices(scope, bus); 1796 aml_append(sb_scope, scope); 1797 } 1798 } 1799 1800 #ifdef CONFIG_TPM 1801 if (TPM_IS_CRB(tpm)) { 1802 dev = aml_device("TPM"); 1803 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 1804 aml_append(dev, aml_name_decl("_STR", 1805 aml_string("TPM 2.0 Device"))); 1806 crs = aml_resource_template(); 1807 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 1808 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 1809 aml_append(dev, aml_name_decl("_CRS", crs)); 1810 1811 aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); 1812 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1813 1814 tpm_build_ppi_acpi(tpm, dev); 1815 1816 aml_append(sb_scope, dev); 1817 } 1818 #endif 1819 1820 if (pcms->sgx_epc.size != 0) { 1821 uint64_t epc_base = pcms->sgx_epc.base; 1822 uint64_t epc_size = pcms->sgx_epc.size; 1823 1824 dev = aml_device("EPC"); 1825 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C"))); 1826 aml_append(dev, aml_name_decl("_STR", 1827 aml_unicode("Enclave Page Cache 1.0"))); 1828 crs = aml_resource_template(); 1829 aml_append(crs, 1830 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1831 AML_MAX_FIXED, AML_NON_CACHEABLE, 1832 AML_READ_WRITE, 0, epc_base, 1833 epc_base + epc_size - 1, 0, epc_size)); 1834 aml_append(dev, aml_name_decl("_CRS", crs)); 1835 1836 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1837 aml_append(method, aml_return(aml_int(0x0f))); 1838 aml_append(dev, method); 1839 1840 aml_append(sb_scope, dev); 1841 } 1842 aml_append(dsdt, sb_scope); 1843 1844 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { 1845 bool has_pcnt; 1846 1847 Object *pci_host = acpi_get_i386_pci_host(); 1848 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus; 1849 1850 scope = aml_scope("\\_SB.PCI0"); 1851 has_pcnt = build_append_notfication_callback(scope, bus); 1852 if (has_pcnt) { 1853 aml_append(dsdt, scope); 1854 } 1855 1856 scope = aml_scope("_GPE"); 1857 { 1858 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1859 if (has_pcnt) { 1860 aml_append(method, 1861 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1862 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1863 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1864 } 1865 aml_append(scope, method); 1866 } 1867 aml_append(dsdt, scope); 1868 } 1869 1870 /* copy AML table into ACPI tables blob and patch header there */ 1871 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 1872 acpi_table_end(linker, &table); 1873 free_aml_allocator(); 1874 } 1875 1876 /* 1877 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a) 1878 * 3.2.4The ACPI 2.0 HPET Description Table (HPET) 1879 */ 1880 static void 1881 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 1882 const char *oem_table_id) 1883 { 1884 AcpiTable table = { .sig = "HPET", .rev = 1, 1885 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1886 1887 acpi_table_begin(&table, table_data); 1888 /* Note timer_block_id value must be kept in sync with value advertised by 1889 * emulated hpet 1890 */ 1891 /* Event Timer Block ID */ 1892 build_append_int_noprefix(table_data, 0x8086a201, 4); 1893 /* BASE_ADDRESS */ 1894 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE); 1895 /* HPET Number */ 1896 build_append_int_noprefix(table_data, 0, 1); 1897 /* Main Counter Minimum Clock_tick in Periodic Mode */ 1898 build_append_int_noprefix(table_data, 0, 2); 1899 /* Page Protection And OEM Attribute */ 1900 build_append_int_noprefix(table_data, 0, 1); 1901 acpi_table_end(linker, &table); 1902 } 1903 1904 #ifdef CONFIG_TPM 1905 /* 1906 * TCPA Description Table 1907 * 1908 * Following Level 00, Rev 00.37 of specs: 1909 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 1910 * 7.1.2 ACPI Table Layout 1911 */ 1912 static void 1913 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, 1914 const char *oem_id, const char *oem_table_id) 1915 { 1916 unsigned log_addr_offset; 1917 AcpiTable table = { .sig = "TCPA", .rev = 2, 1918 .oem_id = oem_id, .oem_table_id = oem_table_id }; 1919 1920 acpi_table_begin(&table, table_data); 1921 /* Platform Class */ 1922 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); 1923 /* Log Area Minimum Length (LAML) */ 1924 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); 1925 /* Log Area Start Address (LASA) */ 1926 log_addr_offset = table_data->len; 1927 build_append_int_noprefix(table_data, 0, 8); 1928 1929 /* allocate/reserve space for TPM log area */ 1930 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE); 1931 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 1932 false /* high memory */); 1933 /* log area start address to be filled by Guest linker */ 1934 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 1935 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); 1936 1937 acpi_table_end(linker, &table); 1938 } 1939 #endif 1940 1941 #define HOLE_640K_START (640 * KiB) 1942 #define HOLE_640K_END (1 * MiB) 1943 1944 /* 1945 * ACPI spec, Revision 3.0 1946 * 5.2.15 System Resource Affinity Table (SRAT) 1947 */ 1948 static void 1949 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 1950 { 1951 int i; 1952 int numa_mem_start, slots; 1953 uint64_t mem_len, mem_base, next_base; 1954 MachineClass *mc = MACHINE_GET_CLASS(machine); 1955 X86MachineState *x86ms = X86_MACHINE(machine); 1956 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 1957 PCMachineState *pcms = PC_MACHINE(machine); 1958 int nb_numa_nodes = machine->numa_state->num_nodes; 1959 NodeInfo *numa_info = machine->numa_state->nodes; 1960 ram_addr_t hotpluggable_address_space_size = 1961 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 1962 NULL); 1963 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, 1964 .oem_table_id = x86ms->oem_table_id }; 1965 1966 acpi_table_begin(&table, table_data); 1967 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 1968 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 1969 1970 for (i = 0; i < apic_ids->len; i++) { 1971 int node_id = apic_ids->cpus[i].props.node_id; 1972 uint32_t apic_id = apic_ids->cpus[i].arch_id; 1973 1974 if (apic_id < 255) { 1975 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */ 1976 build_append_int_noprefix(table_data, 0, 1); /* Type */ 1977 build_append_int_noprefix(table_data, 16, 1); /* Length */ 1978 /* Proximity Domain [7:0] */ 1979 build_append_int_noprefix(table_data, node_id, 1); 1980 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ 1981 /* Flags, Table 5-36 */ 1982 build_append_int_noprefix(table_data, 1, 4); 1983 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 1984 /* Proximity Domain [31:8] */ 1985 build_append_int_noprefix(table_data, 0, 3); 1986 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 1987 } else { 1988 /* 1989 * ACPI spec, Revision 4.0 1990 * 5.2.16.3 Processor Local x2APIC Affinity Structure 1991 */ 1992 build_append_int_noprefix(table_data, 2, 1); /* Type */ 1993 build_append_int_noprefix(table_data, 24, 1); /* Length */ 1994 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 1995 /* Proximity Domain */ 1996 build_append_int_noprefix(table_data, node_id, 4); 1997 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ 1998 /* Flags, Table 5-39 */ 1999 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); 2000 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 2001 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 2002 } 2003 } 2004 2005 /* the memory map is a bit tricky, it contains at least one hole 2006 * from 640k-1M and possibly another one from 3.5G-4G. 2007 */ 2008 next_base = 0; 2009 numa_mem_start = table_data->len; 2010 2011 for (i = 1; i < nb_numa_nodes + 1; ++i) { 2012 mem_base = next_base; 2013 mem_len = numa_info[i - 1].node_mem; 2014 next_base = mem_base + mem_len; 2015 2016 /* Cut out the 640K hole */ 2017 if (mem_base <= HOLE_640K_START && 2018 next_base > HOLE_640K_START) { 2019 mem_len -= next_base - HOLE_640K_START; 2020 if (mem_len > 0) { 2021 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2022 MEM_AFFINITY_ENABLED); 2023 } 2024 2025 /* Check for the rare case: 640K < RAM < 1M */ 2026 if (next_base <= HOLE_640K_END) { 2027 next_base = HOLE_640K_END; 2028 continue; 2029 } 2030 mem_base = HOLE_640K_END; 2031 mem_len = next_base - HOLE_640K_END; 2032 } 2033 2034 /* Cut out the ACPI_PCI hole */ 2035 if (mem_base <= x86ms->below_4g_mem_size && 2036 next_base > x86ms->below_4g_mem_size) { 2037 mem_len -= next_base - x86ms->below_4g_mem_size; 2038 if (mem_len > 0) { 2039 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2040 MEM_AFFINITY_ENABLED); 2041 } 2042 mem_base = x86ms->above_4g_mem_start; 2043 mem_len = next_base - x86ms->below_4g_mem_size; 2044 next_base = mem_base + mem_len; 2045 } 2046 2047 if (mem_len > 0) { 2048 build_srat_memory(table_data, mem_base, mem_len, i - 1, 2049 MEM_AFFINITY_ENABLED); 2050 } 2051 } 2052 2053 if (machine->nvdimms_state->is_enabled) { 2054 nvdimm_build_srat(table_data); 2055 } 2056 2057 sgx_epc_build_srat(table_data); 2058 2059 /* 2060 * TODO: this part is not in ACPI spec and current linux kernel boots fine 2061 * without these entries. But I recall there were issues the last time I 2062 * tried to remove it with some ancient guest OS, however I can't remember 2063 * what that was so keep this around for now 2064 */ 2065 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; 2066 for (; slots < nb_numa_nodes + 2; slots++) { 2067 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2068 } 2069 2070 /* 2071 * Entry is required for Windows to enable memory hotplug in OS 2072 * and for Linux to enable SWIOTLB when booted with less than 2073 * 4G of RAM. Windows works better if the entry sets proximity 2074 * to the highest NUMA node in the machine. 2075 * Memory devices may override proximity set by this entry, 2076 * providing _PXM method if necessary. 2077 */ 2078 if (hotpluggable_address_space_size) { 2079 build_srat_memory(table_data, machine->device_memory->base, 2080 hotpluggable_address_space_size, nb_numa_nodes - 1, 2081 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2082 } 2083 2084 acpi_table_end(linker, &table); 2085 } 2086 2087 /* 2088 * Insert DMAR scope for PCI bridges and endpoint devcie 2089 */ 2090 static void 2091 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) 2092 { 2093 const size_t device_scope_size = 6 /* device scope structure */ + 2094 2 /* 1 path entry */; 2095 GArray *scope_blob = opaque; 2096 2097 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2098 /* Dmar Scope Type: 0x02 for PCI Bridge */ 2099 build_append_int_noprefix(scope_blob, 0x02, 1); 2100 } else { 2101 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ 2102 build_append_int_noprefix(scope_blob, 0x01, 1); 2103 } 2104 2105 /* length */ 2106 build_append_int_noprefix(scope_blob, device_scope_size, 1); 2107 /* reserved */ 2108 build_append_int_noprefix(scope_blob, 0, 2); 2109 /* enumeration_id */ 2110 build_append_int_noprefix(scope_blob, 0, 1); 2111 /* bus */ 2112 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); 2113 /* device */ 2114 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); 2115 /* function */ 2116 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); 2117 } 2118 2119 /* For a given PCI host bridge, walk and insert DMAR scope */ 2120 static int 2121 dmar_host_bridges(Object *obj, void *opaque) 2122 { 2123 GArray *scope_blob = opaque; 2124 2125 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2126 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2127 2128 if (bus && !pci_bus_bypass_iommu(bus)) { 2129 pci_for_each_device_under_bus(bus, insert_scope, scope_blob); 2130 } 2131 } 2132 2133 return 0; 2134 } 2135 2136 /* 2137 * Intel ® Virtualization Technology for Directed I/O 2138 * Architecture Specification. Revision 3.3 2139 * 8.1 DMA Remapping Reporting Structure 2140 */ 2141 static void 2142 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2143 const char *oem_table_id) 2144 { 2145 uint8_t dmar_flags = 0; 2146 uint8_t rsvd10[10] = {}; 2147 /* Root complex IOAPIC uses one path only */ 2148 const size_t ioapic_scope_size = 6 /* device scope structure */ + 2149 2 /* 1 path entry */; 2150 X86IOMMUState *iommu = x86_iommu_get_default(); 2151 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2152 GArray *scope_blob = g_array_new(false, true, 1); 2153 2154 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id, 2155 .oem_table_id = oem_table_id }; 2156 2157 /* 2158 * A PCI bus walk, for each PCI host bridge. 2159 * Insert scope for each PCI bridge and endpoint device which 2160 * is attached to a bus with iommu enabled. 2161 */ 2162 object_child_foreach_recursive(object_get_root(), 2163 dmar_host_bridges, scope_blob); 2164 2165 assert(iommu); 2166 if (x86_iommu_ir_supported(iommu)) { 2167 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2168 } 2169 2170 acpi_table_begin(&table, table_data); 2171 /* Host Address Width */ 2172 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); 2173 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ 2174 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */ 2175 2176 /* 8.3 DMAR Remapping Hardware Unit Definition structure */ 2177 build_append_int_noprefix(table_data, 0, 2); /* Type */ 2178 /* Length */ 2179 build_append_int_noprefix(table_data, 2180 16 + ioapic_scope_size + scope_blob->len, 2); 2181 /* Flags */ 2182 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , 2183 1); 2184 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ 2185 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ 2186 /* Register Base Address */ 2187 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); 2188 2189 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2190 * 8.3.1 (version Oct. 2014 or later). */ 2191 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ 2192 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ 2193 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 2194 /* Enumeration ID */ 2195 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); 2196 /* Start Bus Number */ 2197 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); 2198 /* Path, {Device, Function} pair */ 2199 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2200 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); 2201 2202 /* Add scope found above */ 2203 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); 2204 g_array_free(scope_blob, true); 2205 2206 if (iommu->dt_supported) { 2207 /* 8.5 Root Port ATS Capability Reporting Structure */ 2208 build_append_int_noprefix(table_data, 2, 2); /* Type */ 2209 build_append_int_noprefix(table_data, 8, 2); /* Length */ 2210 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ 2211 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 2212 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ 2213 } 2214 2215 acpi_table_end(linker, &table); 2216 } 2217 2218 /* 2219 * Windows ACPI Emulated Devices Table 2220 * (Version 1.0 - April 6, 2009) 2221 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx 2222 * 2223 * Helpful to speedup Windows guests and ignored by others. 2224 */ 2225 static void 2226 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2227 const char *oem_table_id) 2228 { 2229 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id, 2230 .oem_table_id = oem_table_id }; 2231 2232 acpi_table_begin(&table, table_data); 2233 /* 2234 * Set "ACPI PM timer good" flag. 2235 * 2236 * Tells Windows guests that our ACPI PM timer is reliable in the 2237 * sense that guest can read it only once to obtain a reliable value. 2238 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. 2239 */ 2240 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); 2241 acpi_table_end(linker, &table); 2242 } 2243 2244 /* 2245 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2246 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2247 */ 2248 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2249 2250 /* 2251 * Insert IVHD entry for device and recurse, insert alias, or insert range as 2252 * necessary for the PCI topology. 2253 */ 2254 static void 2255 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) 2256 { 2257 GArray *table_data = opaque; 2258 uint32_t entry; 2259 2260 /* "Select" IVHD entry, type 0x2 */ 2261 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; 2262 build_append_int_noprefix(table_data, entry, 4); 2263 2264 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 2265 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 2266 uint8_t sec = pci_bus_num(sec_bus); 2267 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; 2268 2269 if (pci_bus_is_express(sec_bus)) { 2270 /* 2271 * Walk the bus if there are subordinates, otherwise use a range 2272 * to cover an entire leaf bus. We could potentially also use a 2273 * range for traversed buses, but we'd need to take care not to 2274 * create both Select and Range entries covering the same device. 2275 * This is easier and potentially more compact. 2276 * 2277 * An example bare metal system seems to use Select entries for 2278 * root ports without a slot (ie. built-ins) and Range entries 2279 * when there is a slot. The same system also only hard-codes 2280 * the alias range for an onboard PCIe-to-PCI bridge, apparently 2281 * making no effort to support nested bridges. We attempt to 2282 * be more thorough here. 2283 */ 2284 if (sec == sub) { /* leaf bus */ 2285 /* "Start of Range" IVHD entry, type 0x3 */ 2286 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; 2287 build_append_int_noprefix(table_data, entry, 4); 2288 /* "End of Range" IVHD entry, type 0x4 */ 2289 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2290 build_append_int_noprefix(table_data, entry, 4); 2291 } else { 2292 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); 2293 } 2294 } else { 2295 /* 2296 * If the secondary bus is conventional, then we need to create an 2297 * Alias range for everything downstream. The range covers the 2298 * first devfn on the secondary bus to the last devfn on the 2299 * subordinate bus. The alias target depends on legacy versus 2300 * express bridges, just as in pci_device_iommu_address_space(). 2301 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. 2302 */ 2303 uint16_t dev_id_a, dev_id_b; 2304 2305 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); 2306 2307 if (pci_is_express(dev) && 2308 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) { 2309 dev_id_b = dev_id_a; 2310 } else { 2311 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); 2312 } 2313 2314 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ 2315 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); 2316 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); 2317 2318 /* "End of Range" IVHD entry, type 0x4 */ 2319 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; 2320 build_append_int_noprefix(table_data, entry, 4); 2321 } 2322 } 2323 } 2324 2325 /* For all PCI host bridges, walk and insert IVHD entries */ 2326 static int 2327 ivrs_host_bridges(Object *obj, void *opaque) 2328 { 2329 GArray *ivhd_blob = opaque; 2330 2331 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { 2332 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; 2333 2334 if (bus && !pci_bus_bypass_iommu(bus)) { 2335 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob); 2336 } 2337 } 2338 2339 return 0; 2340 } 2341 2342 static void 2343 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, 2344 const char *oem_table_id) 2345 { 2346 int ivhd_table_len = 24; 2347 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2348 GArray *ivhd_blob = g_array_new(false, true, 1); 2349 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id, 2350 .oem_table_id = oem_table_id }; 2351 2352 acpi_table_begin(&table, table_data); 2353 /* IVinfo - IO virtualization information common to all 2354 * IOMMU units in a system 2355 */ 2356 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2357 /* reserved */ 2358 build_append_int_noprefix(table_data, 0, 8); 2359 2360 /* IVHD definition - type 10h */ 2361 build_append_int_noprefix(table_data, 0x10, 1); 2362 /* virtualization flags */ 2363 build_append_int_noprefix(table_data, 2364 (1UL << 0) | /* HtTunEn */ 2365 (1UL << 4) | /* iotblSup */ 2366 (1UL << 6) | /* PrefSup */ 2367 (1UL << 7), /* PPRSup */ 2368 1); 2369 2370 /* 2371 * A PCI bus walk, for each PCI host bridge, is necessary to create a 2372 * complete set of IVHD entries. Do this into a separate blob so that we 2373 * can calculate the total IVRS table length here and then append the new 2374 * blob further below. Fall back to an entry covering all devices, which 2375 * is sufficient when no aliases are present. 2376 */ 2377 object_child_foreach_recursive(object_get_root(), 2378 ivrs_host_bridges, ivhd_blob); 2379 2380 if (!ivhd_blob->len) { 2381 /* 2382 * Type 1 device entry reporting all devices 2383 * These are 4-byte device entries currently reporting the range of 2384 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2385 */ 2386 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); 2387 } 2388 2389 ivhd_table_len += ivhd_blob->len; 2390 2391 /* 2392 * When interrupt remapping is supported, we add a special IVHD device 2393 * for type IO-APIC. 2394 */ 2395 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2396 ivhd_table_len += 8; 2397 } 2398 2399 /* IVHD length */ 2400 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2401 /* DeviceID */ 2402 build_append_int_noprefix(table_data, s->devid, 2); 2403 /* Capability offset */ 2404 build_append_int_noprefix(table_data, s->capab_offset, 2); 2405 /* IOMMU base address */ 2406 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2407 /* PCI Segment Group */ 2408 build_append_int_noprefix(table_data, 0, 2); 2409 /* IOMMU info */ 2410 build_append_int_noprefix(table_data, 0, 2); 2411 /* IOMMU Feature Reporting */ 2412 build_append_int_noprefix(table_data, 2413 (48UL << 30) | /* HATS */ 2414 (48UL << 28) | /* GATS */ 2415 (1UL << 2) | /* GTSup */ 2416 (1UL << 6), /* GASup */ 2417 4); 2418 2419 /* IVHD entries as found above */ 2420 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); 2421 g_array_free(ivhd_blob, TRUE); 2422 2423 /* 2424 * Add a special IVHD device type. 2425 * Refer to spec - Table 95: IVHD device entry type codes 2426 * 2427 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2428 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2429 */ 2430 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2431 build_append_int_noprefix(table_data, 2432 (0x1ull << 56) | /* type IOAPIC */ 2433 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2434 0x48, /* special device */ 2435 8); 2436 } 2437 acpi_table_end(linker, &table); 2438 } 2439 2440 typedef 2441 struct AcpiBuildState { 2442 /* Copy of table in RAM (for patching). */ 2443 MemoryRegion *table_mr; 2444 /* Is table patched? */ 2445 uint8_t patched; 2446 void *rsdp; 2447 MemoryRegion *rsdp_mr; 2448 MemoryRegion *linker_mr; 2449 } AcpiBuildState; 2450 2451 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2452 { 2453 Object *pci_host; 2454 QObject *o; 2455 2456 pci_host = acpi_get_i386_pci_host(); 2457 if (!pci_host) { 2458 return false; 2459 } 2460 2461 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2462 if (!o) { 2463 return false; 2464 } 2465 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2466 qobject_unref(o); 2467 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2468 return false; 2469 } 2470 2471 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2472 assert(o); 2473 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2474 qobject_unref(o); 2475 return true; 2476 } 2477 2478 static 2479 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2480 { 2481 PCMachineState *pcms = PC_MACHINE(machine); 2482 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2483 X86MachineState *x86ms = X86_MACHINE(machine); 2484 DeviceState *iommu = pcms->iommu; 2485 GArray *table_offsets; 2486 unsigned facs, dsdt, rsdt, fadt; 2487 AcpiPmInfo pm; 2488 AcpiMiscInfo misc; 2489 AcpiMcfgInfo mcfg; 2490 Range pci_hole = {}, pci_hole64 = {}; 2491 uint8_t *u; 2492 size_t aml_len = 0; 2493 GArray *tables_blob = tables->table_data; 2494 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2495 Object *vmgenid_dev; 2496 char *oem_id; 2497 char *oem_table_id; 2498 2499 acpi_get_pm_info(machine, &pm); 2500 acpi_get_misc_info(&misc); 2501 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2502 acpi_get_slic_oem(&slic_oem); 2503 2504 if (slic_oem.id) { 2505 oem_id = slic_oem.id; 2506 } else { 2507 oem_id = x86ms->oem_id; 2508 } 2509 2510 if (slic_oem.table_id) { 2511 oem_table_id = slic_oem.table_id; 2512 } else { 2513 oem_table_id = x86ms->oem_table_id; 2514 } 2515 2516 table_offsets = g_array_new(false, true /* clear */, 2517 sizeof(uint32_t)); 2518 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2519 2520 bios_linker_loader_alloc(tables->linker, 2521 ACPI_BUILD_TABLE_FILE, tables_blob, 2522 64 /* Ensure FACS is aligned */, 2523 false /* high memory */); 2524 2525 /* 2526 * FACS is pointed to by FADT. 2527 * We place it first since it's the only table that has alignment 2528 * requirements. 2529 */ 2530 facs = tables_blob->len; 2531 build_facs(tables_blob); 2532 2533 /* DSDT is pointed to by FADT */ 2534 dsdt = tables_blob->len; 2535 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2536 &pci_hole, &pci_hole64, machine); 2537 2538 /* Count the size of the DSDT and SSDT, we will need it for legacy 2539 * sizing of ACPI tables. 2540 */ 2541 aml_len += tables_blob->len - dsdt; 2542 2543 /* ACPI tables pointed to by RSDT */ 2544 fadt = tables_blob->len; 2545 acpi_add_table(table_offsets, tables_blob); 2546 pm.fadt.facs_tbl_offset = &facs; 2547 pm.fadt.dsdt_tbl_offset = &dsdt; 2548 pm.fadt.xdsdt_tbl_offset = &dsdt; 2549 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); 2550 aml_len += tables_blob->len - fadt; 2551 2552 acpi_add_table(table_offsets, tables_blob); 2553 acpi_build_madt(tables_blob, tables->linker, x86ms, 2554 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, 2555 x86ms->oem_table_id); 2556 2557 #ifdef CONFIG_ACPI_ERST 2558 { 2559 Object *erst_dev; 2560 erst_dev = find_erst_dev(); 2561 if (erst_dev) { 2562 acpi_add_table(table_offsets, tables_blob); 2563 build_erst(tables_blob, tables->linker, erst_dev, 2564 x86ms->oem_id, x86ms->oem_table_id); 2565 } 2566 } 2567 #endif 2568 2569 vmgenid_dev = find_vmgenid_dev(); 2570 if (vmgenid_dev) { 2571 acpi_add_table(table_offsets, tables_blob); 2572 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2573 tables->vmgenid, tables->linker, x86ms->oem_id); 2574 } 2575 2576 if (misc.has_hpet) { 2577 acpi_add_table(table_offsets, tables_blob); 2578 build_hpet(tables_blob, tables->linker, x86ms->oem_id, 2579 x86ms->oem_table_id); 2580 } 2581 #ifdef CONFIG_TPM 2582 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2583 if (misc.tpm_version == TPM_VERSION_1_2) { 2584 acpi_add_table(table_offsets, tables_blob); 2585 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, 2586 x86ms->oem_id, x86ms->oem_table_id); 2587 } else { /* TPM_VERSION_2_0 */ 2588 acpi_add_table(table_offsets, tables_blob); 2589 build_tpm2(tables_blob, tables->linker, tables->tcpalog, 2590 x86ms->oem_id, x86ms->oem_table_id); 2591 } 2592 } 2593 #endif 2594 if (machine->numa_state->num_nodes) { 2595 acpi_add_table(table_offsets, tables_blob); 2596 build_srat(tables_blob, tables->linker, machine); 2597 if (machine->numa_state->have_numa_distance) { 2598 acpi_add_table(table_offsets, tables_blob); 2599 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, 2600 x86ms->oem_table_id); 2601 } 2602 if (machine->numa_state->hmat_enabled) { 2603 acpi_add_table(table_offsets, tables_blob); 2604 build_hmat(tables_blob, tables->linker, machine->numa_state, 2605 x86ms->oem_id, x86ms->oem_table_id); 2606 } 2607 } 2608 if (acpi_get_mcfg(&mcfg)) { 2609 acpi_add_table(table_offsets, tables_blob); 2610 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, 2611 x86ms->oem_table_id); 2612 } 2613 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) { 2614 acpi_add_table(table_offsets, tables_blob); 2615 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, 2616 x86ms->oem_table_id); 2617 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) { 2618 acpi_add_table(table_offsets, tables_blob); 2619 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, 2620 x86ms->oem_table_id); 2621 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) { 2622 PCIDevice *pdev = PCI_DEVICE(iommu); 2623 2624 acpi_add_table(table_offsets, tables_blob); 2625 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), 2626 x86ms->oem_id, x86ms->oem_table_id); 2627 } 2628 if (machine->nvdimms_state->is_enabled) { 2629 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2630 machine->nvdimms_state, machine->ram_slots, 2631 x86ms->oem_id, x86ms->oem_table_id); 2632 } 2633 if (pcms->cxl_devices_state.is_enabled) { 2634 cxl_build_cedt(table_offsets, tables_blob, tables->linker, 2635 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); 2636 } 2637 2638 acpi_add_table(table_offsets, tables_blob); 2639 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); 2640 2641 /* Add tables supplied by user (if any) */ 2642 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2643 unsigned len = acpi_table_len(u); 2644 2645 acpi_add_table(table_offsets, tables_blob); 2646 g_array_append_vals(tables_blob, u, len); 2647 } 2648 2649 /* RSDT is pointed to by RSDP */ 2650 rsdt = tables_blob->len; 2651 build_rsdt(tables_blob, tables->linker, table_offsets, 2652 oem_id, oem_table_id); 2653 2654 /* RSDP is in FSEG memory, so allocate it separately */ 2655 { 2656 AcpiRsdpData rsdp_data = { 2657 .revision = 0, 2658 .oem_id = x86ms->oem_id, 2659 .xsdt_tbl_offset = NULL, 2660 .rsdt_tbl_offset = &rsdt, 2661 }; 2662 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2663 if (!pcmc->rsdp_in_ram) { 2664 /* We used to allocate some extra space for RSDP revision 2 but 2665 * only used the RSDP revision 0 space. The extra bytes were 2666 * zeroed out and not used. 2667 * Here we continue wasting those extra 16 bytes to make sure we 2668 * don't break migration for machine types 2.2 and older due to 2669 * RSDP blob size mismatch. 2670 */ 2671 build_append_int_noprefix(tables->rsdp, 0, 16); 2672 } 2673 } 2674 2675 /* We'll expose it all to Guest so we want to reduce 2676 * chance of size changes. 2677 * 2678 * We used to align the tables to 4k, but of course this would 2679 * too simple to be enough. 4k turned out to be too small an 2680 * alignment very soon, and in fact it is almost impossible to 2681 * keep the table size stable for all (max_cpus, max_memory_slots) 2682 * combinations. So the table size is always 64k for pc-i440fx-2.1 2683 * and we give an error if the table grows beyond that limit. 2684 * 2685 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2686 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2687 * than 2.0 and we can always pad the smaller tables with zeros. We can 2688 * then use the exact size of the 2.0 tables. 2689 * 2690 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2691 */ 2692 if (pcmc->legacy_acpi_table_size) { 2693 /* Subtracting aml_len gives the size of fixed tables. Then add the 2694 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2695 */ 2696 int legacy_aml_len = 2697 pcmc->legacy_acpi_table_size + 2698 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit; 2699 int legacy_table_size = 2700 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2701 ACPI_BUILD_ALIGN_SIZE); 2702 if (tables_blob->len > legacy_table_size) { 2703 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2704 warn_report("ACPI table size %u exceeds %d bytes," 2705 " migration may not work", 2706 tables_blob->len, legacy_table_size); 2707 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2708 " or PCI bridges."); 2709 } 2710 g_array_set_size(tables_blob, legacy_table_size); 2711 } else { 2712 /* Make sure we have a buffer in case we need to resize the tables. */ 2713 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2714 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2715 warn_report("ACPI table size %u exceeds %d bytes," 2716 " migration may not work", 2717 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2718 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2719 " or PCI bridges."); 2720 } 2721 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2722 } 2723 2724 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2725 2726 /* Cleanup memory that's no longer used. */ 2727 g_array_free(table_offsets, true); 2728 g_free(slic_oem.id); 2729 g_free(slic_oem.table_id); 2730 } 2731 2732 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2733 { 2734 uint32_t size = acpi_data_len(data); 2735 2736 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2737 memory_region_ram_resize(mr, size, &error_abort); 2738 2739 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2740 memory_region_set_dirty(mr, 0, size); 2741 } 2742 2743 static void acpi_build_update(void *build_opaque) 2744 { 2745 AcpiBuildState *build_state = build_opaque; 2746 AcpiBuildTables tables; 2747 2748 /* No state to update or already patched? Nothing to do. */ 2749 if (!build_state || build_state->patched) { 2750 return; 2751 } 2752 build_state->patched = 1; 2753 2754 acpi_build_tables_init(&tables); 2755 2756 acpi_build(&tables, MACHINE(qdev_get_machine())); 2757 2758 acpi_ram_update(build_state->table_mr, tables.table_data); 2759 2760 if (build_state->rsdp) { 2761 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2762 } else { 2763 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2764 } 2765 2766 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2767 acpi_build_tables_cleanup(&tables, true); 2768 } 2769 2770 static void acpi_build_reset(void *build_opaque) 2771 { 2772 AcpiBuildState *build_state = build_opaque; 2773 build_state->patched = 0; 2774 } 2775 2776 static const VMStateDescription vmstate_acpi_build = { 2777 .name = "acpi_build", 2778 .version_id = 1, 2779 .minimum_version_id = 1, 2780 .fields = (VMStateField[]) { 2781 VMSTATE_UINT8(patched, AcpiBuildState), 2782 VMSTATE_END_OF_LIST() 2783 }, 2784 }; 2785 2786 void acpi_setup(void) 2787 { 2788 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2789 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2790 X86MachineState *x86ms = X86_MACHINE(pcms); 2791 AcpiBuildTables tables; 2792 AcpiBuildState *build_state; 2793 Object *vmgenid_dev; 2794 #ifdef CONFIG_TPM 2795 TPMIf *tpm; 2796 static FwCfgTPMConfig tpm_config; 2797 #endif 2798 2799 if (!x86ms->fw_cfg) { 2800 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2801 return; 2802 } 2803 2804 if (!pcms->acpi_build_enabled) { 2805 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2806 return; 2807 } 2808 2809 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { 2810 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2811 return; 2812 } 2813 2814 build_state = g_malloc0(sizeof *build_state); 2815 2816 acpi_build_tables_init(&tables); 2817 acpi_build(&tables, MACHINE(pcms)); 2818 2819 /* Now expose it all to Guest */ 2820 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 2821 build_state, tables.table_data, 2822 ACPI_BUILD_TABLE_FILE); 2823 assert(build_state->table_mr != NULL); 2824 2825 build_state->linker_mr = 2826 acpi_add_rom_blob(acpi_build_update, build_state, 2827 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 2828 2829 #ifdef CONFIG_TPM 2830 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2831 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2832 2833 tpm = tpm_find(); 2834 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2835 tpm_config = (FwCfgTPMConfig) { 2836 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2837 .tpm_version = tpm_get_version(tpm), 2838 .tpmppi_version = TPM_PPI_VERSION_1_30 2839 }; 2840 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", 2841 &tpm_config, sizeof tpm_config); 2842 } 2843 #endif 2844 2845 vmgenid_dev = find_vmgenid_dev(); 2846 if (vmgenid_dev) { 2847 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, 2848 tables.vmgenid); 2849 } 2850 2851 if (!pcmc->rsdp_in_ram) { 2852 /* 2853 * Keep for compatibility with old machine types. 2854 * Though RSDP is small, its contents isn't immutable, so 2855 * we'll update it along with the rest of tables on guest access. 2856 */ 2857 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2858 2859 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2860 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2861 acpi_build_update, NULL, build_state, 2862 build_state->rsdp, rsdp_size, true); 2863 build_state->rsdp_mr = NULL; 2864 } else { 2865 build_state->rsdp = NULL; 2866 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 2867 build_state, tables.rsdp, 2868 ACPI_BUILD_RSDP_FILE); 2869 } 2870 2871 qemu_register_reset(acpi_build_reset, build_state); 2872 acpi_build_reset(build_state); 2873 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2874 2875 /* Cleanup tables but don't free the memory: we track it 2876 * in build_state. 2877 */ 2878 acpi_build_tables_cleanup(&tables, false); 2879 } 2880