xref: /openbmc/qemu/hw/i2c/smbus_ich9.c (revision fa59483d)
1 /*
2  * ACPI implementation
3  *
4  * Copyright (c) 2006 Fabrice Bellard
5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6  *               VA Linux Systems Japan K.K.
7  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
8  *
9  * This is based on acpi.c, but heavily rewritten.
10  *
11  * This library is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU Lesser General Public
13  * License version 2 as published by the Free Software Foundation.
14  *
15  * This library is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  * Lesser General Public License for more details.
19  *
20  * You should have received a copy of the GNU Lesser General Public
21  * License along with this library; if not, see <http://www.gnu.org/licenses/>
22  *
23  * Contributions after 2012-01-13 are licensed under the terms of the
24  * GNU GPL, version 2 or (at your option) any later version.
25  *
26  */
27 #include "qemu/osdep.h"
28 #include "hw/hw.h"
29 #include "hw/i2c/pm_smbus.h"
30 #include "hw/pci/pci.h"
31 #include "sysemu/sysemu.h"
32 
33 #include "hw/i386/ich9.h"
34 
35 #define ICH9_SMB_DEVICE(obj) \
36      OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
37 
38 typedef struct ICH9SMBState {
39     PCIDevice dev;
40 
41     bool irq_enabled;
42 
43     PMSMBus smb;
44 } ICH9SMBState;
45 
46 static bool ich9_vmstate_need_smbus(void *opaque, int version_id)
47 {
48     return pm_smbus_vmstate_needed();
49 }
50 
51 static const VMStateDescription vmstate_ich9_smbus = {
52     .name = "ich9_smb",
53     .version_id = 1,
54     .minimum_version_id = 1,
55     .fields = (VMStateField[]) {
56         VMSTATE_PCI_DEVICE(dev, ICH9SMBState),
57         VMSTATE_BOOL_TEST(irq_enabled, ICH9SMBState, ich9_vmstate_need_smbus),
58         VMSTATE_STRUCT_TEST(smb, ICH9SMBState, ich9_vmstate_need_smbus, 1,
59                             pmsmb_vmstate, PMSMBus),
60         VMSTATE_END_OF_LIST()
61     }
62 };
63 
64 static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
65                                     uint32_t val, int len)
66 {
67     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
68 
69     pci_default_write_config(d, address, val, len);
70     if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
71         uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
72         if (hostc & ICH9_SMB_HOSTC_HST_EN) {
73             memory_region_set_enabled(&s->smb.io, true);
74         } else {
75             memory_region_set_enabled(&s->smb.io, false);
76         }
77         s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0;
78         if (hostc & ICH9_SMB_HOSTC_SSRESET) {
79             s->smb.reset(&s->smb);
80             s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET;
81         }
82     }
83 }
84 
85 static void ich9_smbus_realize(PCIDevice *d, Error **errp)
86 {
87     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
88 
89     /* TODO? D31IP.SMIP in chipset configuration space */
90     pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
91 
92     pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
93     /* TODO bar0, bar1: 64bit BAR support*/
94 
95     pm_smbus_init(&d->qdev, &s->smb, false);
96     pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
97                      &s->smb.io);
98 }
99 
100 static void ich9_smb_class_init(ObjectClass *klass, void *data)
101 {
102     DeviceClass *dc = DEVICE_CLASS(klass);
103     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
104 
105     k->vendor_id = PCI_VENDOR_ID_INTEL;
106     k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
107     k->revision = ICH9_A2_SMB_REVISION;
108     k->class_id = PCI_CLASS_SERIAL_SMBUS;
109     dc->vmsd = &vmstate_ich9_smbus;
110     dc->desc = "ICH9 SMBUS Bridge";
111     k->realize = ich9_smbus_realize;
112     k->config_write = ich9_smbus_write_config;
113     /*
114      * Reason: part of ICH9 southbridge, needs to be wired up by
115      * pc_q35_init()
116      */
117     dc->user_creatable = false;
118 }
119 
120 static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
121 {
122     ICH9SMBState *s = pmsmb->opaque;
123 
124     if (enabled == s->irq_enabled) {
125         return;
126     }
127 
128     s->irq_enabled = enabled;
129     pci_set_irq(&s->dev, enabled);
130 }
131 
132 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
133 {
134     PCIDevice *d =
135         pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
136     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
137     s->smb.set_irq = ich9_smb_set_irq;
138     s->smb.opaque = s;
139     return s->smb.smbus;
140 }
141 
142 static const TypeInfo ich9_smb_info = {
143     .name   = TYPE_ICH9_SMB_DEVICE,
144     .parent = TYPE_PCI_DEVICE,
145     .instance_size = sizeof(ICH9SMBState),
146     .class_init = ich9_smb_class_init,
147     .interfaces = (InterfaceInfo[]) {
148         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
149         { },
150     },
151 };
152 
153 static void ich9_smb_register(void)
154 {
155     type_register_static(&ich9_smb_info);
156 }
157 
158 type_init(ich9_smb_register);
159