xref: /openbmc/qemu/hw/i2c/smbus_ich9.c (revision 520e210c)
1 /*
2  * ACPI implementation
3  *
4  * Copyright (c) 2006 Fabrice Bellard
5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6  *               VA Linux Systems Japan K.K.
7  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
8  *
9  * This is based on acpi.c, but heavily rewritten.
10  *
11  * This library is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU Lesser General Public
13  * License version 2 as published by the Free Software Foundation.
14  *
15  * This library is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  * Lesser General Public License for more details.
19  *
20  * You should have received a copy of the GNU Lesser General Public
21  * License along with this library; if not, see <http://www.gnu.org/licenses/>
22  *
23  * Contributions after 2012-01-13 are licensed under the terms of the
24  * GNU GPL, version 2 or (at your option) any later version.
25  *
26  */
27 #include "qemu/osdep.h"
28 #include "hw/hw.h"
29 #include "hw/i2c/pm_smbus.h"
30 #include "hw/pci/pci.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/i2c/i2c.h"
33 #include "hw/i2c/smbus.h"
34 
35 #include "hw/i386/ich9.h"
36 
37 #define ICH9_SMB_DEVICE(obj) \
38      OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
39 
40 typedef struct ICH9SMBState {
41     PCIDevice dev;
42 
43     bool irq_enabled;
44 
45     PMSMBus smb;
46 } ICH9SMBState;
47 
48 static const VMStateDescription vmstate_ich9_smbus = {
49     .name = "ich9_smb",
50     .version_id = 1,
51     .minimum_version_id = 1,
52     .fields = (VMStateField[]) {
53         VMSTATE_PCI_DEVICE(dev, struct ICH9SMBState),
54         VMSTATE_END_OF_LIST()
55     }
56 };
57 
58 static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
59                                     uint32_t val, int len)
60 {
61     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
62 
63     pci_default_write_config(d, address, val, len);
64     if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
65         uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
66         if (hostc & ICH9_SMB_HOSTC_HST_EN) {
67             memory_region_set_enabled(&s->smb.io, true);
68         } else {
69             memory_region_set_enabled(&s->smb.io, false);
70         }
71         s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0;
72         if (hostc & ICH9_SMB_HOSTC_SSRESET) {
73             s->smb.reset(&s->smb);
74             s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET;
75         }
76     }
77 }
78 
79 static void ich9_smbus_realize(PCIDevice *d, Error **errp)
80 {
81     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
82 
83     /* TODO? D31IP.SMIP in chipset configuration space */
84     pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
85 
86     pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
87     /* TODO bar0, bar1: 64bit BAR support*/
88 
89     pm_smbus_init(&d->qdev, &s->smb, false);
90     pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
91                      &s->smb.io);
92 }
93 
94 static void ich9_smb_class_init(ObjectClass *klass, void *data)
95 {
96     DeviceClass *dc = DEVICE_CLASS(klass);
97     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
98 
99     k->vendor_id = PCI_VENDOR_ID_INTEL;
100     k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
101     k->revision = ICH9_A2_SMB_REVISION;
102     k->class_id = PCI_CLASS_SERIAL_SMBUS;
103     dc->vmsd = &vmstate_ich9_smbus;
104     dc->desc = "ICH9 SMBUS Bridge";
105     k->realize = ich9_smbus_realize;
106     k->config_write = ich9_smbus_write_config;
107     /*
108      * Reason: part of ICH9 southbridge, needs to be wired up by
109      * pc_q35_init()
110      */
111     dc->user_creatable = false;
112 }
113 
114 static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
115 {
116     ICH9SMBState *s = pmsmb->opaque;
117 
118     if (enabled == s->irq_enabled) {
119         return;
120     }
121 
122     s->irq_enabled = enabled;
123     pci_set_irq(&s->dev, enabled);
124 }
125 
126 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
127 {
128     PCIDevice *d =
129         pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
130     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
131     s->smb.set_irq = ich9_smb_set_irq;
132     s->smb.opaque = s;
133     return s->smb.smbus;
134 }
135 
136 static const TypeInfo ich9_smb_info = {
137     .name   = TYPE_ICH9_SMB_DEVICE,
138     .parent = TYPE_PCI_DEVICE,
139     .instance_size = sizeof(ICH9SMBState),
140     .class_init = ich9_smb_class_init,
141     .interfaces = (InterfaceInfo[]) {
142         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
143         { },
144     },
145 };
146 
147 static void ich9_smb_register(void)
148 {
149     type_register_static(&ich9_smb_info);
150 }
151 
152 type_init(ich9_smb_register);
153