1 /* 2 * QEMU SMBus EEPROM device 3 * 4 * Copyright (c) 2007 Arastra, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/boards.h" 30 #include "hw/i2c/i2c.h" 31 #include "hw/i2c/smbus_slave.h" 32 #include "hw/i2c/smbus_eeprom.h" 33 34 //#define DEBUG 35 36 #define TYPE_SMBUS_EEPROM "smbus-eeprom" 37 38 #define SMBUS_EEPROM(obj) \ 39 OBJECT_CHECK(SMBusEEPROMDevice, (obj), TYPE_SMBUS_EEPROM) 40 41 #define SMBUS_EEPROM_SIZE 256 42 43 typedef struct SMBusEEPROMDevice { 44 SMBusDevice smbusdev; 45 uint8_t data[SMBUS_EEPROM_SIZE]; 46 void *init_data; 47 uint8_t offset; 48 bool accessed; 49 } SMBusEEPROMDevice; 50 51 static uint8_t eeprom_receive_byte(SMBusDevice *dev) 52 { 53 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 54 uint8_t *data = eeprom->data; 55 uint8_t val = data[eeprom->offset++]; 56 57 eeprom->accessed = true; 58 #ifdef DEBUG 59 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", 60 dev->i2c.address, val); 61 #endif 62 return val; 63 } 64 65 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len) 66 { 67 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 68 uint8_t *data = eeprom->data; 69 70 eeprom->accessed = true; 71 #ifdef DEBUG 72 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", 73 dev->i2c.address, buf[0], buf[1]); 74 #endif 75 /* len is guaranteed to be > 0 */ 76 eeprom->offset = buf[0]; 77 buf++; 78 len--; 79 80 for (; len > 0; len--) { 81 data[eeprom->offset] = *buf++; 82 eeprom->offset = (eeprom->offset + 1) % SMBUS_EEPROM_SIZE; 83 } 84 85 return 0; 86 } 87 88 static bool smbus_eeprom_vmstate_needed(void *opaque) 89 { 90 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 91 SMBusEEPROMDevice *eeprom = opaque; 92 93 return (eeprom->accessed || smbus_vmstate_needed(&eeprom->smbusdev)) && 94 !mc->smbus_no_migration_support; 95 } 96 97 static const VMStateDescription vmstate_smbus_eeprom = { 98 .name = "smbus-eeprom", 99 .version_id = 1, 100 .minimum_version_id = 1, 101 .needed = smbus_eeprom_vmstate_needed, 102 .fields = (VMStateField[]) { 103 VMSTATE_SMBUS_DEVICE(smbusdev, SMBusEEPROMDevice), 104 VMSTATE_UINT8_ARRAY(data, SMBusEEPROMDevice, SMBUS_EEPROM_SIZE), 105 VMSTATE_UINT8(offset, SMBusEEPROMDevice), 106 VMSTATE_BOOL(accessed, SMBusEEPROMDevice), 107 VMSTATE_END_OF_LIST() 108 } 109 }; 110 111 static void smbus_eeprom_realize(DeviceState *dev, Error **errp) 112 { 113 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 114 115 memcpy(eeprom->data, eeprom->init_data, SMBUS_EEPROM_SIZE); 116 eeprom->offset = 0; 117 } 118 119 static Property smbus_eeprom_properties[] = { 120 DEFINE_PROP_PTR("data", SMBusEEPROMDevice, init_data), 121 DEFINE_PROP_END_OF_LIST(), 122 }; 123 124 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) 125 { 126 DeviceClass *dc = DEVICE_CLASS(klass); 127 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); 128 129 dc->realize = smbus_eeprom_realize; 130 sc->receive_byte = eeprom_receive_byte; 131 sc->write_data = eeprom_write_data; 132 dc->props = smbus_eeprom_properties; 133 dc->vmsd = &vmstate_smbus_eeprom; 134 /* Reason: pointer property "data" */ 135 dc->user_creatable = false; 136 } 137 138 static const TypeInfo smbus_eeprom_info = { 139 .name = TYPE_SMBUS_EEPROM, 140 .parent = TYPE_SMBUS_DEVICE, 141 .instance_size = sizeof(SMBusEEPROMDevice), 142 .class_init = smbus_eeprom_class_initfn, 143 }; 144 145 static void smbus_eeprom_register_types(void) 146 { 147 type_register_static(&smbus_eeprom_info); 148 } 149 150 type_init(smbus_eeprom_register_types) 151 152 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) 153 { 154 DeviceState *dev; 155 156 dev = qdev_create((BusState *) smbus, TYPE_SMBUS_EEPROM); 157 qdev_prop_set_uint8(dev, "address", address); 158 qdev_prop_set_ptr(dev, "data", eeprom_buf); 159 qdev_init_nofail(dev); 160 } 161 162 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, 163 const uint8_t *eeprom_spd, int eeprom_spd_size) 164 { 165 int i; 166 /* XXX: make this persistent */ 167 uint8_t *eeprom_buf = g_malloc0(8 * SMBUS_EEPROM_SIZE); 168 if (eeprom_spd_size > 0) { 169 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); 170 } 171 172 for (i = 0; i < nb_eeprom; i++) { 173 smbus_eeprom_init_one(smbus, 0x50 + i, 174 eeprom_buf + (i * SMBUS_EEPROM_SIZE)); 175 } 176 } 177 178 /* Generate SDRAM SPD EEPROM data describing a module of type and size */ 179 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size, 180 Error **errp) 181 { 182 uint8_t *spd; 183 uint8_t nbanks; 184 uint16_t density; 185 uint32_t size; 186 int min_log2, max_log2, sz_log2; 187 int i; 188 189 switch (type) { 190 case SDR: 191 min_log2 = 2; 192 max_log2 = 9; 193 break; 194 case DDR: 195 min_log2 = 5; 196 max_log2 = 12; 197 break; 198 case DDR2: 199 min_log2 = 7; 200 max_log2 = 14; 201 break; 202 default: 203 g_assert_not_reached(); 204 } 205 size = ram_size >> 20; /* work in terms of megabytes */ 206 if (size < 4) { 207 error_setg(errp, "SDRAM size is too small"); 208 return NULL; 209 } 210 sz_log2 = 31 - clz32(size); 211 size = 1U << sz_log2; 212 if (ram_size > size * MiB) { 213 error_setg(errp, "SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, " 214 "truncating to %u MB", ram_size, size); 215 } 216 if (sz_log2 < min_log2) { 217 error_setg(errp, 218 "Memory size is too small for SDRAM type, adjusting type"); 219 if (size >= 32) { 220 type = DDR; 221 min_log2 = 5; 222 max_log2 = 12; 223 } else { 224 type = SDR; 225 min_log2 = 2; 226 max_log2 = 9; 227 } 228 } 229 230 nbanks = 1; 231 while (sz_log2 > max_log2 && nbanks < 8) { 232 sz_log2--; 233 nbanks++; 234 } 235 236 if (size > (1ULL << sz_log2) * nbanks) { 237 error_setg(errp, "Memory size is too big for SDRAM, truncating"); 238 } 239 240 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */ 241 if (nbanks == 1 && sz_log2 > min_log2) { 242 sz_log2--; 243 nbanks++; 244 } 245 246 density = 1ULL << (sz_log2 - 2); 247 switch (type) { 248 case DDR2: 249 density = (density & 0xe0) | (density >> 8 & 0x1f); 250 break; 251 case DDR: 252 density = (density & 0xf8) | (density >> 8 & 0x07); 253 break; 254 case SDR: 255 default: 256 density &= 0xff; 257 break; 258 } 259 260 spd = g_malloc0(256); 261 spd[0] = 128; /* data bytes in EEPROM */ 262 spd[1] = 8; /* log2 size of EEPROM */ 263 spd[2] = type; 264 spd[3] = 13; /* row address bits */ 265 spd[4] = 10; /* column address bits */ 266 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); 267 spd[6] = 64; /* module data width */ 268 /* reserved / data width high */ 269 spd[8] = 4; /* interface voltage level */ 270 spd[9] = 0x25; /* highest CAS latency */ 271 spd[10] = 1; /* access time */ 272 /* DIMM configuration 0 = non-ECC */ 273 spd[12] = 0x82; /* refresh requirements */ 274 spd[13] = 8; /* primary SDRAM width */ 275 /* ECC SDRAM width */ 276 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ 277 spd[16] = 12; /* burst lengths supported */ 278 spd[17] = 4; /* banks per SDRAM device */ 279 spd[18] = 12; /* ~CAS latencies supported */ 280 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ 281 spd[20] = 2; /* DIMM type / ~WE latencies */ 282 /* module features */ 283 /* memory chip features */ 284 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ 285 /* data access time */ 286 /* clock cycle time @ short CAS latency */ 287 /* data access time */ 288 spd[27] = 20; /* min. row precharge time */ 289 spd[28] = 15; /* min. row active row delay */ 290 spd[29] = 20; /* min. ~RAS to ~CAS delay */ 291 spd[30] = 45; /* min. active to precharge time */ 292 spd[31] = density; 293 spd[32] = 20; /* addr/cmd setup time */ 294 spd[33] = 8; /* addr/cmd hold time */ 295 spd[34] = 20; /* data input setup time */ 296 spd[35] = 8; /* data input hold time */ 297 298 /* checksum */ 299 for (i = 0; i < 63; i++) { 300 spd[63] += spd[i]; 301 } 302 return spd; 303 } 304