1 /* 2 * QEMU SMBus EEPROM device 3 * 4 * Copyright (c) 2007 Arastra, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/i2c/i2c.h" 30 #include "hw/i2c/smbus_slave.h" 31 #include "hw/i2c/smbus_eeprom.h" 32 33 //#define DEBUG 34 35 #define TYPE_SMBUS_EEPROM "smbus-eeprom" 36 37 #define SMBUS_EEPROM(obj) \ 38 OBJECT_CHECK(SMBusEEPROMDevice, (obj), TYPE_SMBUS_EEPROM) 39 40 typedef struct SMBusEEPROMDevice { 41 SMBusDevice smbusdev; 42 void *data; 43 uint8_t offset; 44 } SMBusEEPROMDevice; 45 46 static uint8_t eeprom_receive_byte(SMBusDevice *dev) 47 { 48 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 49 uint8_t *data = eeprom->data; 50 uint8_t val = data[eeprom->offset++]; 51 52 #ifdef DEBUG 53 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", 54 dev->i2c.address, val); 55 #endif 56 return val; 57 } 58 59 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len) 60 { 61 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 62 uint8_t *data = eeprom->data; 63 64 #ifdef DEBUG 65 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", 66 dev->i2c.address, buf[0], buf[1]); 67 #endif 68 /* len is guaranteed to be > 0 */ 69 eeprom->offset = buf[0]; 70 buf++; 71 len--; 72 73 for (; len > 0; len--) { 74 data[eeprom->offset] = *buf++; 75 eeprom->offset = (eeprom->offset + 1) % 256; 76 } 77 78 return 0; 79 } 80 81 static void smbus_eeprom_realize(DeviceState *dev, Error **errp) 82 { 83 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 84 85 eeprom->offset = 0; 86 } 87 88 static Property smbus_eeprom_properties[] = { 89 DEFINE_PROP_PTR("data", SMBusEEPROMDevice, data), 90 DEFINE_PROP_END_OF_LIST(), 91 }; 92 93 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) 94 { 95 DeviceClass *dc = DEVICE_CLASS(klass); 96 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); 97 98 dc->realize = smbus_eeprom_realize; 99 sc->receive_byte = eeprom_receive_byte; 100 sc->write_data = eeprom_write_data; 101 dc->props = smbus_eeprom_properties; 102 /* Reason: pointer property "data" */ 103 dc->user_creatable = false; 104 } 105 106 static const TypeInfo smbus_eeprom_info = { 107 .name = TYPE_SMBUS_EEPROM, 108 .parent = TYPE_SMBUS_DEVICE, 109 .instance_size = sizeof(SMBusEEPROMDevice), 110 .class_init = smbus_eeprom_class_initfn, 111 }; 112 113 static void smbus_eeprom_register_types(void) 114 { 115 type_register_static(&smbus_eeprom_info); 116 } 117 118 type_init(smbus_eeprom_register_types) 119 120 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) 121 { 122 DeviceState *dev; 123 124 dev = qdev_create((BusState *) smbus, TYPE_SMBUS_EEPROM); 125 qdev_prop_set_uint8(dev, "address", address); 126 qdev_prop_set_ptr(dev, "data", eeprom_buf); 127 qdev_init_nofail(dev); 128 } 129 130 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, 131 const uint8_t *eeprom_spd, int eeprom_spd_size) 132 { 133 int i; 134 uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */ 135 if (eeprom_spd_size > 0) { 136 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); 137 } 138 139 for (i = 0; i < nb_eeprom; i++) { 140 smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256)); 141 } 142 } 143 144 /* Generate SDRAM SPD EEPROM data describing a module of type and size */ 145 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size, 146 Error **errp) 147 { 148 uint8_t *spd; 149 uint8_t nbanks; 150 uint16_t density; 151 uint32_t size; 152 int min_log2, max_log2, sz_log2; 153 int i; 154 155 switch (type) { 156 case SDR: 157 min_log2 = 2; 158 max_log2 = 9; 159 break; 160 case DDR: 161 min_log2 = 5; 162 max_log2 = 12; 163 break; 164 case DDR2: 165 min_log2 = 7; 166 max_log2 = 14; 167 break; 168 default: 169 g_assert_not_reached(); 170 } 171 size = ram_size >> 20; /* work in terms of megabytes */ 172 if (size < 4) { 173 error_setg(errp, "SDRAM size is too small"); 174 return NULL; 175 } 176 sz_log2 = 31 - clz32(size); 177 size = 1U << sz_log2; 178 if (ram_size > size * MiB) { 179 error_setg(errp, "SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, " 180 "truncating to %u MB", ram_size, size); 181 } 182 if (sz_log2 < min_log2) { 183 error_setg(errp, 184 "Memory size is too small for SDRAM type, adjusting type"); 185 if (size >= 32) { 186 type = DDR; 187 min_log2 = 5; 188 max_log2 = 12; 189 } else { 190 type = SDR; 191 min_log2 = 2; 192 max_log2 = 9; 193 } 194 } 195 196 nbanks = 1; 197 while (sz_log2 > max_log2 && nbanks < 8) { 198 sz_log2--; 199 nbanks++; 200 } 201 202 if (size > (1ULL << sz_log2) * nbanks) { 203 error_setg(errp, "Memory size is too big for SDRAM, truncating"); 204 } 205 206 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */ 207 if (nbanks == 1 && sz_log2 > min_log2) { 208 sz_log2--; 209 nbanks++; 210 } 211 212 density = 1ULL << (sz_log2 - 2); 213 switch (type) { 214 case DDR2: 215 density = (density & 0xe0) | (density >> 8 & 0x1f); 216 break; 217 case DDR: 218 density = (density & 0xf8) | (density >> 8 & 0x07); 219 break; 220 case SDR: 221 default: 222 density &= 0xff; 223 break; 224 } 225 226 spd = g_malloc0(256); 227 spd[0] = 128; /* data bytes in EEPROM */ 228 spd[1] = 8; /* log2 size of EEPROM */ 229 spd[2] = type; 230 spd[3] = 13; /* row address bits */ 231 spd[4] = 10; /* column address bits */ 232 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); 233 spd[6] = 64; /* module data width */ 234 /* reserved / data width high */ 235 spd[8] = 4; /* interface voltage level */ 236 spd[9] = 0x25; /* highest CAS latency */ 237 spd[10] = 1; /* access time */ 238 /* DIMM configuration 0 = non-ECC */ 239 spd[12] = 0x82; /* refresh requirements */ 240 spd[13] = 8; /* primary SDRAM width */ 241 /* ECC SDRAM width */ 242 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ 243 spd[16] = 12; /* burst lengths supported */ 244 spd[17] = 4; /* banks per SDRAM device */ 245 spd[18] = 12; /* ~CAS latencies supported */ 246 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ 247 spd[20] = 2; /* DIMM type / ~WE latencies */ 248 /* module features */ 249 /* memory chip features */ 250 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ 251 /* data access time */ 252 /* clock cycle time @ short CAS latency */ 253 /* data access time */ 254 spd[27] = 20; /* min. row precharge time */ 255 spd[28] = 15; /* min. row active row delay */ 256 spd[29] = 20; /* min. ~RAS to ~CAS delay */ 257 spd[30] = 45; /* min. active to precharge time */ 258 spd[31] = density; 259 spd[32] = 20; /* addr/cmd setup time */ 260 spd[33] = 8; /* addr/cmd hold time */ 261 spd[34] = 20; /* data input setup time */ 262 spd[35] = 8; /* data input hold time */ 263 264 /* checksum */ 265 for (i = 0; i < 63; i++) { 266 spd[63] += spd[i]; 267 } 268 return spd; 269 } 270