1 /* 2 * QEMU SMBus EEPROM device 3 * 4 * Copyright (c) 2007 Arastra, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/i2c/i2c.h" 30 #include "hw/i2c/smbus_slave.h" 31 #include "hw/i2c/smbus_eeprom.h" 32 33 //#define DEBUG 34 35 typedef struct SMBusEEPROMDevice { 36 SMBusDevice smbusdev; 37 void *data; 38 uint8_t offset; 39 } SMBusEEPROMDevice; 40 41 static uint8_t eeprom_receive_byte(SMBusDevice *dev) 42 { 43 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 44 uint8_t *data = eeprom->data; 45 uint8_t val = data[eeprom->offset++]; 46 47 #ifdef DEBUG 48 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", 49 dev->i2c.address, val); 50 #endif 51 return val; 52 } 53 54 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len) 55 { 56 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 57 uint8_t *data = eeprom->data; 58 59 #ifdef DEBUG 60 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", 61 dev->i2c.address, buf[0], buf[1]); 62 #endif 63 /* len is guaranteed to be > 0 */ 64 eeprom->offset = buf[0]; 65 buf++; 66 len--; 67 68 for (; len > 0; len--) { 69 data[eeprom->offset] = *buf++; 70 eeprom->offset = (eeprom->offset + 1) % 256; 71 } 72 73 return 0; 74 } 75 76 static void smbus_eeprom_realize(DeviceState *dev, Error **errp) 77 { 78 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *)dev; 79 80 eeprom->offset = 0; 81 } 82 83 static Property smbus_eeprom_properties[] = { 84 DEFINE_PROP_PTR("data", SMBusEEPROMDevice, data), 85 DEFINE_PROP_END_OF_LIST(), 86 }; 87 88 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) 89 { 90 DeviceClass *dc = DEVICE_CLASS(klass); 91 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); 92 93 dc->realize = smbus_eeprom_realize; 94 sc->receive_byte = eeprom_receive_byte; 95 sc->write_data = eeprom_write_data; 96 dc->props = smbus_eeprom_properties; 97 /* Reason: pointer property "data" */ 98 dc->user_creatable = false; 99 } 100 101 static const TypeInfo smbus_eeprom_info = { 102 .name = "smbus-eeprom", 103 .parent = TYPE_SMBUS_DEVICE, 104 .instance_size = sizeof(SMBusEEPROMDevice), 105 .class_init = smbus_eeprom_class_initfn, 106 }; 107 108 static void smbus_eeprom_register_types(void) 109 { 110 type_register_static(&smbus_eeprom_info); 111 } 112 113 type_init(smbus_eeprom_register_types) 114 115 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) 116 { 117 DeviceState *dev; 118 119 dev = qdev_create((BusState *) smbus, "smbus-eeprom"); 120 qdev_prop_set_uint8(dev, "address", address); 121 qdev_prop_set_ptr(dev, "data", eeprom_buf); 122 qdev_init_nofail(dev); 123 } 124 125 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, 126 const uint8_t *eeprom_spd, int eeprom_spd_size) 127 { 128 int i; 129 uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */ 130 if (eeprom_spd_size > 0) { 131 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); 132 } 133 134 for (i = 0; i < nb_eeprom; i++) { 135 smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256)); 136 } 137 } 138 139 /* Generate SDRAM SPD EEPROM data describing a module of type and size */ 140 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size, 141 Error **errp) 142 { 143 uint8_t *spd; 144 uint8_t nbanks; 145 uint16_t density; 146 uint32_t size; 147 int min_log2, max_log2, sz_log2; 148 int i; 149 150 switch (type) { 151 case SDR: 152 min_log2 = 2; 153 max_log2 = 9; 154 break; 155 case DDR: 156 min_log2 = 5; 157 max_log2 = 12; 158 break; 159 case DDR2: 160 min_log2 = 7; 161 max_log2 = 14; 162 break; 163 default: 164 g_assert_not_reached(); 165 } 166 size = ram_size >> 20; /* work in terms of megabytes */ 167 if (size < 4) { 168 error_setg(errp, "SDRAM size is too small"); 169 return NULL; 170 } 171 sz_log2 = 31 - clz32(size); 172 size = 1U << sz_log2; 173 if (ram_size > size * MiB) { 174 error_setg(errp, "SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, " 175 "truncating to %u MB", ram_size, size); 176 } 177 if (sz_log2 < min_log2) { 178 error_setg(errp, 179 "Memory size is too small for SDRAM type, adjusting type"); 180 if (size >= 32) { 181 type = DDR; 182 min_log2 = 5; 183 max_log2 = 12; 184 } else { 185 type = SDR; 186 min_log2 = 2; 187 max_log2 = 9; 188 } 189 } 190 191 nbanks = 1; 192 while (sz_log2 > max_log2 && nbanks < 8) { 193 sz_log2--; 194 nbanks++; 195 } 196 197 if (size > (1ULL << sz_log2) * nbanks) { 198 error_setg(errp, "Memory size is too big for SDRAM, truncating"); 199 } 200 201 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */ 202 if (nbanks == 1 && sz_log2 > min_log2) { 203 sz_log2--; 204 nbanks++; 205 } 206 207 density = 1ULL << (sz_log2 - 2); 208 switch (type) { 209 case DDR2: 210 density = (density & 0xe0) | (density >> 8 & 0x1f); 211 break; 212 case DDR: 213 density = (density & 0xf8) | (density >> 8 & 0x07); 214 break; 215 case SDR: 216 default: 217 density &= 0xff; 218 break; 219 } 220 221 spd = g_malloc0(256); 222 spd[0] = 128; /* data bytes in EEPROM */ 223 spd[1] = 8; /* log2 size of EEPROM */ 224 spd[2] = type; 225 spd[3] = 13; /* row address bits */ 226 spd[4] = 10; /* column address bits */ 227 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); 228 spd[6] = 64; /* module data width */ 229 /* reserved / data width high */ 230 spd[8] = 4; /* interface voltage level */ 231 spd[9] = 0x25; /* highest CAS latency */ 232 spd[10] = 1; /* access time */ 233 /* DIMM configuration 0 = non-ECC */ 234 spd[12] = 0x82; /* refresh requirements */ 235 spd[13] = 8; /* primary SDRAM width */ 236 /* ECC SDRAM width */ 237 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ 238 spd[16] = 12; /* burst lengths supported */ 239 spd[17] = 4; /* banks per SDRAM device */ 240 spd[18] = 12; /* ~CAS latencies supported */ 241 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ 242 spd[20] = 2; /* DIMM type / ~WE latencies */ 243 /* module features */ 244 /* memory chip features */ 245 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ 246 /* data access time */ 247 /* clock cycle time @ short CAS latency */ 248 /* data access time */ 249 spd[27] = 20; /* min. row precharge time */ 250 spd[28] = 15; /* min. row active row delay */ 251 spd[29] = 20; /* min. ~RAS to ~CAS delay */ 252 spd[30] = 45; /* min. active to precharge time */ 253 spd[31] = density; 254 spd[32] = 20; /* addr/cmd setup time */ 255 spd[33] = 8; /* addr/cmd hold time */ 256 spd[34] = 20; /* data input setup time */ 257 spd[35] = 8; /* data input hold time */ 258 259 /* checksum */ 260 for (i = 0; i < 63; i++) { 261 spd[63] += spd[i]; 262 } 263 return spd; 264 } 265