1 /* 2 * QEMU SMBus EEPROM device 3 * 4 * Copyright (c) 2007 Arastra, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/i2c/i2c.h" 30 #include "hw/i2c/smbus_slave.h" 31 #include "hw/i2c/smbus_eeprom.h" 32 33 //#define DEBUG 34 35 #define TYPE_SMBUS_EEPROM "smbus-eeprom" 36 37 #define SMBUS_EEPROM(obj) \ 38 OBJECT_CHECK(SMBusEEPROMDevice, (obj), TYPE_SMBUS_EEPROM) 39 40 #define SMBUS_EEPROM_SIZE 256 41 42 typedef struct SMBusEEPROMDevice { 43 SMBusDevice smbusdev; 44 void *data; 45 uint8_t offset; 46 } SMBusEEPROMDevice; 47 48 static uint8_t eeprom_receive_byte(SMBusDevice *dev) 49 { 50 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 51 uint8_t *data = eeprom->data; 52 uint8_t val = data[eeprom->offset++]; 53 54 #ifdef DEBUG 55 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", 56 dev->i2c.address, val); 57 #endif 58 return val; 59 } 60 61 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len) 62 { 63 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 64 uint8_t *data = eeprom->data; 65 66 #ifdef DEBUG 67 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", 68 dev->i2c.address, buf[0], buf[1]); 69 #endif 70 /* len is guaranteed to be > 0 */ 71 eeprom->offset = buf[0]; 72 buf++; 73 len--; 74 75 for (; len > 0; len--) { 76 data[eeprom->offset] = *buf++; 77 eeprom->offset = (eeprom->offset + 1) % SMBUS_EEPROM_SIZE; 78 } 79 80 return 0; 81 } 82 83 static void smbus_eeprom_realize(DeviceState *dev, Error **errp) 84 { 85 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 86 87 eeprom->offset = 0; 88 } 89 90 static Property smbus_eeprom_properties[] = { 91 DEFINE_PROP_PTR("data", SMBusEEPROMDevice, data), 92 DEFINE_PROP_END_OF_LIST(), 93 }; 94 95 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) 96 { 97 DeviceClass *dc = DEVICE_CLASS(klass); 98 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); 99 100 dc->realize = smbus_eeprom_realize; 101 sc->receive_byte = eeprom_receive_byte; 102 sc->write_data = eeprom_write_data; 103 dc->props = smbus_eeprom_properties; 104 /* Reason: pointer property "data" */ 105 dc->user_creatable = false; 106 } 107 108 static const TypeInfo smbus_eeprom_info = { 109 .name = TYPE_SMBUS_EEPROM, 110 .parent = TYPE_SMBUS_DEVICE, 111 .instance_size = sizeof(SMBusEEPROMDevice), 112 .class_init = smbus_eeprom_class_initfn, 113 }; 114 115 static void smbus_eeprom_register_types(void) 116 { 117 type_register_static(&smbus_eeprom_info); 118 } 119 120 type_init(smbus_eeprom_register_types) 121 122 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) 123 { 124 DeviceState *dev; 125 126 dev = qdev_create((BusState *) smbus, TYPE_SMBUS_EEPROM); 127 qdev_prop_set_uint8(dev, "address", address); 128 qdev_prop_set_ptr(dev, "data", eeprom_buf); 129 qdev_init_nofail(dev); 130 } 131 132 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, 133 const uint8_t *eeprom_spd, int eeprom_spd_size) 134 { 135 int i; 136 /* XXX: make this persistent */ 137 uint8_t *eeprom_buf = g_malloc0(8 * SMBUS_EEPROM_SIZE); 138 if (eeprom_spd_size > 0) { 139 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); 140 } 141 142 for (i = 0; i < nb_eeprom; i++) { 143 smbus_eeprom_init_one(smbus, 0x50 + i, 144 eeprom_buf + (i * SMBUS_EEPROM_SIZE)); 145 } 146 } 147 148 /* Generate SDRAM SPD EEPROM data describing a module of type and size */ 149 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size, 150 Error **errp) 151 { 152 uint8_t *spd; 153 uint8_t nbanks; 154 uint16_t density; 155 uint32_t size; 156 int min_log2, max_log2, sz_log2; 157 int i; 158 159 switch (type) { 160 case SDR: 161 min_log2 = 2; 162 max_log2 = 9; 163 break; 164 case DDR: 165 min_log2 = 5; 166 max_log2 = 12; 167 break; 168 case DDR2: 169 min_log2 = 7; 170 max_log2 = 14; 171 break; 172 default: 173 g_assert_not_reached(); 174 } 175 size = ram_size >> 20; /* work in terms of megabytes */ 176 if (size < 4) { 177 error_setg(errp, "SDRAM size is too small"); 178 return NULL; 179 } 180 sz_log2 = 31 - clz32(size); 181 size = 1U << sz_log2; 182 if (ram_size > size * MiB) { 183 error_setg(errp, "SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, " 184 "truncating to %u MB", ram_size, size); 185 } 186 if (sz_log2 < min_log2) { 187 error_setg(errp, 188 "Memory size is too small for SDRAM type, adjusting type"); 189 if (size >= 32) { 190 type = DDR; 191 min_log2 = 5; 192 max_log2 = 12; 193 } else { 194 type = SDR; 195 min_log2 = 2; 196 max_log2 = 9; 197 } 198 } 199 200 nbanks = 1; 201 while (sz_log2 > max_log2 && nbanks < 8) { 202 sz_log2--; 203 nbanks++; 204 } 205 206 if (size > (1ULL << sz_log2) * nbanks) { 207 error_setg(errp, "Memory size is too big for SDRAM, truncating"); 208 } 209 210 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */ 211 if (nbanks == 1 && sz_log2 > min_log2) { 212 sz_log2--; 213 nbanks++; 214 } 215 216 density = 1ULL << (sz_log2 - 2); 217 switch (type) { 218 case DDR2: 219 density = (density & 0xe0) | (density >> 8 & 0x1f); 220 break; 221 case DDR: 222 density = (density & 0xf8) | (density >> 8 & 0x07); 223 break; 224 case SDR: 225 default: 226 density &= 0xff; 227 break; 228 } 229 230 spd = g_malloc0(256); 231 spd[0] = 128; /* data bytes in EEPROM */ 232 spd[1] = 8; /* log2 size of EEPROM */ 233 spd[2] = type; 234 spd[3] = 13; /* row address bits */ 235 spd[4] = 10; /* column address bits */ 236 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); 237 spd[6] = 64; /* module data width */ 238 /* reserved / data width high */ 239 spd[8] = 4; /* interface voltage level */ 240 spd[9] = 0x25; /* highest CAS latency */ 241 spd[10] = 1; /* access time */ 242 /* DIMM configuration 0 = non-ECC */ 243 spd[12] = 0x82; /* refresh requirements */ 244 spd[13] = 8; /* primary SDRAM width */ 245 /* ECC SDRAM width */ 246 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ 247 spd[16] = 12; /* burst lengths supported */ 248 spd[17] = 4; /* banks per SDRAM device */ 249 spd[18] = 12; /* ~CAS latencies supported */ 250 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ 251 spd[20] = 2; /* DIMM type / ~WE latencies */ 252 /* module features */ 253 /* memory chip features */ 254 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ 255 /* data access time */ 256 /* clock cycle time @ short CAS latency */ 257 /* data access time */ 258 spd[27] = 20; /* min. row precharge time */ 259 spd[28] = 15; /* min. row active row delay */ 260 spd[29] = 20; /* min. ~RAS to ~CAS delay */ 261 spd[30] = 45; /* min. active to precharge time */ 262 spd[31] = density; 263 spd[32] = 20; /* addr/cmd setup time */ 264 spd[33] = 8; /* addr/cmd hold time */ 265 spd[34] = 20; /* data input setup time */ 266 spd[35] = 8; /* data input hold time */ 267 268 /* checksum */ 269 for (i = 0; i < 63; i++) { 270 spd[63] += spd[i]; 271 } 272 return spd; 273 } 274