1 /* 2 * QEMU SMBus EEPROM device 3 * 4 * Copyright (c) 2007 Arastra, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/i2c/i2c.h" 30 #include "hw/i2c/smbus.h" 31 32 //#define DEBUG 33 34 typedef struct SMBusEEPROMDevice { 35 SMBusDevice smbusdev; 36 void *data; 37 uint8_t offset; 38 } SMBusEEPROMDevice; 39 40 static void eeprom_quick_cmd(SMBusDevice *dev, uint8_t read) 41 { 42 #ifdef DEBUG 43 printf("eeprom_quick_cmd: addr=0x%02x read=%d\n", dev->i2c.address, read); 44 #endif 45 } 46 47 static void eeprom_send_byte(SMBusDevice *dev, uint8_t val) 48 { 49 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 50 #ifdef DEBUG 51 printf("eeprom_send_byte: addr=0x%02x val=0x%02x\n", 52 dev->i2c.address, val); 53 #endif 54 eeprom->offset = val; 55 } 56 57 static uint8_t eeprom_receive_byte(SMBusDevice *dev) 58 { 59 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 60 uint8_t *data = eeprom->data; 61 uint8_t val = data[eeprom->offset++]; 62 #ifdef DEBUG 63 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", 64 dev->i2c.address, val); 65 #endif 66 return val; 67 } 68 69 static void eeprom_write_data(SMBusDevice *dev, uint8_t cmd, uint8_t *buf, int len) 70 { 71 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 72 int n; 73 #ifdef DEBUG 74 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", 75 dev->i2c.address, cmd, buf[0]); 76 #endif 77 /* A page write operation is not a valid SMBus command. 78 It is a block write without a length byte. Fortunately we 79 get the full block anyway. */ 80 /* TODO: Should this set the current location? */ 81 if (cmd + len > 256) 82 n = 256 - cmd; 83 else 84 n = len; 85 memcpy(eeprom->data + cmd, buf, n); 86 len -= n; 87 if (len) 88 memcpy(eeprom->data, buf + n, len); 89 } 90 91 static uint8_t eeprom_read_data(SMBusDevice *dev, uint8_t cmd, int n) 92 { 93 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 94 /* If this is the first byte then set the current position. */ 95 if (n == 0) 96 eeprom->offset = cmd; 97 /* As with writes, we implement block reads without the 98 SMBus length byte. */ 99 return eeprom_receive_byte(dev); 100 } 101 102 static void smbus_eeprom_realize(DeviceState *dev, Error **errp) 103 { 104 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *)dev; 105 106 eeprom->offset = 0; 107 } 108 109 static Property smbus_eeprom_properties[] = { 110 DEFINE_PROP_PTR("data", SMBusEEPROMDevice, data), 111 DEFINE_PROP_END_OF_LIST(), 112 }; 113 114 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) 115 { 116 DeviceClass *dc = DEVICE_CLASS(klass); 117 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); 118 119 dc->realize = smbus_eeprom_realize; 120 sc->quick_cmd = eeprom_quick_cmd; 121 sc->send_byte = eeprom_send_byte; 122 sc->receive_byte = eeprom_receive_byte; 123 sc->write_data = eeprom_write_data; 124 sc->read_data = eeprom_read_data; 125 dc->props = smbus_eeprom_properties; 126 /* Reason: pointer property "data" */ 127 dc->user_creatable = false; 128 } 129 130 static const TypeInfo smbus_eeprom_info = { 131 .name = "smbus-eeprom", 132 .parent = TYPE_SMBUS_DEVICE, 133 .instance_size = sizeof(SMBusEEPROMDevice), 134 .class_init = smbus_eeprom_class_initfn, 135 }; 136 137 static void smbus_eeprom_register_types(void) 138 { 139 type_register_static(&smbus_eeprom_info); 140 } 141 142 type_init(smbus_eeprom_register_types) 143 144 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) 145 { 146 DeviceState *dev; 147 148 dev = qdev_create((BusState *) smbus, "smbus-eeprom"); 149 qdev_prop_set_uint8(dev, "address", address); 150 qdev_prop_set_ptr(dev, "data", eeprom_buf); 151 qdev_init_nofail(dev); 152 } 153 154 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, 155 const uint8_t *eeprom_spd, int eeprom_spd_size) 156 { 157 int i; 158 uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */ 159 if (eeprom_spd_size > 0) { 160 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); 161 } 162 163 for (i = 0; i < nb_eeprom; i++) { 164 smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256)); 165 } 166 } 167 168 /* Generate SDRAM SPD EEPROM data describing a module of type and size */ 169 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size, 170 Error **errp) 171 { 172 uint8_t *spd; 173 uint8_t nbanks; 174 uint16_t density; 175 uint32_t size; 176 int min_log2, max_log2, sz_log2; 177 int i; 178 179 switch (type) { 180 case SDR: 181 min_log2 = 2; 182 max_log2 = 9; 183 break; 184 case DDR: 185 min_log2 = 5; 186 max_log2 = 12; 187 break; 188 case DDR2: 189 min_log2 = 7; 190 max_log2 = 14; 191 break; 192 default: 193 g_assert_not_reached(); 194 } 195 size = ram_size >> 20; /* work in terms of megabytes */ 196 if (size < 4) { 197 error_setg(errp, "SDRAM size is too small"); 198 return NULL; 199 } 200 sz_log2 = 31 - clz32(size); 201 size = 1U << sz_log2; 202 if (ram_size > size * MiB) { 203 error_setg(errp, "SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, " 204 "truncating to %u MB", ram_size, size); 205 } 206 if (sz_log2 < min_log2) { 207 error_setg(errp, 208 "Memory size is too small for SDRAM type, adjusting type"); 209 if (size >= 32) { 210 type = DDR; 211 min_log2 = 5; 212 max_log2 = 12; 213 } else { 214 type = SDR; 215 min_log2 = 2; 216 max_log2 = 9; 217 } 218 } 219 220 nbanks = 1; 221 while (sz_log2 > max_log2 && nbanks < 8) { 222 sz_log2--; 223 nbanks++; 224 } 225 226 if (size > (1ULL << sz_log2) * nbanks) { 227 error_setg(errp, "Memory size is too big for SDRAM, truncating"); 228 } 229 230 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */ 231 if (nbanks == 1 && sz_log2 > min_log2) { 232 sz_log2--; 233 nbanks++; 234 } 235 236 density = 1ULL << (sz_log2 - 2); 237 switch (type) { 238 case DDR2: 239 density = (density & 0xe0) | (density >> 8 & 0x1f); 240 break; 241 case DDR: 242 density = (density & 0xf8) | (density >> 8 & 0x07); 243 break; 244 case SDR: 245 default: 246 density &= 0xff; 247 break; 248 } 249 250 spd = g_malloc0(256); 251 spd[0] = 128; /* data bytes in EEPROM */ 252 spd[1] = 8; /* log2 size of EEPROM */ 253 spd[2] = type; 254 spd[3] = 13; /* row address bits */ 255 spd[4] = 10; /* column address bits */ 256 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); 257 spd[6] = 64; /* module data width */ 258 /* reserved / data width high */ 259 spd[8] = 4; /* interface voltage level */ 260 spd[9] = 0x25; /* highest CAS latency */ 261 spd[10] = 1; /* access time */ 262 /* DIMM configuration 0 = non-ECC */ 263 spd[12] = 0x82; /* refresh requirements */ 264 spd[13] = 8; /* primary SDRAM width */ 265 /* ECC SDRAM width */ 266 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ 267 spd[16] = 12; /* burst lengths supported */ 268 spd[17] = 4; /* banks per SDRAM device */ 269 spd[18] = 12; /* ~CAS latencies supported */ 270 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ 271 spd[20] = 2; /* DIMM type / ~WE latencies */ 272 /* module features */ 273 /* memory chip features */ 274 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ 275 /* data access time */ 276 /* clock cycle time @ short CAS latency */ 277 /* data access time */ 278 spd[27] = 20; /* min. row precharge time */ 279 spd[28] = 15; /* min. row active row delay */ 280 spd[29] = 20; /* min. ~RAS to ~CAS delay */ 281 spd[30] = 45; /* min. active to precharge time */ 282 spd[31] = density; 283 spd[32] = 20; /* addr/cmd setup time */ 284 spd[33] = 8; /* addr/cmd hold time */ 285 spd[34] = 20; /* data input setup time */ 286 spd[35] = 8; /* data input hold time */ 287 288 /* checksum */ 289 for (i = 0; i < 63; i++) { 290 spd[63] += spd[i]; 291 } 292 return spd; 293 } 294