1 /* 2 * QEMU SMBus EEPROM device 3 * 4 * Copyright (c) 2007 Arastra, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/i2c/i2c.h" 30 #include "hw/i2c/smbus_slave.h" 31 #include "hw/i2c/smbus_eeprom.h" 32 33 //#define DEBUG 34 35 typedef struct SMBusEEPROMDevice { 36 SMBusDevice smbusdev; 37 void *data; 38 uint8_t offset; 39 } SMBusEEPROMDevice; 40 41 static uint8_t eeprom_receive_byte(SMBusDevice *dev) 42 { 43 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 44 uint8_t *data = eeprom->data; 45 uint8_t val = data[eeprom->offset++]; 46 #ifdef DEBUG 47 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", 48 dev->i2c.address, val); 49 #endif 50 return val; 51 } 52 53 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len) 54 { 55 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 56 uint8_t *data = eeprom->data; 57 58 #ifdef DEBUG 59 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", 60 dev->i2c.address, buf[0], buf[1]); 61 #endif 62 /* len is guaranteed to be > 0 */ 63 eeprom->offset = buf[0]; 64 buf++; 65 len--; 66 67 for (; len > 0; len--) { 68 data[eeprom->offset] = *buf++; 69 eeprom->offset = (eeprom->offset + 1) % 256; 70 } 71 72 return 0; 73 } 74 75 static void smbus_eeprom_realize(DeviceState *dev, Error **errp) 76 { 77 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *)dev; 78 79 eeprom->offset = 0; 80 } 81 82 static Property smbus_eeprom_properties[] = { 83 DEFINE_PROP_PTR("data", SMBusEEPROMDevice, data), 84 DEFINE_PROP_END_OF_LIST(), 85 }; 86 87 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) 88 { 89 DeviceClass *dc = DEVICE_CLASS(klass); 90 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); 91 92 dc->realize = smbus_eeprom_realize; 93 sc->receive_byte = eeprom_receive_byte; 94 sc->write_data = eeprom_write_data; 95 dc->props = smbus_eeprom_properties; 96 /* Reason: pointer property "data" */ 97 dc->user_creatable = false; 98 } 99 100 static const TypeInfo smbus_eeprom_info = { 101 .name = "smbus-eeprom", 102 .parent = TYPE_SMBUS_DEVICE, 103 .instance_size = sizeof(SMBusEEPROMDevice), 104 .class_init = smbus_eeprom_class_initfn, 105 }; 106 107 static void smbus_eeprom_register_types(void) 108 { 109 type_register_static(&smbus_eeprom_info); 110 } 111 112 type_init(smbus_eeprom_register_types) 113 114 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) 115 { 116 DeviceState *dev; 117 118 dev = qdev_create((BusState *) smbus, "smbus-eeprom"); 119 qdev_prop_set_uint8(dev, "address", address); 120 qdev_prop_set_ptr(dev, "data", eeprom_buf); 121 qdev_init_nofail(dev); 122 } 123 124 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, 125 const uint8_t *eeprom_spd, int eeprom_spd_size) 126 { 127 int i; 128 uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */ 129 if (eeprom_spd_size > 0) { 130 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); 131 } 132 133 for (i = 0; i < nb_eeprom; i++) { 134 smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256)); 135 } 136 } 137 138 /* Generate SDRAM SPD EEPROM data describing a module of type and size */ 139 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size, 140 Error **errp) 141 { 142 uint8_t *spd; 143 uint8_t nbanks; 144 uint16_t density; 145 uint32_t size; 146 int min_log2, max_log2, sz_log2; 147 int i; 148 149 switch (type) { 150 case SDR: 151 min_log2 = 2; 152 max_log2 = 9; 153 break; 154 case DDR: 155 min_log2 = 5; 156 max_log2 = 12; 157 break; 158 case DDR2: 159 min_log2 = 7; 160 max_log2 = 14; 161 break; 162 default: 163 g_assert_not_reached(); 164 } 165 size = ram_size >> 20; /* work in terms of megabytes */ 166 if (size < 4) { 167 error_setg(errp, "SDRAM size is too small"); 168 return NULL; 169 } 170 sz_log2 = 31 - clz32(size); 171 size = 1U << sz_log2; 172 if (ram_size > size * MiB) { 173 error_setg(errp, "SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, " 174 "truncating to %u MB", ram_size, size); 175 } 176 if (sz_log2 < min_log2) { 177 error_setg(errp, 178 "Memory size is too small for SDRAM type, adjusting type"); 179 if (size >= 32) { 180 type = DDR; 181 min_log2 = 5; 182 max_log2 = 12; 183 } else { 184 type = SDR; 185 min_log2 = 2; 186 max_log2 = 9; 187 } 188 } 189 190 nbanks = 1; 191 while (sz_log2 > max_log2 && nbanks < 8) { 192 sz_log2--; 193 nbanks++; 194 } 195 196 if (size > (1ULL << sz_log2) * nbanks) { 197 error_setg(errp, "Memory size is too big for SDRAM, truncating"); 198 } 199 200 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */ 201 if (nbanks == 1 && sz_log2 > min_log2) { 202 sz_log2--; 203 nbanks++; 204 } 205 206 density = 1ULL << (sz_log2 - 2); 207 switch (type) { 208 case DDR2: 209 density = (density & 0xe0) | (density >> 8 & 0x1f); 210 break; 211 case DDR: 212 density = (density & 0xf8) | (density >> 8 & 0x07); 213 break; 214 case SDR: 215 default: 216 density &= 0xff; 217 break; 218 } 219 220 spd = g_malloc0(256); 221 spd[0] = 128; /* data bytes in EEPROM */ 222 spd[1] = 8; /* log2 size of EEPROM */ 223 spd[2] = type; 224 spd[3] = 13; /* row address bits */ 225 spd[4] = 10; /* column address bits */ 226 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); 227 spd[6] = 64; /* module data width */ 228 /* reserved / data width high */ 229 spd[8] = 4; /* interface voltage level */ 230 spd[9] = 0x25; /* highest CAS latency */ 231 spd[10] = 1; /* access time */ 232 /* DIMM configuration 0 = non-ECC */ 233 spd[12] = 0x82; /* refresh requirements */ 234 spd[13] = 8; /* primary SDRAM width */ 235 /* ECC SDRAM width */ 236 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ 237 spd[16] = 12; /* burst lengths supported */ 238 spd[17] = 4; /* banks per SDRAM device */ 239 spd[18] = 12; /* ~CAS latencies supported */ 240 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ 241 spd[20] = 2; /* DIMM type / ~WE latencies */ 242 /* module features */ 243 /* memory chip features */ 244 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ 245 /* data access time */ 246 /* clock cycle time @ short CAS latency */ 247 /* data access time */ 248 spd[27] = 20; /* min. row precharge time */ 249 spd[28] = 15; /* min. row active row delay */ 250 spd[29] = 20; /* min. ~RAS to ~CAS delay */ 251 spd[30] = 45; /* min. active to precharge time */ 252 spd[31] = density; 253 spd[32] = 20; /* addr/cmd setup time */ 254 spd[33] = 8; /* addr/cmd hold time */ 255 spd[34] = 20; /* data input setup time */ 256 spd[35] = 8; /* data input hold time */ 257 258 /* checksum */ 259 for (i = 0; i < 63; i++) { 260 spd[63] += spd[i]; 261 } 262 return spd; 263 } 264