1 /* 2 * PPC4xx I2C controller emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * Copyright (c) 2012 François Revol 6 * Copyright (c) 2016 BALATON Zoltan 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/log.h" 30 #include "cpu.h" 31 #include "hw/hw.h" 32 #include "hw/i2c/ppc4xx_i2c.h" 33 34 #define PPC4xx_I2C_MEM_SIZE 0x12 35 36 #define IIC_CNTL_PT (1 << 0) 37 #define IIC_CNTL_READ (1 << 1) 38 #define IIC_CNTL_CHT (1 << 2) 39 #define IIC_CNTL_RPST (1 << 3) 40 41 #define IIC_STS_PT (1 << 0) 42 #define IIC_STS_ERR (1 << 2) 43 #define IIC_STS_MDBS (1 << 5) 44 45 #define IIC_EXTSTS_XFRA (1 << 0) 46 47 #define IIC_XTCNTLSS_SRST (1 << 0) 48 49 static void ppc4xx_i2c_reset(DeviceState *s) 50 { 51 PPC4xxI2CState *i2c = PPC4xx_I2C(s); 52 53 /* FIXME: Should also reset bus? 54 *if (s->address != ADDR_RESET) { 55 * i2c_end_transfer(s->bus); 56 *} 57 */ 58 59 i2c->mdata = 0; 60 i2c->lmadr = 0; 61 i2c->hmadr = 0; 62 i2c->cntl = 0; 63 i2c->mdcntl = 0; 64 i2c->sts = 0; 65 i2c->extsts = 0x8f; 66 i2c->sdata = 0; 67 i2c->lsadr = 0; 68 i2c->hsadr = 0; 69 i2c->clkdiv = 0; 70 i2c->intrmsk = 0; 71 i2c->xfrcnt = 0; 72 i2c->xtcntlss = 0; 73 i2c->directcntl = 0x0f; 74 i2c->intr = 0; 75 } 76 77 static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c) 78 { 79 return true; 80 } 81 82 static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size) 83 { 84 PPC4xxI2CState *i2c = PPC4xx_I2C(opaque); 85 uint64_t ret; 86 87 switch (addr) { 88 case 0x00: 89 ret = i2c->mdata; 90 if (ppc4xx_i2c_is_master(i2c)) { 91 ret = 0xff; 92 93 if (!(i2c->sts & IIC_STS_MDBS)) { 94 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read " 95 "without starting transfer\n", 96 TYPE_PPC4xx_I2C, __func__); 97 } else { 98 int pending = (i2c->cntl >> 4) & 3; 99 100 /* get the next byte */ 101 int byte = i2c_recv(i2c->bus); 102 103 if (byte < 0) { 104 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed " 105 "for device 0x%02x\n", TYPE_PPC4xx_I2C, 106 __func__, i2c->lmadr); 107 ret = 0xff; 108 } else { 109 ret = byte; 110 /* Raise interrupt if enabled */ 111 /*ppc4xx_i2c_raise_interrupt(i2c)*/; 112 } 113 114 if (!pending) { 115 i2c->sts &= ~IIC_STS_MDBS; 116 /*i2c_end_transfer(i2c->bus);*/ 117 /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/ 118 } else if (pending) { 119 /* current smbus implementation doesn't like 120 multibyte xfer repeated start */ 121 i2c_end_transfer(i2c->bus); 122 if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) { 123 /* if non zero is returned, the adress is not valid */ 124 i2c->sts &= ~IIC_STS_PT; 125 i2c->sts |= IIC_STS_ERR; 126 i2c->extsts |= IIC_EXTSTS_XFRA; 127 } else { 128 /*i2c->sts |= IIC_STS_PT;*/ 129 i2c->sts |= IIC_STS_MDBS; 130 i2c->sts &= ~IIC_STS_ERR; 131 i2c->extsts = 0; 132 } 133 } 134 pending--; 135 i2c->cntl = (i2c->cntl & 0xcf) | (pending << 4); 136 } 137 } else { 138 qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n", 139 TYPE_PPC4xx_I2C, __func__); 140 } 141 break; 142 case 0x02: 143 ret = i2c->sdata; 144 break; 145 case 0x04: 146 ret = i2c->lmadr; 147 break; 148 case 0x05: 149 ret = i2c->hmadr; 150 break; 151 case 0x06: 152 ret = i2c->cntl; 153 break; 154 case 0x07: 155 ret = i2c->mdcntl; 156 break; 157 case 0x08: 158 ret = i2c->sts; 159 break; 160 case 0x09: 161 ret = i2c->extsts; 162 break; 163 case 0x0A: 164 ret = i2c->lsadr; 165 break; 166 case 0x0B: 167 ret = i2c->hsadr; 168 break; 169 case 0x0C: 170 ret = i2c->clkdiv; 171 break; 172 case 0x0D: 173 ret = i2c->intrmsk; 174 break; 175 case 0x0E: 176 ret = i2c->xfrcnt; 177 break; 178 case 0x0F: 179 ret = i2c->xtcntlss; 180 break; 181 case 0x10: 182 ret = i2c->directcntl; 183 break; 184 case 0x11: 185 ret = i2c->intr; 186 break; 187 default: 188 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" 189 HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr); 190 ret = 0; 191 break; 192 } 193 194 return ret; 195 } 196 197 static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, 198 unsigned int size) 199 { 200 PPC4xxI2CState *i2c = opaque; 201 202 switch (addr) { 203 case 0x00: 204 i2c->mdata = value; 205 if (!i2c_bus_busy(i2c->bus)) { 206 /* assume we start a write transfer */ 207 if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 0)) { 208 /* if non zero is returned, the adress is not valid */ 209 i2c->sts &= ~IIC_STS_PT; 210 i2c->sts |= IIC_STS_ERR; 211 i2c->extsts |= IIC_EXTSTS_XFRA; 212 } else { 213 i2c->sts |= IIC_STS_PT; 214 i2c->sts &= ~IIC_STS_ERR; 215 i2c->extsts = 0; 216 } 217 } 218 if (i2c_bus_busy(i2c->bus)) { 219 if (i2c_send(i2c->bus, i2c->mdata)) { 220 /* if the target return non zero then end the transfer */ 221 i2c->sts &= ~IIC_STS_PT; 222 i2c->sts |= IIC_STS_ERR; 223 i2c->extsts |= IIC_EXTSTS_XFRA; 224 i2c_end_transfer(i2c->bus); 225 } 226 } 227 break; 228 case 0x02: 229 i2c->sdata = value; 230 break; 231 case 0x04: 232 i2c->lmadr = value; 233 if (i2c_bus_busy(i2c->bus)) { 234 i2c_end_transfer(i2c->bus); 235 } 236 break; 237 case 0x05: 238 i2c->hmadr = value; 239 break; 240 case 0x06: 241 i2c->cntl = value; 242 if (i2c->cntl & IIC_CNTL_PT) { 243 if (i2c->cntl & IIC_CNTL_READ) { 244 if (i2c_bus_busy(i2c->bus)) { 245 /* end previous transfer */ 246 i2c->sts &= ~IIC_STS_PT; 247 i2c_end_transfer(i2c->bus); 248 } 249 if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) { 250 /* if non zero is returned, the adress is not valid */ 251 i2c->sts &= ~IIC_STS_PT; 252 i2c->sts |= IIC_STS_ERR; 253 i2c->extsts |= IIC_EXTSTS_XFRA; 254 } else { 255 /*i2c->sts |= IIC_STS_PT;*/ 256 i2c->sts |= IIC_STS_MDBS; 257 i2c->sts &= ~IIC_STS_ERR; 258 i2c->extsts = 0; 259 } 260 } else { 261 /* we actually already did the write transfer... */ 262 i2c->sts &= ~IIC_STS_PT; 263 } 264 } 265 break; 266 case 0x07: 267 i2c->mdcntl = value & 0xDF; 268 break; 269 case 0x08: 270 i2c->sts &= ~(value & 0x0A); 271 break; 272 case 0x09: 273 i2c->extsts &= ~(value & 0x8F); 274 break; 275 case 0x0A: 276 i2c->lsadr = value; 277 /*i2c_set_slave_address(i2c->bus, i2c->lsadr);*/ 278 break; 279 case 0x0B: 280 i2c->hsadr = value; 281 break; 282 case 0x0C: 283 i2c->clkdiv = value; 284 break; 285 case 0x0D: 286 i2c->intrmsk = value; 287 break; 288 case 0x0E: 289 i2c->xfrcnt = value & 0x77; 290 break; 291 case 0x0F: 292 if (value & IIC_XTCNTLSS_SRST) { 293 /* Is it actually a full reset? U-Boot sets some regs before */ 294 ppc4xx_i2c_reset(DEVICE(i2c)); 295 break; 296 } 297 i2c->xtcntlss = value; 298 break; 299 case 0x10: 300 i2c->directcntl = value & 0x7; 301 break; 302 case 0x11: 303 i2c->intr = value; 304 break; 305 default: 306 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" 307 HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr); 308 break; 309 } 310 } 311 312 static const MemoryRegionOps ppc4xx_i2c_ops = { 313 .read = ppc4xx_i2c_readb, 314 .write = ppc4xx_i2c_writeb, 315 .valid.min_access_size = 1, 316 .valid.max_access_size = 4, 317 .impl.min_access_size = 1, 318 .impl.max_access_size = 1, 319 .endianness = DEVICE_NATIVE_ENDIAN, 320 }; 321 322 static void ppc4xx_i2c_init(Object *o) 323 { 324 PPC4xxI2CState *s = PPC4xx_I2C(o); 325 326 memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s, 327 TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE); 328 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 329 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); 330 s->bus = i2c_init_bus(DEVICE(s), "i2c"); 331 } 332 333 static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data) 334 { 335 DeviceClass *dc = DEVICE_CLASS(klass); 336 337 dc->reset = ppc4xx_i2c_reset; 338 } 339 340 static const TypeInfo ppc4xx_i2c_type_info = { 341 .name = TYPE_PPC4xx_I2C, 342 .parent = TYPE_SYS_BUS_DEVICE, 343 .instance_size = sizeof(PPC4xxI2CState), 344 .instance_init = ppc4xx_i2c_init, 345 .class_init = ppc4xx_i2c_class_init, 346 }; 347 348 static void ppc4xx_i2c_register_types(void) 349 { 350 type_register_static(&ppc4xx_i2c_type_info); 351 } 352 353 type_init(ppc4xx_i2c_register_types) 354