1 /* 2 * PPC4xx I2C controller emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * Copyright (c) 2012 François Revol 6 * Copyright (c) 2016-2018 BALATON Zoltan 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/log.h" 30 #include "cpu.h" 31 #include "hw/hw.h" 32 #include "hw/i2c/ppc4xx_i2c.h" 33 34 #define PPC4xx_I2C_MEM_SIZE 18 35 36 #define IIC_CNTL_PT (1 << 0) 37 #define IIC_CNTL_READ (1 << 1) 38 #define IIC_CNTL_CHT (1 << 2) 39 #define IIC_CNTL_RPST (1 << 3) 40 41 #define IIC_STS_PT (1 << 0) 42 #define IIC_STS_ERR (1 << 2) 43 #define IIC_STS_MDBS (1 << 5) 44 45 #define IIC_EXTSTS_XFRA (1 << 0) 46 47 #define IIC_XTCNTLSS_SRST (1 << 0) 48 49 static void ppc4xx_i2c_reset(DeviceState *s) 50 { 51 PPC4xxI2CState *i2c = PPC4xx_I2C(s); 52 53 /* FIXME: Should also reset bus? 54 *if (s->address != ADDR_RESET) { 55 * i2c_end_transfer(s->bus); 56 *} 57 */ 58 59 i2c->mdata = 0; 60 i2c->lmadr = 0; 61 i2c->hmadr = 0; 62 i2c->cntl = 0; 63 i2c->mdcntl = 0; 64 i2c->sts = 0; 65 i2c->extsts = 0x8f; 66 i2c->lsadr = 0; 67 i2c->hsadr = 0; 68 i2c->clkdiv = 0; 69 i2c->intrmsk = 0; 70 i2c->xfrcnt = 0; 71 i2c->xtcntlss = 0; 72 i2c->directcntl = 0xf; 73 } 74 75 static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c) 76 { 77 return true; 78 } 79 80 static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size) 81 { 82 PPC4xxI2CState *i2c = PPC4xx_I2C(opaque); 83 uint64_t ret; 84 85 switch (addr) { 86 case 0: 87 ret = i2c->mdata; 88 if (ppc4xx_i2c_is_master(i2c)) { 89 ret = 0xff; 90 91 if (!(i2c->sts & IIC_STS_MDBS)) { 92 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read " 93 "without starting transfer\n", 94 TYPE_PPC4xx_I2C, __func__); 95 } else { 96 int pending = (i2c->cntl >> 4) & 3; 97 98 /* get the next byte */ 99 int byte = i2c_recv(i2c->bus); 100 101 if (byte < 0) { 102 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed " 103 "for device 0x%02x\n", TYPE_PPC4xx_I2C, 104 __func__, i2c->lmadr); 105 ret = 0xff; 106 } else { 107 ret = byte; 108 /* Raise interrupt if enabled */ 109 /*ppc4xx_i2c_raise_interrupt(i2c)*/; 110 } 111 112 if (!pending) { 113 i2c->sts &= ~IIC_STS_MDBS; 114 /*i2c_end_transfer(i2c->bus);*/ 115 /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/ 116 } else if (pending) { 117 /* current smbus implementation doesn't like 118 multibyte xfer repeated start */ 119 i2c_end_transfer(i2c->bus); 120 if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) { 121 /* if non zero is returned, the adress is not valid */ 122 i2c->sts &= ~IIC_STS_PT; 123 i2c->sts |= IIC_STS_ERR; 124 i2c->extsts |= IIC_EXTSTS_XFRA; 125 } else { 126 /*i2c->sts |= IIC_STS_PT;*/ 127 i2c->sts |= IIC_STS_MDBS; 128 i2c->sts &= ~IIC_STS_ERR; 129 i2c->extsts = 0; 130 } 131 } 132 pending--; 133 i2c->cntl = (i2c->cntl & 0xcf) | (pending << 4); 134 } 135 } else { 136 qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n", 137 TYPE_PPC4xx_I2C, __func__); 138 } 139 break; 140 case 4: 141 ret = i2c->lmadr; 142 break; 143 case 5: 144 ret = i2c->hmadr; 145 break; 146 case 6: 147 ret = i2c->cntl; 148 break; 149 case 7: 150 ret = i2c->mdcntl; 151 break; 152 case 8: 153 ret = i2c->sts; 154 break; 155 case 9: 156 ret = i2c->extsts; 157 break; 158 case 10: 159 ret = i2c->lsadr; 160 break; 161 case 11: 162 ret = i2c->hsadr; 163 break; 164 case 12: 165 ret = i2c->clkdiv; 166 break; 167 case 13: 168 ret = i2c->intrmsk; 169 break; 170 case 14: 171 ret = i2c->xfrcnt; 172 break; 173 case 15: 174 ret = i2c->xtcntlss; 175 break; 176 case 16: 177 ret = i2c->directcntl; 178 break; 179 default: 180 if (addr < PPC4xx_I2C_MEM_SIZE) { 181 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%" 182 HWADDR_PRIx "\n", __func__, addr); 183 } else { 184 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" 185 HWADDR_PRIx "\n", __func__, addr); 186 } 187 ret = 0; 188 break; 189 } 190 return ret; 191 } 192 193 static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, 194 unsigned int size) 195 { 196 PPC4xxI2CState *i2c = opaque; 197 198 switch (addr) { 199 case 0: 200 i2c->mdata = value; 201 if (!i2c_bus_busy(i2c->bus)) { 202 /* assume we start a write transfer */ 203 if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 0)) { 204 /* if non zero is returned, the adress is not valid */ 205 i2c->sts &= ~IIC_STS_PT; 206 i2c->sts |= IIC_STS_ERR; 207 i2c->extsts |= IIC_EXTSTS_XFRA; 208 } else { 209 i2c->sts |= IIC_STS_PT; 210 i2c->sts &= ~IIC_STS_ERR; 211 i2c->extsts = 0; 212 } 213 } 214 if (i2c_bus_busy(i2c->bus)) { 215 if (i2c_send(i2c->bus, i2c->mdata)) { 216 /* if the target return non zero then end the transfer */ 217 i2c->sts &= ~IIC_STS_PT; 218 i2c->sts |= IIC_STS_ERR; 219 i2c->extsts |= IIC_EXTSTS_XFRA; 220 i2c_end_transfer(i2c->bus); 221 } 222 } 223 break; 224 case 4: 225 i2c->lmadr = value; 226 if (i2c_bus_busy(i2c->bus)) { 227 i2c_end_transfer(i2c->bus); 228 } 229 break; 230 case 5: 231 i2c->hmadr = value; 232 break; 233 case 6: 234 i2c->cntl = value; 235 if (i2c->cntl & IIC_CNTL_PT) { 236 if (i2c->cntl & IIC_CNTL_READ) { 237 if (i2c_bus_busy(i2c->bus)) { 238 /* end previous transfer */ 239 i2c->sts &= ~IIC_STS_PT; 240 i2c_end_transfer(i2c->bus); 241 } 242 if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) { 243 /* if non zero is returned, the adress is not valid */ 244 i2c->sts &= ~IIC_STS_PT; 245 i2c->sts |= IIC_STS_ERR; 246 i2c->extsts |= IIC_EXTSTS_XFRA; 247 } else { 248 /*i2c->sts |= IIC_STS_PT;*/ 249 i2c->sts |= IIC_STS_MDBS; 250 i2c->sts &= ~IIC_STS_ERR; 251 i2c->extsts = 0; 252 } 253 } else { 254 /* we actually already did the write transfer... */ 255 i2c->sts &= ~IIC_STS_PT; 256 } 257 } 258 break; 259 case 7: 260 i2c->mdcntl = value & 0xdf; 261 break; 262 case 8: 263 i2c->sts &= ~(value & 0xa); 264 break; 265 case 9: 266 i2c->extsts &= ~(value & 0x8f); 267 break; 268 case 10: 269 i2c->lsadr = value; 270 break; 271 case 11: 272 i2c->hsadr = value; 273 break; 274 case 12: 275 i2c->clkdiv = value; 276 break; 277 case 13: 278 i2c->intrmsk = value; 279 break; 280 case 14: 281 i2c->xfrcnt = value & 0x77; 282 break; 283 case 15: 284 if (value & IIC_XTCNTLSS_SRST) { 285 /* Is it actually a full reset? U-Boot sets some regs before */ 286 ppc4xx_i2c_reset(DEVICE(i2c)); 287 break; 288 } 289 i2c->xtcntlss = value; 290 break; 291 case 16: 292 i2c->directcntl = value & 0x7; 293 break; 294 default: 295 if (addr < PPC4xx_I2C_MEM_SIZE) { 296 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%" 297 HWADDR_PRIx "\n", __func__, addr); 298 } else { 299 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" 300 HWADDR_PRIx "\n", __func__, addr); 301 } 302 break; 303 } 304 } 305 306 static const MemoryRegionOps ppc4xx_i2c_ops = { 307 .read = ppc4xx_i2c_readb, 308 .write = ppc4xx_i2c_writeb, 309 .valid.min_access_size = 1, 310 .valid.max_access_size = 4, 311 .impl.min_access_size = 1, 312 .impl.max_access_size = 1, 313 .endianness = DEVICE_NATIVE_ENDIAN, 314 }; 315 316 static void ppc4xx_i2c_init(Object *o) 317 { 318 PPC4xxI2CState *s = PPC4xx_I2C(o); 319 320 memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s, 321 TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE); 322 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 323 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); 324 s->bus = i2c_init_bus(DEVICE(s), "i2c"); 325 } 326 327 static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data) 328 { 329 DeviceClass *dc = DEVICE_CLASS(klass); 330 331 dc->reset = ppc4xx_i2c_reset; 332 } 333 334 static const TypeInfo ppc4xx_i2c_type_info = { 335 .name = TYPE_PPC4xx_I2C, 336 .parent = TYPE_SYS_BUS_DEVICE, 337 .instance_size = sizeof(PPC4xxI2CState), 338 .instance_init = ppc4xx_i2c_init, 339 .class_init = ppc4xx_i2c_class_init, 340 }; 341 342 static void ppc4xx_i2c_register_types(void) 343 { 344 type_register_static(&ppc4xx_i2c_type_info); 345 } 346 347 type_init(ppc4xx_i2c_register_types) 348