1 /* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. All rights reserved. 3 * 4 * Author: Amit Tomar, <Amit.Tomar@freescale.com> 5 * 6 * Description: 7 * This file is derived from IMX I2C controller, 8 * by Jean-Christophe DUBOIS . 9 * 10 * Thanks to Scott Wood and Alexander Graf for their kind help on this. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License, version 2 or later, 14 * as published by the Free Software Foundation. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/i2c/i2c.h" 22 #include "qemu/log.h" 23 #include "hw/sysbus.h" 24 25 /* #define DEBUG_I2C */ 26 27 #ifdef DEBUG_I2C 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "mpc_i2c[%s]: " fmt, __func__, ## __VA_ARGS__); \ 30 } while (0) 31 #else 32 #define DPRINTF(fmt, ...) do {} while (0) 33 #endif 34 35 #define TYPE_MPC_I2C "mpc-i2c" 36 #define MPC_I2C(obj) \ 37 OBJECT_CHECK(MPCI2CState, (obj), TYPE_MPC_I2C) 38 39 #define MPC_I2C_ADR 0x00 40 #define MPC_I2C_FDR 0x04 41 #define MPC_I2C_CR 0x08 42 #define MPC_I2C_SR 0x0c 43 #define MPC_I2C_DR 0x10 44 #define MPC_I2C_DFSRR 0x14 45 46 #define CCR_MEN (1 << 7) 47 #define CCR_MIEN (1 << 6) 48 #define CCR_MSTA (1 << 5) 49 #define CCR_MTX (1 << 4) 50 #define CCR_TXAK (1 << 3) 51 #define CCR_RSTA (1 << 2) 52 #define CCR_BCST (1 << 0) 53 54 #define CSR_MCF (1 << 7) 55 #define CSR_MAAS (1 << 6) 56 #define CSR_MBB (1 << 5) 57 #define CSR_MAL (1 << 4) 58 #define CSR_SRW (1 << 2) 59 #define CSR_MIF (1 << 1) 60 #define CSR_RXAK (1 << 0) 61 62 #define CADR_MASK 0xFE 63 #define CFDR_MASK 0x3F 64 #define CCR_MASK 0xFC 65 #define CSR_MASK 0xED 66 #define CDR_MASK 0xFF 67 68 #define CYCLE_RESET 0xFF 69 70 typedef struct MPCI2CState { 71 SysBusDevice parent_obj; 72 73 I2CBus *bus; 74 qemu_irq irq; 75 MemoryRegion iomem; 76 77 uint8_t address; 78 uint8_t adr; 79 uint8_t fdr; 80 uint8_t cr; 81 uint8_t sr; 82 uint8_t dr; 83 uint8_t dfssr; 84 } MPCI2CState; 85 86 static bool mpc_i2c_is_enabled(MPCI2CState *s) 87 { 88 return s->cr & CCR_MEN; 89 } 90 91 static bool mpc_i2c_is_master(MPCI2CState *s) 92 { 93 return s->cr & CCR_MSTA; 94 } 95 96 static bool mpc_i2c_direction_is_tx(MPCI2CState *s) 97 { 98 return s->cr & CCR_MTX; 99 } 100 101 static bool mpc_i2c_irq_pending(MPCI2CState *s) 102 { 103 return s->sr & CSR_MIF; 104 } 105 106 static bool mpc_i2c_irq_is_enabled(MPCI2CState *s) 107 { 108 return s->cr & CCR_MIEN; 109 } 110 111 static void mpc_i2c_reset(DeviceState *dev) 112 { 113 MPCI2CState *i2c = MPC_I2C(dev); 114 115 i2c->address = 0xFF; 116 i2c->adr = 0x00; 117 i2c->fdr = 0x00; 118 i2c->cr = 0x00; 119 i2c->sr = 0x81; 120 i2c->dr = 0x00; 121 } 122 123 static void mpc_i2c_irq(MPCI2CState *s) 124 { 125 bool irq_active = false; 126 127 if (mpc_i2c_is_enabled(s) && mpc_i2c_irq_is_enabled(s) 128 && mpc_i2c_irq_pending(s)) { 129 irq_active = true; 130 } 131 132 if (irq_active) { 133 qemu_irq_raise(s->irq); 134 } else { 135 qemu_irq_lower(s->irq); 136 } 137 } 138 139 static void mpc_i2c_soft_reset(MPCI2CState *s) 140 { 141 /* This is a soft reset. ADR is preserved during soft resets */ 142 uint8_t adr = s->adr; 143 mpc_i2c_reset(DEVICE(s)); 144 s->adr = adr; 145 } 146 147 static void mpc_i2c_address_send(MPCI2CState *s) 148 { 149 /* if returns non zero slave address is not right */ 150 if (i2c_start_transfer(s->bus, s->dr >> 1, s->dr & (0x01))) { 151 s->sr |= CSR_RXAK; 152 } else { 153 s->address = s->dr; 154 s->sr &= ~CSR_RXAK; 155 s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */ 156 s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */ 157 mpc_i2c_irq(s); 158 } 159 } 160 161 static void mpc_i2c_data_send(MPCI2CState *s) 162 { 163 if (i2c_send(s->bus, s->dr)) { 164 /* End of transfer */ 165 s->sr |= CSR_RXAK; 166 i2c_end_transfer(s->bus); 167 } else { 168 s->sr &= ~CSR_RXAK; 169 s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */ 170 s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */ 171 mpc_i2c_irq(s); 172 } 173 } 174 175 static void mpc_i2c_data_recive(MPCI2CState *s) 176 { 177 int ret; 178 /* get the next byte */ 179 ret = i2c_recv(s->bus); 180 if (ret >= 0) { 181 s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */ 182 s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */ 183 mpc_i2c_irq(s); 184 } else { 185 DPRINTF("read failed for device"); 186 ret = 0xff; 187 } 188 s->dr = ret; 189 } 190 191 static uint64_t mpc_i2c_read(void *opaque, hwaddr addr, unsigned size) 192 { 193 MPCI2CState *s = opaque; 194 uint8_t value; 195 196 switch (addr) { 197 case MPC_I2C_ADR: 198 value = s->adr; 199 break; 200 case MPC_I2C_FDR: 201 value = s->fdr; 202 break; 203 case MPC_I2C_CR: 204 value = s->cr; 205 break; 206 case MPC_I2C_SR: 207 value = s->sr; 208 break; 209 case MPC_I2C_DR: 210 value = s->dr; 211 if (mpc_i2c_is_master(s)) { /* master mode */ 212 if (mpc_i2c_direction_is_tx(s)) { 213 DPRINTF("MTX is set not in recv mode\n"); 214 } else { 215 mpc_i2c_data_recive(s); 216 } 217 } 218 break; 219 default: 220 value = 0; 221 DPRINTF("ERROR: Bad read addr 0x%x\n", (unsigned int)addr); 222 break; 223 } 224 225 DPRINTF("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, 226 addr, value); 227 return (uint64_t)value; 228 } 229 230 static void mpc_i2c_write(void *opaque, hwaddr addr, 231 uint64_t value, unsigned size) 232 { 233 MPCI2CState *s = opaque; 234 235 DPRINTF("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n", __func__, 236 addr, value); 237 switch (addr) { 238 case MPC_I2C_ADR: 239 s->adr = value & CADR_MASK; 240 break; 241 case MPC_I2C_FDR: 242 s->fdr = value & CFDR_MASK; 243 break; 244 case MPC_I2C_CR: 245 if (mpc_i2c_is_enabled(s) && ((value & CCR_MEN) == 0)) { 246 mpc_i2c_soft_reset(s); 247 break; 248 } 249 /* normal write */ 250 s->cr = value & CCR_MASK; 251 if (mpc_i2c_is_master(s)) { /* master mode */ 252 /* set the bus to busy after master is set as per RM */ 253 s->sr |= CSR_MBB; 254 } else { 255 /* bus is not busy anymore */ 256 s->sr &= ~CSR_MBB; 257 /* Reset the address for fresh write/read cycle */ 258 if (s->address != CYCLE_RESET) { 259 i2c_end_transfer(s->bus); 260 s->address = CYCLE_RESET; 261 } 262 } 263 /* For restart end the onging transfer */ 264 if (s->cr & CCR_RSTA) { 265 if (s->address != CYCLE_RESET) { 266 s->address = CYCLE_RESET; 267 i2c_end_transfer(s->bus); 268 s->cr &= ~CCR_RSTA; 269 } 270 } 271 break; 272 case MPC_I2C_SR: 273 s->sr = value & CSR_MASK; 274 /* Lower the interrupt */ 275 if (!(s->sr & CSR_MIF) || !(s->sr & CSR_MAL)) { 276 mpc_i2c_irq(s); 277 } 278 break; 279 case MPC_I2C_DR: 280 /* if the device is not enabled, nothing to do */ 281 if (!mpc_i2c_is_enabled(s)) { 282 break; 283 } 284 s->dr = value & CDR_MASK; 285 if (mpc_i2c_is_master(s)) { /* master mode */ 286 if (s->address == CYCLE_RESET) { 287 mpc_i2c_address_send(s); 288 } else { 289 mpc_i2c_data_send(s); 290 } 291 } 292 break; 293 case MPC_I2C_DFSRR: 294 s->dfssr = value; 295 break; 296 default: 297 DPRINTF("ERROR: Bad write addr 0x%x\n", (unsigned int)addr); 298 break; 299 } 300 } 301 302 static const MemoryRegionOps i2c_ops = { 303 .read = mpc_i2c_read, 304 .write = mpc_i2c_write, 305 .valid.max_access_size = 1, 306 .endianness = DEVICE_NATIVE_ENDIAN, 307 }; 308 309 static const VMStateDescription mpc_i2c_vmstate = { 310 .name = TYPE_MPC_I2C, 311 .version_id = 1, 312 .minimum_version_id = 1, 313 .fields = (VMStateField[]) { 314 VMSTATE_UINT8(address, MPCI2CState), 315 VMSTATE_UINT8(adr, MPCI2CState), 316 VMSTATE_UINT8(fdr, MPCI2CState), 317 VMSTATE_UINT8(cr, MPCI2CState), 318 VMSTATE_UINT8(sr, MPCI2CState), 319 VMSTATE_UINT8(dr, MPCI2CState), 320 VMSTATE_UINT8(dfssr, MPCI2CState), 321 VMSTATE_END_OF_LIST() 322 } 323 }; 324 325 static void mpc_i2c_realize(DeviceState *dev, Error **errp) 326 { 327 MPCI2CState *i2c = MPC_I2C(dev); 328 sysbus_init_irq(SYS_BUS_DEVICE(dev), &i2c->irq); 329 memory_region_init_io(&i2c->iomem, OBJECT(i2c), &i2c_ops, i2c, 330 "mpc-i2c", 0x14); 331 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &i2c->iomem); 332 i2c->bus = i2c_init_bus(DEVICE(dev), "i2c"); 333 } 334 335 static void mpc_i2c_class_init(ObjectClass *klass, void *data) 336 { 337 DeviceClass *dc = DEVICE_CLASS(klass); 338 339 dc->vmsd = &mpc_i2c_vmstate ; 340 dc->reset = mpc_i2c_reset; 341 dc->realize = mpc_i2c_realize; 342 dc->desc = "MPC I2C Controller"; 343 } 344 345 static const TypeInfo mpc_i2c_type_info = { 346 .name = TYPE_MPC_I2C, 347 .parent = TYPE_SYS_BUS_DEVICE, 348 .instance_size = sizeof(MPCI2CState), 349 .class_init = mpc_i2c_class_init, 350 }; 351 352 static void mpc_i2c_register_types(void) 353 { 354 type_register_static(&mpc_i2c_type_info); 355 } 356 357 type_init(mpc_i2c_register_types) 358