1 /* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. All rights reserved. 3 * 4 * Author: Amit Tomar, <Amit.Tomar@freescale.com> 5 * 6 * Description: 7 * This file is derived from IMX I2C controller, 8 * by Jean-Christophe DUBOIS . 9 * 10 * Thanks to Scott Wood and Alexander Graf for their kind help on this. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License, version 2 or later, 14 * as published by the Free Software Foundation. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/i2c/i2c.h" 22 #include "qemu/log.h" 23 #include "qemu/module.h" 24 #include "hw/sysbus.h" 25 26 /* #define DEBUG_I2C */ 27 28 #ifdef DEBUG_I2C 29 #define DPRINTF(fmt, ...) \ 30 do { fprintf(stderr, "mpc_i2c[%s]: " fmt, __func__, ## __VA_ARGS__); \ 31 } while (0) 32 #else 33 #define DPRINTF(fmt, ...) do {} while (0) 34 #endif 35 36 #define TYPE_MPC_I2C "mpc-i2c" 37 #define MPC_I2C(obj) \ 38 OBJECT_CHECK(MPCI2CState, (obj), TYPE_MPC_I2C) 39 40 #define MPC_I2C_ADR 0x00 41 #define MPC_I2C_FDR 0x04 42 #define MPC_I2C_CR 0x08 43 #define MPC_I2C_SR 0x0c 44 #define MPC_I2C_DR 0x10 45 #define MPC_I2C_DFSRR 0x14 46 47 #define CCR_MEN (1 << 7) 48 #define CCR_MIEN (1 << 6) 49 #define CCR_MSTA (1 << 5) 50 #define CCR_MTX (1 << 4) 51 #define CCR_TXAK (1 << 3) 52 #define CCR_RSTA (1 << 2) 53 #define CCR_BCST (1 << 0) 54 55 #define CSR_MCF (1 << 7) 56 #define CSR_MAAS (1 << 6) 57 #define CSR_MBB (1 << 5) 58 #define CSR_MAL (1 << 4) 59 #define CSR_SRW (1 << 2) 60 #define CSR_MIF (1 << 1) 61 #define CSR_RXAK (1 << 0) 62 63 #define CADR_MASK 0xFE 64 #define CFDR_MASK 0x3F 65 #define CCR_MASK 0xFC 66 #define CSR_MASK 0xED 67 #define CDR_MASK 0xFF 68 69 #define CYCLE_RESET 0xFF 70 71 typedef struct MPCI2CState { 72 SysBusDevice parent_obj; 73 74 I2CBus *bus; 75 qemu_irq irq; 76 MemoryRegion iomem; 77 78 uint8_t address; 79 uint8_t adr; 80 uint8_t fdr; 81 uint8_t cr; 82 uint8_t sr; 83 uint8_t dr; 84 uint8_t dfssr; 85 } MPCI2CState; 86 87 static bool mpc_i2c_is_enabled(MPCI2CState *s) 88 { 89 return s->cr & CCR_MEN; 90 } 91 92 static bool mpc_i2c_is_master(MPCI2CState *s) 93 { 94 return s->cr & CCR_MSTA; 95 } 96 97 static bool mpc_i2c_direction_is_tx(MPCI2CState *s) 98 { 99 return s->cr & CCR_MTX; 100 } 101 102 static bool mpc_i2c_irq_pending(MPCI2CState *s) 103 { 104 return s->sr & CSR_MIF; 105 } 106 107 static bool mpc_i2c_irq_is_enabled(MPCI2CState *s) 108 { 109 return s->cr & CCR_MIEN; 110 } 111 112 static void mpc_i2c_reset(DeviceState *dev) 113 { 114 MPCI2CState *i2c = MPC_I2C(dev); 115 116 i2c->address = 0xFF; 117 i2c->adr = 0x00; 118 i2c->fdr = 0x00; 119 i2c->cr = 0x00; 120 i2c->sr = 0x81; 121 i2c->dr = 0x00; 122 } 123 124 static void mpc_i2c_irq(MPCI2CState *s) 125 { 126 bool irq_active = false; 127 128 if (mpc_i2c_is_enabled(s) && mpc_i2c_irq_is_enabled(s) 129 && mpc_i2c_irq_pending(s)) { 130 irq_active = true; 131 } 132 133 if (irq_active) { 134 qemu_irq_raise(s->irq); 135 } else { 136 qemu_irq_lower(s->irq); 137 } 138 } 139 140 static void mpc_i2c_soft_reset(MPCI2CState *s) 141 { 142 /* This is a soft reset. ADR is preserved during soft resets */ 143 uint8_t adr = s->adr; 144 mpc_i2c_reset(DEVICE(s)); 145 s->adr = adr; 146 } 147 148 static void mpc_i2c_address_send(MPCI2CState *s) 149 { 150 /* if returns non zero slave address is not right */ 151 if (i2c_start_transfer(s->bus, s->dr >> 1, s->dr & (0x01))) { 152 s->sr |= CSR_RXAK; 153 } else { 154 s->address = s->dr; 155 s->sr &= ~CSR_RXAK; 156 s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */ 157 s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */ 158 mpc_i2c_irq(s); 159 } 160 } 161 162 static void mpc_i2c_data_send(MPCI2CState *s) 163 { 164 if (i2c_send(s->bus, s->dr)) { 165 /* End of transfer */ 166 s->sr |= CSR_RXAK; 167 i2c_end_transfer(s->bus); 168 } else { 169 s->sr &= ~CSR_RXAK; 170 s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */ 171 s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */ 172 mpc_i2c_irq(s); 173 } 174 } 175 176 static void mpc_i2c_data_recive(MPCI2CState *s) 177 { 178 int ret; 179 /* get the next byte */ 180 ret = i2c_recv(s->bus); 181 if (ret >= 0) { 182 s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */ 183 s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */ 184 mpc_i2c_irq(s); 185 } else { 186 DPRINTF("read failed for device"); 187 ret = 0xff; 188 } 189 s->dr = ret; 190 } 191 192 static uint64_t mpc_i2c_read(void *opaque, hwaddr addr, unsigned size) 193 { 194 MPCI2CState *s = opaque; 195 uint8_t value; 196 197 switch (addr) { 198 case MPC_I2C_ADR: 199 value = s->adr; 200 break; 201 case MPC_I2C_FDR: 202 value = s->fdr; 203 break; 204 case MPC_I2C_CR: 205 value = s->cr; 206 break; 207 case MPC_I2C_SR: 208 value = s->sr; 209 break; 210 case MPC_I2C_DR: 211 value = s->dr; 212 if (mpc_i2c_is_master(s)) { /* master mode */ 213 if (mpc_i2c_direction_is_tx(s)) { 214 DPRINTF("MTX is set not in recv mode\n"); 215 } else { 216 mpc_i2c_data_recive(s); 217 } 218 } 219 break; 220 default: 221 value = 0; 222 DPRINTF("ERROR: Bad read addr 0x%x\n", (unsigned int)addr); 223 break; 224 } 225 226 DPRINTF("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, 227 addr, value); 228 return (uint64_t)value; 229 } 230 231 static void mpc_i2c_write(void *opaque, hwaddr addr, 232 uint64_t value, unsigned size) 233 { 234 MPCI2CState *s = opaque; 235 236 DPRINTF("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n", __func__, 237 addr, value); 238 switch (addr) { 239 case MPC_I2C_ADR: 240 s->adr = value & CADR_MASK; 241 break; 242 case MPC_I2C_FDR: 243 s->fdr = value & CFDR_MASK; 244 break; 245 case MPC_I2C_CR: 246 if (mpc_i2c_is_enabled(s) && ((value & CCR_MEN) == 0)) { 247 mpc_i2c_soft_reset(s); 248 break; 249 } 250 /* normal write */ 251 s->cr = value & CCR_MASK; 252 if (mpc_i2c_is_master(s)) { /* master mode */ 253 /* set the bus to busy after master is set as per RM */ 254 s->sr |= CSR_MBB; 255 } else { 256 /* bus is not busy anymore */ 257 s->sr &= ~CSR_MBB; 258 /* Reset the address for fresh write/read cycle */ 259 if (s->address != CYCLE_RESET) { 260 i2c_end_transfer(s->bus); 261 s->address = CYCLE_RESET; 262 } 263 } 264 /* For restart end the onging transfer */ 265 if (s->cr & CCR_RSTA) { 266 if (s->address != CYCLE_RESET) { 267 s->address = CYCLE_RESET; 268 i2c_end_transfer(s->bus); 269 s->cr &= ~CCR_RSTA; 270 } 271 } 272 break; 273 case MPC_I2C_SR: 274 s->sr = value & CSR_MASK; 275 /* Lower the interrupt */ 276 if (!(s->sr & CSR_MIF) || !(s->sr & CSR_MAL)) { 277 mpc_i2c_irq(s); 278 } 279 break; 280 case MPC_I2C_DR: 281 /* if the device is not enabled, nothing to do */ 282 if (!mpc_i2c_is_enabled(s)) { 283 break; 284 } 285 s->dr = value & CDR_MASK; 286 if (mpc_i2c_is_master(s)) { /* master mode */ 287 if (s->address == CYCLE_RESET) { 288 mpc_i2c_address_send(s); 289 } else { 290 mpc_i2c_data_send(s); 291 } 292 } 293 break; 294 case MPC_I2C_DFSRR: 295 s->dfssr = value; 296 break; 297 default: 298 DPRINTF("ERROR: Bad write addr 0x%x\n", (unsigned int)addr); 299 break; 300 } 301 } 302 303 static const MemoryRegionOps i2c_ops = { 304 .read = mpc_i2c_read, 305 .write = mpc_i2c_write, 306 .valid.max_access_size = 1, 307 .endianness = DEVICE_NATIVE_ENDIAN, 308 }; 309 310 static const VMStateDescription mpc_i2c_vmstate = { 311 .name = TYPE_MPC_I2C, 312 .version_id = 1, 313 .minimum_version_id = 1, 314 .fields = (VMStateField[]) { 315 VMSTATE_UINT8(address, MPCI2CState), 316 VMSTATE_UINT8(adr, MPCI2CState), 317 VMSTATE_UINT8(fdr, MPCI2CState), 318 VMSTATE_UINT8(cr, MPCI2CState), 319 VMSTATE_UINT8(sr, MPCI2CState), 320 VMSTATE_UINT8(dr, MPCI2CState), 321 VMSTATE_UINT8(dfssr, MPCI2CState), 322 VMSTATE_END_OF_LIST() 323 } 324 }; 325 326 static void mpc_i2c_realize(DeviceState *dev, Error **errp) 327 { 328 MPCI2CState *i2c = MPC_I2C(dev); 329 sysbus_init_irq(SYS_BUS_DEVICE(dev), &i2c->irq); 330 memory_region_init_io(&i2c->iomem, OBJECT(i2c), &i2c_ops, i2c, 331 "mpc-i2c", 0x14); 332 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &i2c->iomem); 333 i2c->bus = i2c_init_bus(DEVICE(dev), "i2c"); 334 } 335 336 static void mpc_i2c_class_init(ObjectClass *klass, void *data) 337 { 338 DeviceClass *dc = DEVICE_CLASS(klass); 339 340 dc->vmsd = &mpc_i2c_vmstate ; 341 dc->reset = mpc_i2c_reset; 342 dc->realize = mpc_i2c_realize; 343 dc->desc = "MPC I2C Controller"; 344 } 345 346 static const TypeInfo mpc_i2c_type_info = { 347 .name = TYPE_MPC_I2C, 348 .parent = TYPE_SYS_BUS_DEVICE, 349 .instance_size = sizeof(MPCI2CState), 350 .class_init = mpc_i2c_class_init, 351 }; 352 353 static void mpc_i2c_register_types(void) 354 { 355 type_register_static(&mpc_i2c_type_info); 356 } 357 358 type_init(mpc_i2c_register_types) 359