xref: /openbmc/qemu/hw/i2c/imx_i2c.c (revision 64552b6b)
1 /*
2  *  i.MX I2C Bus Serial Interface Emulation
3  *
4  *  Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
5  *
6  *  This program is free software; you can redistribute it and/or modify it
7  *  under the terms of the GNU General Public License as published by the
8  *  Free Software Foundation; either version 2 of the License, or
9  *  (at your option) any later version.
10  *
11  *  This program is distributed in the hope that it will be useful, but WITHOUT
12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14  *  for more details.
15  *
16  *  You should have received a copy of the GNU General Public License along
17  *  with this program; if not, see <http://www.gnu.org/licenses/>.
18  *
19  */
20 
21 #include "qemu/osdep.h"
22 #include "hw/i2c/imx_i2c.h"
23 #include "hw/irq.h"
24 #include "hw/i2c/i2c.h"
25 #include "qemu/log.h"
26 #include "qemu/module.h"
27 
28 #ifndef DEBUG_IMX_I2C
29 #define DEBUG_IMX_I2C 0
30 #endif
31 
32 #define DPRINTF(fmt, args...) \
33     do { \
34         if (DEBUG_IMX_I2C) { \
35             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \
36                                              __func__, ##args); \
37         } \
38     } while (0)
39 
40 static const char *imx_i2c_get_regname(unsigned offset)
41 {
42     switch (offset) {
43     case IADR_ADDR:
44         return "IADR";
45     case IFDR_ADDR:
46         return "IFDR";
47     case I2CR_ADDR:
48         return "I2CR";
49     case I2SR_ADDR:
50         return "I2SR";
51     case I2DR_ADDR:
52         return "I2DR";
53     default:
54         return "[?]";
55     }
56 }
57 
58 static inline bool imx_i2c_is_enabled(IMXI2CState *s)
59 {
60     return s->i2cr & I2CR_IEN;
61 }
62 
63 static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s)
64 {
65     return s->i2cr & I2CR_IIEN;
66 }
67 
68 static inline bool imx_i2c_is_master(IMXI2CState *s)
69 {
70     return s->i2cr & I2CR_MSTA;
71 }
72 
73 static void imx_i2c_reset(DeviceState *dev)
74 {
75     IMXI2CState *s = IMX_I2C(dev);
76 
77     if (s->address != ADDR_RESET) {
78         i2c_end_transfer(s->bus);
79     }
80 
81     s->address    = ADDR_RESET;
82     s->iadr       = IADR_RESET;
83     s->ifdr       = IFDR_RESET;
84     s->i2cr       = I2CR_RESET;
85     s->i2sr       = I2SR_RESET;
86     s->i2dr_read  = I2DR_RESET;
87     s->i2dr_write = I2DR_RESET;
88 }
89 
90 static inline void imx_i2c_raise_interrupt(IMXI2CState *s)
91 {
92     /*
93      * raise an interrupt if the device is enabled and it is configured
94      * to generate some interrupts.
95      */
96     if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) {
97         s->i2sr |= I2SR_IIF;
98         qemu_irq_raise(s->irq);
99     }
100 }
101 
102 static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
103                              unsigned size)
104 {
105     uint16_t value;
106     IMXI2CState *s = IMX_I2C(opaque);
107 
108     switch (offset) {
109     case IADR_ADDR:
110         value = s->iadr;
111         break;
112     case IFDR_ADDR:
113         value = s->ifdr;
114         break;
115     case I2CR_ADDR:
116         value = s->i2cr;
117         break;
118     case I2SR_ADDR:
119         value = s->i2sr;
120         break;
121     case I2DR_ADDR:
122         value = s->i2dr_read;
123 
124         if (imx_i2c_is_master(s)) {
125             uint8_t ret = 0xff;
126 
127             if (s->address == ADDR_RESET) {
128                 /* something is wrong as the address is not set */
129                 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
130                               "without specifying the slave address\n",
131                               TYPE_IMX_I2C, __func__);
132             } else if (s->i2cr & I2CR_MTX) {
133                 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
134                               "but MTX is set\n", TYPE_IMX_I2C, __func__);
135             } else {
136                 /* get the next byte */
137                 ret = i2c_recv(s->bus);
138                 imx_i2c_raise_interrupt(s);
139             }
140 
141             s->i2dr_read = ret;
142         } else {
143             qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
144                           TYPE_IMX_I2C, __func__);
145         }
146         break;
147     default:
148         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
149                       HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
150         value = 0;
151         break;
152     }
153 
154     DPRINTF("read %s [0x%" HWADDR_PRIx "] -> 0x%02x\n",
155             imx_i2c_get_regname(offset), offset, value);
156 
157     return (uint64_t)value;
158 }
159 
160 static void imx_i2c_write(void *opaque, hwaddr offset,
161                           uint64_t value, unsigned size)
162 {
163     IMXI2CState *s = IMX_I2C(opaque);
164 
165     DPRINTF("write %s [0x%" HWADDR_PRIx "] <- 0x%02x\n",
166             imx_i2c_get_regname(offset), offset, (int)value);
167 
168     value &= 0xff;
169 
170     switch (offset) {
171     case IADR_ADDR:
172         s->iadr = value & IADR_MASK;
173         /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */
174         break;
175     case IFDR_ADDR:
176         s->ifdr = value & IFDR_MASK;
177         break;
178     case I2CR_ADDR:
179         if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) {
180             /* This is a soft reset. IADR is preserved during soft resets */
181             uint16_t iadr = s->iadr;
182             imx_i2c_reset(DEVICE(s));
183             s->iadr = iadr;
184         } else { /* normal write */
185             s->i2cr = value & I2CR_MASK;
186 
187             if (imx_i2c_is_master(s)) {
188                 /* set the bus to busy */
189                 s->i2sr |= I2SR_IBB;
190             } else { /* slave mode */
191                 /* bus is not busy anymore */
192                 s->i2sr &= ~I2SR_IBB;
193 
194                 /*
195                  * if we unset the master mode then it ends the ongoing
196                  * transfer if any
197                  */
198                 if (s->address != ADDR_RESET) {
199                     i2c_end_transfer(s->bus);
200                     s->address = ADDR_RESET;
201                 }
202             }
203 
204             if (s->i2cr & I2CR_RSTA) { /* Restart */
205                 /* if this is a restart then it ends the ongoing transfer */
206                 if (s->address != ADDR_RESET) {
207                     i2c_end_transfer(s->bus);
208                     s->address = ADDR_RESET;
209                     s->i2cr &= ~I2CR_RSTA;
210                 }
211             }
212         }
213         break;
214     case I2SR_ADDR:
215         /*
216          * if the user writes 0 to IIF then lower the interrupt and
217          * reset the bit
218          */
219         if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) {
220             s->i2sr &= ~I2SR_IIF;
221             qemu_irq_lower(s->irq);
222         }
223 
224         /*
225          * if the user writes 0 to IAL, reset the bit
226          */
227         if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) {
228             s->i2sr &= ~I2SR_IAL;
229         }
230 
231         break;
232     case I2DR_ADDR:
233         /* if the device is not enabled, nothing to do */
234         if (!imx_i2c_is_enabled(s)) {
235             break;
236         }
237 
238         s->i2dr_write = value & I2DR_MASK;
239 
240         if (imx_i2c_is_master(s)) {
241             /* If this is the first write cycle then it is the slave addr */
242             if (s->address == ADDR_RESET) {
243                 if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7),
244                                        extract32(s->i2dr_write, 0, 1))) {
245                     /* if non zero is returned, the address is not valid */
246                     s->i2sr |= I2SR_RXAK;
247                 } else {
248                     s->address = s->i2dr_write;
249                     s->i2sr &= ~I2SR_RXAK;
250                     imx_i2c_raise_interrupt(s);
251                 }
252             } else { /* This is a normal data write */
253                 if (i2c_send(s->bus, s->i2dr_write)) {
254                     /* if the target return non zero then end the transfer */
255                     s->i2sr |= I2SR_RXAK;
256                     s->address = ADDR_RESET;
257                     i2c_end_transfer(s->bus);
258                 } else {
259                     s->i2sr &= ~I2SR_RXAK;
260                     imx_i2c_raise_interrupt(s);
261                 }
262             }
263         } else {
264             qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
265                           TYPE_IMX_I2C, __func__);
266         }
267         break;
268     default:
269         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
270                       HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
271         break;
272     }
273 }
274 
275 static const MemoryRegionOps imx_i2c_ops = {
276     .read = imx_i2c_read,
277     .write = imx_i2c_write,
278     .valid.min_access_size = 1,
279     .valid.max_access_size = 2,
280     .endianness = DEVICE_NATIVE_ENDIAN,
281 };
282 
283 static const VMStateDescription imx_i2c_vmstate = {
284     .name = TYPE_IMX_I2C,
285     .version_id = 1,
286     .minimum_version_id = 1,
287     .fields = (VMStateField[]) {
288         VMSTATE_UINT16(address, IMXI2CState),
289         VMSTATE_UINT16(iadr, IMXI2CState),
290         VMSTATE_UINT16(ifdr, IMXI2CState),
291         VMSTATE_UINT16(i2cr, IMXI2CState),
292         VMSTATE_UINT16(i2sr, IMXI2CState),
293         VMSTATE_UINT16(i2dr_read, IMXI2CState),
294         VMSTATE_UINT16(i2dr_write, IMXI2CState),
295         VMSTATE_END_OF_LIST()
296     }
297 };
298 
299 static void imx_i2c_realize(DeviceState *dev, Error **errp)
300 {
301     IMXI2CState *s = IMX_I2C(dev);
302 
303     memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C,
304                           IMX_I2C_MEM_SIZE);
305     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
306     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
307     s->bus = i2c_init_bus(DEVICE(dev), NULL);
308 }
309 
310 static void imx_i2c_class_init(ObjectClass *klass, void *data)
311 {
312     DeviceClass *dc = DEVICE_CLASS(klass);
313 
314     dc->vmsd = &imx_i2c_vmstate;
315     dc->reset = imx_i2c_reset;
316     dc->realize = imx_i2c_realize;
317     dc->desc = "i.MX I2C Controller";
318 }
319 
320 static const TypeInfo imx_i2c_type_info = {
321     .name = TYPE_IMX_I2C,
322     .parent = TYPE_SYS_BUS_DEVICE,
323     .instance_size = sizeof(IMXI2CState),
324     .class_init = imx_i2c_class_init,
325 };
326 
327 static void imx_i2c_register_types(void)
328 {
329     type_register_static(&imx_i2c_type_info);
330 }
331 
332 type_init(imx_i2c_register_types)
333