120d0f9cfSJean-Christophe Dubois /* 220d0f9cfSJean-Christophe Dubois * i.MX I2C Bus Serial Interface Emulation 320d0f9cfSJean-Christophe Dubois * 420d0f9cfSJean-Christophe Dubois * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> 520d0f9cfSJean-Christophe Dubois * 620d0f9cfSJean-Christophe Dubois * This program is free software; you can redistribute it and/or modify it 720d0f9cfSJean-Christophe Dubois * under the terms of the GNU General Public License as published by the 820d0f9cfSJean-Christophe Dubois * Free Software Foundation; either version 2 of the License, or 920d0f9cfSJean-Christophe Dubois * (at your option) any later version. 1020d0f9cfSJean-Christophe Dubois * 1120d0f9cfSJean-Christophe Dubois * This program is distributed in the hope that it will be useful, but WITHOUT 1220d0f9cfSJean-Christophe Dubois * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1320d0f9cfSJean-Christophe Dubois * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1420d0f9cfSJean-Christophe Dubois * for more details. 1520d0f9cfSJean-Christophe Dubois * 1620d0f9cfSJean-Christophe Dubois * You should have received a copy of the GNU General Public License along 1720d0f9cfSJean-Christophe Dubois * with this program; if not, see <http://www.gnu.org/licenses/>. 1820d0f9cfSJean-Christophe Dubois * 1920d0f9cfSJean-Christophe Dubois */ 2020d0f9cfSJean-Christophe Dubois 21*8ef94f0bSPeter Maydell #include "qemu/osdep.h" 2220d0f9cfSJean-Christophe Dubois #include "hw/i2c/imx_i2c.h" 2320d0f9cfSJean-Christophe Dubois #include "hw/i2c/i2c.h" 2420d0f9cfSJean-Christophe Dubois 253afcbb01SJean-Christophe Dubois #ifndef DEBUG_IMX_I2C 263afcbb01SJean-Christophe Dubois #define DEBUG_IMX_I2C 0 2720d0f9cfSJean-Christophe Dubois #endif 2820d0f9cfSJean-Christophe Dubois 293afcbb01SJean-Christophe Dubois #define DPRINTF(fmt, args...) \ 303afcbb01SJean-Christophe Dubois do { \ 313afcbb01SJean-Christophe Dubois if (DEBUG_IMX_I2C) { \ 323afcbb01SJean-Christophe Dubois fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \ 333afcbb01SJean-Christophe Dubois __func__, ##args); \ 343afcbb01SJean-Christophe Dubois } \ 353afcbb01SJean-Christophe Dubois } while (0) 3620d0f9cfSJean-Christophe Dubois 3720d0f9cfSJean-Christophe Dubois static const char *imx_i2c_get_regname(unsigned offset) 3820d0f9cfSJean-Christophe Dubois { 3920d0f9cfSJean-Christophe Dubois switch (offset) { 4020d0f9cfSJean-Christophe Dubois case IADR_ADDR: 4120d0f9cfSJean-Christophe Dubois return "IADR"; 4220d0f9cfSJean-Christophe Dubois case IFDR_ADDR: 4320d0f9cfSJean-Christophe Dubois return "IFDR"; 4420d0f9cfSJean-Christophe Dubois case I2CR_ADDR: 4520d0f9cfSJean-Christophe Dubois return "I2CR"; 4620d0f9cfSJean-Christophe Dubois case I2SR_ADDR: 4720d0f9cfSJean-Christophe Dubois return "I2SR"; 4820d0f9cfSJean-Christophe Dubois case I2DR_ADDR: 4920d0f9cfSJean-Christophe Dubois return "I2DR"; 5020d0f9cfSJean-Christophe Dubois default: 5120d0f9cfSJean-Christophe Dubois return "[?]"; 5220d0f9cfSJean-Christophe Dubois } 5320d0f9cfSJean-Christophe Dubois } 5420d0f9cfSJean-Christophe Dubois 5520d0f9cfSJean-Christophe Dubois static inline bool imx_i2c_is_enabled(IMXI2CState *s) 5620d0f9cfSJean-Christophe Dubois { 5720d0f9cfSJean-Christophe Dubois return s->i2cr & I2CR_IEN; 5820d0f9cfSJean-Christophe Dubois } 5920d0f9cfSJean-Christophe Dubois 6020d0f9cfSJean-Christophe Dubois static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s) 6120d0f9cfSJean-Christophe Dubois { 6220d0f9cfSJean-Christophe Dubois return s->i2cr & I2CR_IIEN; 6320d0f9cfSJean-Christophe Dubois } 6420d0f9cfSJean-Christophe Dubois 6520d0f9cfSJean-Christophe Dubois static inline bool imx_i2c_is_master(IMXI2CState *s) 6620d0f9cfSJean-Christophe Dubois { 6720d0f9cfSJean-Christophe Dubois return s->i2cr & I2CR_MSTA; 6820d0f9cfSJean-Christophe Dubois } 6920d0f9cfSJean-Christophe Dubois 7020d0f9cfSJean-Christophe Dubois static void imx_i2c_reset(DeviceState *dev) 7120d0f9cfSJean-Christophe Dubois { 7220d0f9cfSJean-Christophe Dubois IMXI2CState *s = IMX_I2C(dev); 7320d0f9cfSJean-Christophe Dubois 7420d0f9cfSJean-Christophe Dubois if (s->address != ADDR_RESET) { 7520d0f9cfSJean-Christophe Dubois i2c_end_transfer(s->bus); 7620d0f9cfSJean-Christophe Dubois } 7720d0f9cfSJean-Christophe Dubois 7820d0f9cfSJean-Christophe Dubois s->address = ADDR_RESET; 7920d0f9cfSJean-Christophe Dubois s->iadr = IADR_RESET; 8020d0f9cfSJean-Christophe Dubois s->ifdr = IFDR_RESET; 8120d0f9cfSJean-Christophe Dubois s->i2cr = I2CR_RESET; 8220d0f9cfSJean-Christophe Dubois s->i2sr = I2SR_RESET; 8320d0f9cfSJean-Christophe Dubois s->i2dr_read = I2DR_RESET; 8420d0f9cfSJean-Christophe Dubois s->i2dr_write = I2DR_RESET; 8520d0f9cfSJean-Christophe Dubois } 8620d0f9cfSJean-Christophe Dubois 8720d0f9cfSJean-Christophe Dubois static inline void imx_i2c_raise_interrupt(IMXI2CState *s) 8820d0f9cfSJean-Christophe Dubois { 8920d0f9cfSJean-Christophe Dubois /* 9020d0f9cfSJean-Christophe Dubois * raise an interrupt if the device is enabled and it is configured 9120d0f9cfSJean-Christophe Dubois * to generate some interrupts. 9220d0f9cfSJean-Christophe Dubois */ 9320d0f9cfSJean-Christophe Dubois if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) { 9420d0f9cfSJean-Christophe Dubois s->i2sr |= I2SR_IIF; 9520d0f9cfSJean-Christophe Dubois qemu_irq_raise(s->irq); 9620d0f9cfSJean-Christophe Dubois } 9720d0f9cfSJean-Christophe Dubois } 9820d0f9cfSJean-Christophe Dubois 9920d0f9cfSJean-Christophe Dubois static uint64_t imx_i2c_read(void *opaque, hwaddr offset, 10020d0f9cfSJean-Christophe Dubois unsigned size) 10120d0f9cfSJean-Christophe Dubois { 10220d0f9cfSJean-Christophe Dubois uint16_t value; 10320d0f9cfSJean-Christophe Dubois IMXI2CState *s = IMX_I2C(opaque); 10420d0f9cfSJean-Christophe Dubois 10520d0f9cfSJean-Christophe Dubois switch (offset) { 10620d0f9cfSJean-Christophe Dubois case IADR_ADDR: 10720d0f9cfSJean-Christophe Dubois value = s->iadr; 10820d0f9cfSJean-Christophe Dubois break; 10920d0f9cfSJean-Christophe Dubois case IFDR_ADDR: 11020d0f9cfSJean-Christophe Dubois value = s->ifdr; 11120d0f9cfSJean-Christophe Dubois break; 11220d0f9cfSJean-Christophe Dubois case I2CR_ADDR: 11320d0f9cfSJean-Christophe Dubois value = s->i2cr; 11420d0f9cfSJean-Christophe Dubois break; 11520d0f9cfSJean-Christophe Dubois case I2SR_ADDR: 11620d0f9cfSJean-Christophe Dubois value = s->i2sr; 11720d0f9cfSJean-Christophe Dubois break; 11820d0f9cfSJean-Christophe Dubois case I2DR_ADDR: 11920d0f9cfSJean-Christophe Dubois value = s->i2dr_read; 12020d0f9cfSJean-Christophe Dubois 12120d0f9cfSJean-Christophe Dubois if (imx_i2c_is_master(s)) { 12220d0f9cfSJean-Christophe Dubois int ret = 0xff; 12320d0f9cfSJean-Christophe Dubois 12420d0f9cfSJean-Christophe Dubois if (s->address == ADDR_RESET) { 12520d0f9cfSJean-Christophe Dubois /* something is wrong as the address is not set */ 1263afcbb01SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read " 12720d0f9cfSJean-Christophe Dubois "without specifying the slave address\n", 12820d0f9cfSJean-Christophe Dubois TYPE_IMX_I2C, __func__); 12920d0f9cfSJean-Christophe Dubois } else if (s->i2cr & I2CR_MTX) { 1303afcbb01SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read " 13120d0f9cfSJean-Christophe Dubois "but MTX is set\n", TYPE_IMX_I2C, __func__); 13220d0f9cfSJean-Christophe Dubois } else { 13320d0f9cfSJean-Christophe Dubois /* get the next byte */ 13420d0f9cfSJean-Christophe Dubois ret = i2c_recv(s->bus); 13520d0f9cfSJean-Christophe Dubois 13620d0f9cfSJean-Christophe Dubois if (ret >= 0) { 13720d0f9cfSJean-Christophe Dubois imx_i2c_raise_interrupt(s); 13820d0f9cfSJean-Christophe Dubois } else { 1393afcbb01SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed " 14020d0f9cfSJean-Christophe Dubois "for device 0x%02x\n", TYPE_IMX_I2C, 14120d0f9cfSJean-Christophe Dubois __func__, s->address); 14220d0f9cfSJean-Christophe Dubois ret = 0xff; 14320d0f9cfSJean-Christophe Dubois } 14420d0f9cfSJean-Christophe Dubois } 14520d0f9cfSJean-Christophe Dubois 14620d0f9cfSJean-Christophe Dubois s->i2dr_read = ret; 14720d0f9cfSJean-Christophe Dubois } else { 1483afcbb01SJean-Christophe Dubois qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n", 14920d0f9cfSJean-Christophe Dubois TYPE_IMX_I2C, __func__); 15020d0f9cfSJean-Christophe Dubois } 15120d0f9cfSJean-Christophe Dubois break; 15220d0f9cfSJean-Christophe Dubois default: 1533afcbb01SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" 1543afcbb01SJean-Christophe Dubois HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset); 15520d0f9cfSJean-Christophe Dubois value = 0; 15620d0f9cfSJean-Christophe Dubois break; 15720d0f9cfSJean-Christophe Dubois } 15820d0f9cfSJean-Christophe Dubois 1593afcbb01SJean-Christophe Dubois DPRINTF("read %s [0x%" HWADDR_PRIx "] -> 0x%02x\n", 1603afcbb01SJean-Christophe Dubois imx_i2c_get_regname(offset), offset, value); 16120d0f9cfSJean-Christophe Dubois 16220d0f9cfSJean-Christophe Dubois return (uint64_t)value; 16320d0f9cfSJean-Christophe Dubois } 16420d0f9cfSJean-Christophe Dubois 16520d0f9cfSJean-Christophe Dubois static void imx_i2c_write(void *opaque, hwaddr offset, 16620d0f9cfSJean-Christophe Dubois uint64_t value, unsigned size) 16720d0f9cfSJean-Christophe Dubois { 16820d0f9cfSJean-Christophe Dubois IMXI2CState *s = IMX_I2C(opaque); 16920d0f9cfSJean-Christophe Dubois 1703afcbb01SJean-Christophe Dubois DPRINTF("write %s [0x%" HWADDR_PRIx "] <- 0x%02x\n", 1713afcbb01SJean-Christophe Dubois imx_i2c_get_regname(offset), offset, (int)value); 17220d0f9cfSJean-Christophe Dubois 17320d0f9cfSJean-Christophe Dubois value &= 0xff; 17420d0f9cfSJean-Christophe Dubois 17520d0f9cfSJean-Christophe Dubois switch (offset) { 17620d0f9cfSJean-Christophe Dubois case IADR_ADDR: 17720d0f9cfSJean-Christophe Dubois s->iadr = value & IADR_MASK; 17820d0f9cfSJean-Christophe Dubois /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */ 17920d0f9cfSJean-Christophe Dubois break; 18020d0f9cfSJean-Christophe Dubois case IFDR_ADDR: 18120d0f9cfSJean-Christophe Dubois s->ifdr = value & IFDR_MASK; 18220d0f9cfSJean-Christophe Dubois break; 18320d0f9cfSJean-Christophe Dubois case I2CR_ADDR: 18420d0f9cfSJean-Christophe Dubois if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) { 18520d0f9cfSJean-Christophe Dubois /* This is a soft reset. IADR is preserved during soft resets */ 18620d0f9cfSJean-Christophe Dubois uint16_t iadr = s->iadr; 18720d0f9cfSJean-Christophe Dubois imx_i2c_reset(DEVICE(s)); 18820d0f9cfSJean-Christophe Dubois s->iadr = iadr; 18920d0f9cfSJean-Christophe Dubois } else { /* normal write */ 19020d0f9cfSJean-Christophe Dubois s->i2cr = value & I2CR_MASK; 19120d0f9cfSJean-Christophe Dubois 19220d0f9cfSJean-Christophe Dubois if (imx_i2c_is_master(s)) { 19320d0f9cfSJean-Christophe Dubois /* set the bus to busy */ 19420d0f9cfSJean-Christophe Dubois s->i2sr |= I2SR_IBB; 19520d0f9cfSJean-Christophe Dubois } else { /* slave mode */ 19620d0f9cfSJean-Christophe Dubois /* bus is not busy anymore */ 19720d0f9cfSJean-Christophe Dubois s->i2sr &= ~I2SR_IBB; 19820d0f9cfSJean-Christophe Dubois 19920d0f9cfSJean-Christophe Dubois /* 20020d0f9cfSJean-Christophe Dubois * if we unset the master mode then it ends the ongoing 20120d0f9cfSJean-Christophe Dubois * transfer if any 20220d0f9cfSJean-Christophe Dubois */ 20320d0f9cfSJean-Christophe Dubois if (s->address != ADDR_RESET) { 20420d0f9cfSJean-Christophe Dubois i2c_end_transfer(s->bus); 20520d0f9cfSJean-Christophe Dubois s->address = ADDR_RESET; 20620d0f9cfSJean-Christophe Dubois } 20720d0f9cfSJean-Christophe Dubois } 20820d0f9cfSJean-Christophe Dubois 20920d0f9cfSJean-Christophe Dubois if (s->i2cr & I2CR_RSTA) { /* Restart */ 21020d0f9cfSJean-Christophe Dubois /* if this is a restart then it ends the ongoing transfer */ 21120d0f9cfSJean-Christophe Dubois if (s->address != ADDR_RESET) { 21220d0f9cfSJean-Christophe Dubois i2c_end_transfer(s->bus); 21320d0f9cfSJean-Christophe Dubois s->address = ADDR_RESET; 21420d0f9cfSJean-Christophe Dubois s->i2cr &= ~I2CR_RSTA; 21520d0f9cfSJean-Christophe Dubois } 21620d0f9cfSJean-Christophe Dubois } 21720d0f9cfSJean-Christophe Dubois } 21820d0f9cfSJean-Christophe Dubois break; 21920d0f9cfSJean-Christophe Dubois case I2SR_ADDR: 22020d0f9cfSJean-Christophe Dubois /* 22120d0f9cfSJean-Christophe Dubois * if the user writes 0 to IIF then lower the interrupt and 22220d0f9cfSJean-Christophe Dubois * reset the bit 22320d0f9cfSJean-Christophe Dubois */ 22420d0f9cfSJean-Christophe Dubois if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) { 22520d0f9cfSJean-Christophe Dubois s->i2sr &= ~I2SR_IIF; 22620d0f9cfSJean-Christophe Dubois qemu_irq_lower(s->irq); 22720d0f9cfSJean-Christophe Dubois } 22820d0f9cfSJean-Christophe Dubois 22920d0f9cfSJean-Christophe Dubois /* 23020d0f9cfSJean-Christophe Dubois * if the user writes 0 to IAL, reset the bit 23120d0f9cfSJean-Christophe Dubois */ 23220d0f9cfSJean-Christophe Dubois if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) { 23320d0f9cfSJean-Christophe Dubois s->i2sr &= ~I2SR_IAL; 23420d0f9cfSJean-Christophe Dubois } 23520d0f9cfSJean-Christophe Dubois 23620d0f9cfSJean-Christophe Dubois break; 23720d0f9cfSJean-Christophe Dubois case I2DR_ADDR: 23820d0f9cfSJean-Christophe Dubois /* if the device is not enabled, nothing to do */ 23920d0f9cfSJean-Christophe Dubois if (!imx_i2c_is_enabled(s)) { 24020d0f9cfSJean-Christophe Dubois break; 24120d0f9cfSJean-Christophe Dubois } 24220d0f9cfSJean-Christophe Dubois 24320d0f9cfSJean-Christophe Dubois s->i2dr_write = value & I2DR_MASK; 24420d0f9cfSJean-Christophe Dubois 24520d0f9cfSJean-Christophe Dubois if (imx_i2c_is_master(s)) { 24620d0f9cfSJean-Christophe Dubois /* If this is the first write cycle then it is the slave addr */ 24720d0f9cfSJean-Christophe Dubois if (s->address == ADDR_RESET) { 24820d0f9cfSJean-Christophe Dubois if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7), 24920d0f9cfSJean-Christophe Dubois extract32(s->i2dr_write, 0, 1))) { 25020d0f9cfSJean-Christophe Dubois /* if non zero is returned, the adress is not valid */ 25120d0f9cfSJean-Christophe Dubois s->i2sr |= I2SR_RXAK; 25220d0f9cfSJean-Christophe Dubois } else { 25320d0f9cfSJean-Christophe Dubois s->address = s->i2dr_write; 25420d0f9cfSJean-Christophe Dubois s->i2sr &= ~I2SR_RXAK; 25520d0f9cfSJean-Christophe Dubois imx_i2c_raise_interrupt(s); 25620d0f9cfSJean-Christophe Dubois } 25720d0f9cfSJean-Christophe Dubois } else { /* This is a normal data write */ 25820d0f9cfSJean-Christophe Dubois if (i2c_send(s->bus, s->i2dr_write)) { 25920d0f9cfSJean-Christophe Dubois /* if the target return non zero then end the transfer */ 26020d0f9cfSJean-Christophe Dubois s->i2sr |= I2SR_RXAK; 26120d0f9cfSJean-Christophe Dubois s->address = ADDR_RESET; 26220d0f9cfSJean-Christophe Dubois i2c_end_transfer(s->bus); 26320d0f9cfSJean-Christophe Dubois } else { 26420d0f9cfSJean-Christophe Dubois s->i2sr &= ~I2SR_RXAK; 26520d0f9cfSJean-Christophe Dubois imx_i2c_raise_interrupt(s); 26620d0f9cfSJean-Christophe Dubois } 26720d0f9cfSJean-Christophe Dubois } 26820d0f9cfSJean-Christophe Dubois } else { 2693afcbb01SJean-Christophe Dubois qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n", 27020d0f9cfSJean-Christophe Dubois TYPE_IMX_I2C, __func__); 27120d0f9cfSJean-Christophe Dubois } 27220d0f9cfSJean-Christophe Dubois break; 27320d0f9cfSJean-Christophe Dubois default: 2743afcbb01SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" 2753afcbb01SJean-Christophe Dubois HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset); 27620d0f9cfSJean-Christophe Dubois break; 27720d0f9cfSJean-Christophe Dubois } 27820d0f9cfSJean-Christophe Dubois } 27920d0f9cfSJean-Christophe Dubois 28020d0f9cfSJean-Christophe Dubois static const MemoryRegionOps imx_i2c_ops = { 28120d0f9cfSJean-Christophe Dubois .read = imx_i2c_read, 28220d0f9cfSJean-Christophe Dubois .write = imx_i2c_write, 28320d0f9cfSJean-Christophe Dubois .valid.min_access_size = 1, 28420d0f9cfSJean-Christophe Dubois .valid.max_access_size = 2, 28520d0f9cfSJean-Christophe Dubois .endianness = DEVICE_NATIVE_ENDIAN, 28620d0f9cfSJean-Christophe Dubois }; 28720d0f9cfSJean-Christophe Dubois 28820d0f9cfSJean-Christophe Dubois static const VMStateDescription imx_i2c_vmstate = { 28920d0f9cfSJean-Christophe Dubois .name = TYPE_IMX_I2C, 29020d0f9cfSJean-Christophe Dubois .version_id = 1, 29120d0f9cfSJean-Christophe Dubois .minimum_version_id = 1, 29220d0f9cfSJean-Christophe Dubois .fields = (VMStateField[]) { 29320d0f9cfSJean-Christophe Dubois VMSTATE_UINT16(address, IMXI2CState), 29420d0f9cfSJean-Christophe Dubois VMSTATE_UINT16(iadr, IMXI2CState), 29520d0f9cfSJean-Christophe Dubois VMSTATE_UINT16(ifdr, IMXI2CState), 29620d0f9cfSJean-Christophe Dubois VMSTATE_UINT16(i2cr, IMXI2CState), 29720d0f9cfSJean-Christophe Dubois VMSTATE_UINT16(i2sr, IMXI2CState), 29820d0f9cfSJean-Christophe Dubois VMSTATE_UINT16(i2dr_read, IMXI2CState), 29920d0f9cfSJean-Christophe Dubois VMSTATE_UINT16(i2dr_write, IMXI2CState), 30020d0f9cfSJean-Christophe Dubois VMSTATE_END_OF_LIST() 30120d0f9cfSJean-Christophe Dubois } 30220d0f9cfSJean-Christophe Dubois }; 30320d0f9cfSJean-Christophe Dubois 30420d0f9cfSJean-Christophe Dubois static void imx_i2c_realize(DeviceState *dev, Error **errp) 30520d0f9cfSJean-Christophe Dubois { 30620d0f9cfSJean-Christophe Dubois IMXI2CState *s = IMX_I2C(dev); 30720d0f9cfSJean-Christophe Dubois 30820d0f9cfSJean-Christophe Dubois memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C, 30920d0f9cfSJean-Christophe Dubois IMX_I2C_MEM_SIZE); 31020d0f9cfSJean-Christophe Dubois sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 31120d0f9cfSJean-Christophe Dubois sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 31220d0f9cfSJean-Christophe Dubois s->bus = i2c_init_bus(DEVICE(dev), "i2c"); 31320d0f9cfSJean-Christophe Dubois } 31420d0f9cfSJean-Christophe Dubois 31520d0f9cfSJean-Christophe Dubois static void imx_i2c_class_init(ObjectClass *klass, void *data) 31620d0f9cfSJean-Christophe Dubois { 31720d0f9cfSJean-Christophe Dubois DeviceClass *dc = DEVICE_CLASS(klass); 31820d0f9cfSJean-Christophe Dubois 31920d0f9cfSJean-Christophe Dubois dc->vmsd = &imx_i2c_vmstate; 32020d0f9cfSJean-Christophe Dubois dc->reset = imx_i2c_reset; 32120d0f9cfSJean-Christophe Dubois dc->realize = imx_i2c_realize; 32220d0f9cfSJean-Christophe Dubois } 32320d0f9cfSJean-Christophe Dubois 32420d0f9cfSJean-Christophe Dubois static const TypeInfo imx_i2c_type_info = { 32520d0f9cfSJean-Christophe Dubois .name = TYPE_IMX_I2C, 32620d0f9cfSJean-Christophe Dubois .parent = TYPE_SYS_BUS_DEVICE, 32720d0f9cfSJean-Christophe Dubois .instance_size = sizeof(IMXI2CState), 32820d0f9cfSJean-Christophe Dubois .class_init = imx_i2c_class_init, 32920d0f9cfSJean-Christophe Dubois }; 33020d0f9cfSJean-Christophe Dubois 33120d0f9cfSJean-Christophe Dubois static void imx_i2c_register_types(void) 33220d0f9cfSJean-Christophe Dubois { 33320d0f9cfSJean-Christophe Dubois type_register_static(&imx_i2c_type_info); 33420d0f9cfSJean-Christophe Dubois } 33520d0f9cfSJean-Christophe Dubois 33620d0f9cfSJean-Christophe Dubois type_init(imx_i2c_register_types) 337