1 /* 2 * Exynos4210 I2C Bus Serial Interface Emulation 3 * 4 * Copyright (C) 2012 Samsung Electronics Co Ltd. 5 * Maksim Kozlov, <m.kozlov@samsung.com> 6 * Igor Mitsyanko, <i.mitsyanko@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 * 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/timer.h" 25 #include "hw/sysbus.h" 26 #include "hw/i2c/i2c.h" 27 28 #ifndef EXYNOS4_I2C_DEBUG 29 #define EXYNOS4_I2C_DEBUG 0 30 #endif 31 32 #define TYPE_EXYNOS4_I2C "exynos4210.i2c" 33 #define EXYNOS4_I2C(obj) \ 34 OBJECT_CHECK(Exynos4210I2CState, (obj), TYPE_EXYNOS4_I2C) 35 36 /* Exynos4210 I2C memory map */ 37 #define EXYNOS4_I2C_MEM_SIZE 0x14 38 #define I2CCON_ADDR 0x00 /* control register */ 39 #define I2CSTAT_ADDR 0x04 /* control/status register */ 40 #define I2CADD_ADDR 0x08 /* address register */ 41 #define I2CDS_ADDR 0x0c /* data shift register */ 42 #define I2CLC_ADDR 0x10 /* line control register */ 43 44 #define I2CCON_ACK_GEN (1 << 7) 45 #define I2CCON_INTRS_EN (1 << 5) 46 #define I2CCON_INT_PEND (1 << 4) 47 48 #define EXYNOS4_I2C_MODE(reg) (((reg) >> 6) & 3) 49 #define I2C_IN_MASTER_MODE(reg) (((reg) >> 6) & 2) 50 #define I2CMODE_MASTER_Rx 0x2 51 #define I2CMODE_MASTER_Tx 0x3 52 #define I2CSTAT_LAST_BIT (1 << 0) 53 #define I2CSTAT_OUTPUT_EN (1 << 4) 54 #define I2CSTAT_START_BUSY (1 << 5) 55 56 57 #if EXYNOS4_I2C_DEBUG 58 #define DPRINT(fmt, args...) \ 59 do { fprintf(stderr, "QEMU I2C: "fmt, ## args); } while (0) 60 61 static const char *exynos4_i2c_get_regname(unsigned offset) 62 { 63 switch (offset) { 64 case I2CCON_ADDR: 65 return "I2CCON"; 66 case I2CSTAT_ADDR: 67 return "I2CSTAT"; 68 case I2CADD_ADDR: 69 return "I2CADD"; 70 case I2CDS_ADDR: 71 return "I2CDS"; 72 case I2CLC_ADDR: 73 return "I2CLC"; 74 default: 75 return "[?]"; 76 } 77 } 78 79 #else 80 #define DPRINT(fmt, args...) do { } while (0) 81 #endif 82 83 typedef struct Exynos4210I2CState { 84 SysBusDevice parent_obj; 85 86 MemoryRegion iomem; 87 I2CBus *bus; 88 qemu_irq irq; 89 90 uint8_t i2ccon; 91 uint8_t i2cstat; 92 uint8_t i2cadd; 93 uint8_t i2cds; 94 uint8_t i2clc; 95 bool scl_free; 96 } Exynos4210I2CState; 97 98 static inline void exynos4210_i2c_raise_interrupt(Exynos4210I2CState *s) 99 { 100 if (s->i2ccon & I2CCON_INTRS_EN) { 101 s->i2ccon |= I2CCON_INT_PEND; 102 qemu_irq_raise(s->irq); 103 } 104 } 105 106 static void exynos4210_i2c_data_receive(void *opaque) 107 { 108 Exynos4210I2CState *s = (Exynos4210I2CState *)opaque; 109 110 s->i2cstat &= ~I2CSTAT_LAST_BIT; 111 s->scl_free = false; 112 s->i2cds = i2c_recv(s->bus); 113 exynos4210_i2c_raise_interrupt(s); 114 } 115 116 static void exynos4210_i2c_data_send(void *opaque) 117 { 118 Exynos4210I2CState *s = (Exynos4210I2CState *)opaque; 119 120 s->i2cstat &= ~I2CSTAT_LAST_BIT; 121 s->scl_free = false; 122 if (i2c_send(s->bus, s->i2cds) < 0 && (s->i2ccon & I2CCON_ACK_GEN)) { 123 s->i2cstat |= I2CSTAT_LAST_BIT; 124 } 125 exynos4210_i2c_raise_interrupt(s); 126 } 127 128 static uint64_t exynos4210_i2c_read(void *opaque, hwaddr offset, 129 unsigned size) 130 { 131 Exynos4210I2CState *s = (Exynos4210I2CState *)opaque; 132 uint8_t value; 133 134 switch (offset) { 135 case I2CCON_ADDR: 136 value = s->i2ccon; 137 break; 138 case I2CSTAT_ADDR: 139 value = s->i2cstat; 140 break; 141 case I2CADD_ADDR: 142 value = s->i2cadd; 143 break; 144 case I2CDS_ADDR: 145 value = s->i2cds; 146 s->scl_free = true; 147 if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Rx && 148 (s->i2cstat & I2CSTAT_START_BUSY) && 149 !(s->i2ccon & I2CCON_INT_PEND)) { 150 exynos4210_i2c_data_receive(s); 151 } 152 break; 153 case I2CLC_ADDR: 154 value = s->i2clc; 155 break; 156 default: 157 value = 0; 158 DPRINT("ERROR: Bad read offset 0x%x\n", (unsigned int)offset); 159 break; 160 } 161 162 DPRINT("read %s [0x%02x] -> 0x%02x\n", exynos4_i2c_get_regname(offset), 163 (unsigned int)offset, value); 164 return value; 165 } 166 167 static void exynos4210_i2c_write(void *opaque, hwaddr offset, 168 uint64_t value, unsigned size) 169 { 170 Exynos4210I2CState *s = (Exynos4210I2CState *)opaque; 171 uint8_t v = value & 0xff; 172 173 DPRINT("write %s [0x%02x] <- 0x%02x\n", exynos4_i2c_get_regname(offset), 174 (unsigned int)offset, v); 175 176 switch (offset) { 177 case I2CCON_ADDR: 178 s->i2ccon = (v & ~I2CCON_INT_PEND) | (s->i2ccon & I2CCON_INT_PEND); 179 if ((s->i2ccon & I2CCON_INT_PEND) && !(v & I2CCON_INT_PEND)) { 180 s->i2ccon &= ~I2CCON_INT_PEND; 181 qemu_irq_lower(s->irq); 182 if (!(s->i2ccon & I2CCON_INTRS_EN)) { 183 s->i2cstat &= ~I2CSTAT_START_BUSY; 184 } 185 186 if (s->i2cstat & I2CSTAT_START_BUSY) { 187 if (s->scl_free) { 188 if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Tx) { 189 exynos4210_i2c_data_send(s); 190 } else if (EXYNOS4_I2C_MODE(s->i2cstat) == 191 I2CMODE_MASTER_Rx) { 192 exynos4210_i2c_data_receive(s); 193 } 194 } else { 195 s->i2ccon |= I2CCON_INT_PEND; 196 qemu_irq_raise(s->irq); 197 } 198 } 199 } 200 break; 201 case I2CSTAT_ADDR: 202 s->i2cstat = 203 (s->i2cstat & I2CSTAT_START_BUSY) | (v & ~I2CSTAT_START_BUSY); 204 205 if (!(s->i2cstat & I2CSTAT_OUTPUT_EN)) { 206 s->i2cstat &= ~I2CSTAT_START_BUSY; 207 s->scl_free = true; 208 qemu_irq_lower(s->irq); 209 break; 210 } 211 212 /* Nothing to do if in i2c slave mode */ 213 if (!I2C_IN_MASTER_MODE(s->i2cstat)) { 214 break; 215 } 216 217 if (v & I2CSTAT_START_BUSY) { 218 s->i2cstat &= ~I2CSTAT_LAST_BIT; 219 s->i2cstat |= I2CSTAT_START_BUSY; /* Line is busy */ 220 s->scl_free = false; 221 222 /* Generate start bit and send slave address */ 223 if (i2c_start_transfer(s->bus, s->i2cds >> 1, s->i2cds & 0x1) && 224 (s->i2ccon & I2CCON_ACK_GEN)) { 225 s->i2cstat |= I2CSTAT_LAST_BIT; 226 } else if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Rx) { 227 exynos4210_i2c_data_receive(s); 228 } 229 exynos4210_i2c_raise_interrupt(s); 230 } else { 231 i2c_end_transfer(s->bus); 232 if (!(s->i2ccon & I2CCON_INT_PEND)) { 233 s->i2cstat &= ~I2CSTAT_START_BUSY; 234 } 235 s->scl_free = true; 236 } 237 break; 238 case I2CADD_ADDR: 239 if ((s->i2cstat & I2CSTAT_OUTPUT_EN) == 0) { 240 s->i2cadd = v; 241 } 242 break; 243 case I2CDS_ADDR: 244 if (s->i2cstat & I2CSTAT_OUTPUT_EN) { 245 s->i2cds = v; 246 s->scl_free = true; 247 if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Tx && 248 (s->i2cstat & I2CSTAT_START_BUSY) && 249 !(s->i2ccon & I2CCON_INT_PEND)) { 250 exynos4210_i2c_data_send(s); 251 } 252 } 253 break; 254 case I2CLC_ADDR: 255 s->i2clc = v; 256 break; 257 default: 258 DPRINT("ERROR: Bad write offset 0x%x\n", (unsigned int)offset); 259 break; 260 } 261 } 262 263 static const MemoryRegionOps exynos4210_i2c_ops = { 264 .read = exynos4210_i2c_read, 265 .write = exynos4210_i2c_write, 266 .endianness = DEVICE_NATIVE_ENDIAN, 267 }; 268 269 static const VMStateDescription exynos4210_i2c_vmstate = { 270 .name = "exynos4210.i2c", 271 .version_id = 1, 272 .minimum_version_id = 1, 273 .fields = (VMStateField[]) { 274 VMSTATE_UINT8(i2ccon, Exynos4210I2CState), 275 VMSTATE_UINT8(i2cstat, Exynos4210I2CState), 276 VMSTATE_UINT8(i2cds, Exynos4210I2CState), 277 VMSTATE_UINT8(i2cadd, Exynos4210I2CState), 278 VMSTATE_UINT8(i2clc, Exynos4210I2CState), 279 VMSTATE_BOOL(scl_free, Exynos4210I2CState), 280 VMSTATE_END_OF_LIST() 281 } 282 }; 283 284 static void exynos4210_i2c_reset(DeviceState *d) 285 { 286 Exynos4210I2CState *s = EXYNOS4_I2C(d); 287 288 s->i2ccon = 0x00; 289 s->i2cstat = 0x00; 290 s->i2cds = 0xFF; 291 s->i2clc = 0x00; 292 s->i2cadd = 0xFF; 293 s->scl_free = true; 294 } 295 296 static void exynos4210_i2c_init(Object *obj) 297 { 298 DeviceState *dev = DEVICE(obj); 299 Exynos4210I2CState *s = EXYNOS4_I2C(obj); 300 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 301 302 memory_region_init_io(&s->iomem, obj, &exynos4210_i2c_ops, s, 303 TYPE_EXYNOS4_I2C, EXYNOS4_I2C_MEM_SIZE); 304 sysbus_init_mmio(sbd, &s->iomem); 305 sysbus_init_irq(sbd, &s->irq); 306 s->bus = i2c_init_bus(dev, "i2c"); 307 } 308 309 static void exynos4210_i2c_class_init(ObjectClass *klass, void *data) 310 { 311 DeviceClass *dc = DEVICE_CLASS(klass); 312 313 dc->vmsd = &exynos4210_i2c_vmstate; 314 dc->reset = exynos4210_i2c_reset; 315 } 316 317 static const TypeInfo exynos4210_i2c_type_info = { 318 .name = TYPE_EXYNOS4_I2C, 319 .parent = TYPE_SYS_BUS_DEVICE, 320 .instance_size = sizeof(Exynos4210I2CState), 321 .instance_init = exynos4210_i2c_init, 322 .class_init = exynos4210_i2c_class_init, 323 }; 324 325 static void exynos4210_i2c_register_types(void) 326 { 327 type_register_static(&exynos4210_i2c_type_info); 328 } 329 330 type_init(exynos4210_i2c_register_types) 331