1 /* 2 * ARM Aspeed I2C controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "qemu/cutils.h" 25 #include "qemu/log.h" 26 #include "qemu/module.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "hw/i2c/aspeed_i2c.h" 30 #include "hw/irq.h" 31 #include "hw/qdev-properties.h" 32 #include "hw/registerfields.h" 33 #include "trace.h" 34 35 /* Enable SLAVE_ADDR_RX_MATCH always */ 36 #define R_I2CD_INTR_STS_ALWAYS_ENABLE R_I2CD_INTR_STS_SLAVE_ADDR_RX_MATCH_MASK 37 38 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) 39 { 40 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 41 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 42 uint32_t intr_ctrl_reg = aspeed_i2c_bus_intr_ctrl_offset(bus); 43 uint32_t intr_ctrl_mask = bus->regs[intr_ctrl_reg] | 44 R_I2CD_INTR_STS_ALWAYS_ENABLE; 45 bool raise_irq; 46 47 if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT)) { 48 g_autofree char *buf = g_strdup_printf("%s%s%s%s%s%s%s", 49 aspeed_i2c_bus_pkt_mode_en(bus) && 50 ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ? 51 "pktdone|" : "", 52 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_NAK) ? 53 "nak|" : "", 54 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_ACK) ? 55 "ack|" : "", 56 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE) ? 57 "done|" : "", 58 ARRAY_FIELD_EX32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH) ? 59 "slave-match|" : "", 60 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, NORMAL_STOP) ? 61 "normal|" : "", 62 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, ABNORMAL) ? 63 "abnormal" : ""); 64 65 trace_aspeed_i2c_bus_raise_interrupt(bus->regs[reg_intr_sts], buf); 66 } 67 68 raise_irq = bus->regs[reg_intr_sts] & intr_ctrl_mask ; 69 70 /* In packet mode we don't mask off INTR_STS */ 71 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { 72 bus->regs[reg_intr_sts] &= intr_ctrl_mask; 73 } 74 75 if (raise_irq) { 76 bus->controller->intr_status |= 1 << bus->id; 77 qemu_irq_raise(aic->bus_get_irq(bus)); 78 } 79 } 80 81 static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, 82 unsigned size) 83 { 84 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 85 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; 86 87 switch (offset) { 88 case A_I2CD_FUN_CTRL: 89 case A_I2CD_AC_TIMING1: 90 case A_I2CD_AC_TIMING2: 91 case A_I2CD_INTR_CTRL: 92 case A_I2CD_INTR_STS: 93 case A_I2CD_DEV_ADDR: 94 case A_I2CD_POOL_CTRL: 95 case A_I2CD_BYTE_BUF: 96 /* Value is already set, don't do anything. */ 97 break; 98 case A_I2CD_CMD: 99 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); 100 break; 101 case A_I2CD_DMA_ADDR: 102 if (!aic->has_dma) { 103 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 104 value = -1; 105 } 106 break; 107 case A_I2CD_DMA_LEN: 108 if (!aic->has_dma) { 109 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 110 value = -1; 111 } 112 break; 113 114 default: 115 qemu_log_mask(LOG_GUEST_ERROR, 116 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 117 value = -1; 118 break; 119 } 120 121 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); 122 return value; 123 } 124 125 static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, 126 unsigned size) 127 { 128 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; 129 130 switch (offset) { 131 case A_I2CC_FUN_CTRL: 132 case A_I2CC_AC_TIMING: 133 case A_I2CC_POOL_CTRL: 134 case A_I2CM_INTR_CTRL: 135 case A_I2CM_INTR_STS: 136 case A_I2CC_MS_TXRX_BYTE_BUF: 137 case A_I2CM_DMA_LEN: 138 case A_I2CM_DMA_TX_ADDR: 139 case A_I2CM_DMA_RX_ADDR: 140 case A_I2CM_DMA_LEN_STS: 141 case A_I2CC_DMA_ADDR: 142 case A_I2CC_DMA_LEN: 143 /* Value is already set, don't do anything. */ 144 break; 145 case A_I2CM_CMD: 146 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); 147 break; 148 default: 149 qemu_log_mask(LOG_GUEST_ERROR, 150 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 151 value = -1; 152 break; 153 } 154 155 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); 156 return value; 157 } 158 159 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, 160 unsigned size) 161 { 162 AspeedI2CBus *bus = opaque; 163 if (aspeed_i2c_is_new_mode(bus->controller)) { 164 return aspeed_i2c_bus_new_read(bus, offset, size); 165 } 166 return aspeed_i2c_bus_old_read(bus, offset, size); 167 } 168 169 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) 170 { 171 if (aspeed_i2c_is_new_mode(bus->controller)) { 172 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_STATE, 173 state); 174 } else { 175 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_CMD, TX_STATE, state); 176 } 177 } 178 179 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) 180 { 181 if (aspeed_i2c_is_new_mode(bus->controller)) { 182 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, 183 TX_STATE); 184 } 185 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, TX_STATE); 186 } 187 188 static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data) 189 { 190 MemTxResult result; 191 AspeedI2CState *s = bus->controller; 192 uint32_t reg_dma_addr = aspeed_i2c_bus_dma_addr_offset(bus); 193 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 194 195 result = address_space_read(&s->dram_as, bus->regs[reg_dma_addr], 196 MEMTXATTRS_UNSPECIFIED, data, 1); 197 if (result != MEMTX_OK) { 198 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n", 199 __func__, bus->regs[reg_dma_addr]); 200 return -1; 201 } 202 203 bus->regs[reg_dma_addr]++; 204 bus->regs[reg_dma_len]--; 205 return 0; 206 } 207 208 static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) 209 { 210 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 211 int ret = -1; 212 int i; 213 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 214 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 215 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 216 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 217 int pool_tx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, 218 TX_COUNT); 219 220 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 221 for (i = pool_start; i < pool_tx_count; i++) { 222 uint8_t *pool_base = aic->bus_pool_base(bus); 223 224 trace_aspeed_i2c_bus_send("BUF", i + 1, pool_tx_count, 225 pool_base[i]); 226 ret = i2c_send(bus->bus, pool_base[i]); 227 if (ret) { 228 break; 229 } 230 } 231 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_BUFF_EN, 0); 232 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 233 /* In new mode, clear how many bytes we TXed */ 234 if (aspeed_i2c_is_new_mode(bus->controller)) { 235 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); 236 } 237 while (bus->regs[reg_dma_len]) { 238 uint8_t data; 239 aspeed_i2c_dma_read(bus, &data); 240 trace_aspeed_i2c_bus_send("DMA", bus->regs[reg_dma_len], 241 bus->regs[reg_dma_len], data); 242 ret = i2c_send(bus->bus, data); 243 if (ret) { 244 break; 245 } 246 /* In new mode, keep track of how many bytes we TXed */ 247 if (aspeed_i2c_is_new_mode(bus->controller)) { 248 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 249 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, 250 TX_LEN) + 1); 251 } 252 } 253 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); 254 } else { 255 trace_aspeed_i2c_bus_send("BYTE", pool_start, 1, 256 bus->regs[reg_byte_buf]); 257 ret = i2c_send(bus->bus, bus->regs[reg_byte_buf]); 258 } 259 260 return ret; 261 } 262 263 static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) 264 { 265 AspeedI2CState *s = bus->controller; 266 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 267 uint8_t data; 268 int i; 269 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 270 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 271 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 272 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 273 uint32_t reg_dma_addr = aspeed_i2c_bus_dma_addr_offset(bus); 274 int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, 275 RX_COUNT); 276 277 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { 278 uint8_t *pool_base = aic->bus_pool_base(bus); 279 280 for (i = 0; i < pool_rx_count; i++) { 281 pool_base[i] = i2c_recv(bus->bus); 282 trace_aspeed_i2c_bus_recv("BUF", i + 1, pool_rx_count, 283 pool_base[i]); 284 } 285 286 /* Update RX count */ 287 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_pool_ctrl, RX_COUNT, i & 0xff); 288 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_BUFF_EN, 0); 289 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { 290 uint8_t data; 291 /* In new mode, clear how many bytes we RXed */ 292 if (aspeed_i2c_is_new_mode(bus->controller)) { 293 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); 294 } 295 296 while (bus->regs[reg_dma_len]) { 297 MemTxResult result; 298 299 data = i2c_recv(bus->bus); 300 trace_aspeed_i2c_bus_recv("DMA", bus->regs[reg_dma_len], 301 bus->regs[reg_dma_len], data); 302 result = address_space_write(&s->dram_as, bus->regs[reg_dma_addr], 303 MEMTXATTRS_UNSPECIFIED, &data, 1); 304 if (result != MEMTX_OK) { 305 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n", 306 __func__, bus->regs[reg_dma_addr]); 307 return; 308 } 309 bus->regs[reg_dma_addr]++; 310 bus->regs[reg_dma_len]--; 311 /* In new mode, keep track of how many bytes we RXed */ 312 if (aspeed_i2c_is_new_mode(bus->controller)) { 313 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 314 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, 315 RX_LEN) + 1); 316 } 317 } 318 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_DMA_EN, 0); 319 } else { 320 data = i2c_recv(bus->bus); 321 trace_aspeed_i2c_bus_recv("BYTE", 1, 1, bus->regs[reg_byte_buf]); 322 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); 323 } 324 } 325 326 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) 327 { 328 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 329 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 330 331 aspeed_i2c_set_state(bus, I2CD_MRXD); 332 aspeed_i2c_bus_recv(bus); 333 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); 334 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) { 335 i2c_nack(bus->bus); 336 } 337 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_RX_CMD, 0); 338 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_S_RX_CMD_LAST, 0); 339 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 340 } 341 342 static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) 343 { 344 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 345 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 346 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 347 348 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 349 return (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_DEV_ADDR) << 1) | 350 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD); 351 } 352 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 353 uint8_t *pool_base = aic->bus_pool_base(bus); 354 355 return pool_base[0]; 356 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 357 uint8_t data; 358 359 aspeed_i2c_dma_read(bus, &data); 360 return data; 361 } else { 362 return bus->regs[reg_byte_buf]; 363 } 364 } 365 366 static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) 367 { 368 AspeedI2CState *s = bus->controller; 369 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 370 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 371 bool dma_en = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) || 372 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) || 373 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) || 374 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN); 375 if (!aic->check_sram) { 376 return true; 377 } 378 379 /* 380 * AST2500: SRAM must be enabled before using the Buffer Pool or 381 * DMA mode. 382 */ 383 if (!FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, SRAM_EN) && dma_en) { 384 qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__); 385 return false; 386 } 387 388 return true; 389 } 390 391 static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) 392 { 393 g_autofree char *cmd_flags = NULL; 394 uint32_t count; 395 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 396 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 397 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 398 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 399 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { 400 count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT); 401 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { 402 count = bus->regs[reg_dma_len]; 403 } else { /* BYTE mode */ 404 count = 1; 405 } 406 407 cmd_flags = g_strdup_printf("%s%s%s%s%s%s%s%s%s", 408 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD) ? "start|" : "", 409 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) ? "rxdma|" : "", 410 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) ? "txdma|" : "", 411 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) ? "rxbuf|" : "", 412 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN) ? "txbuf|" : "", 413 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD) ? "tx|" : "", 414 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) ? "rx|" : "", 415 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST) ? "last|" : "", 416 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD) ? "stop|" : ""); 417 418 trace_aspeed_i2c_bus_cmd(bus->regs[reg_cmd], cmd_flags, count, 419 bus->regs[reg_intr_sts]); 420 } 421 422 /* 423 * The state machine needs some refinement. It is only used to track 424 * invalid STOP commands for the moment. 425 */ 426 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 427 { 428 uint8_t pool_start = 0; 429 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 430 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 431 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 432 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 433 434 if (!aspeed_i2c_check_sram(bus)) { 435 return; 436 } 437 438 if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_CMD)) { 439 aspeed_i2c_bus_cmd_dump(bus); 440 } 441 442 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD)) { 443 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? 444 I2CD_MSTARTR : I2CD_MSTART; 445 uint8_t addr; 446 447 aspeed_i2c_set_state(bus, state); 448 449 addr = aspeed_i2c_get_addr(bus); 450 if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), 451 extract32(addr, 0, 1))) { 452 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); 453 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 454 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 455 } 456 } else { 457 /* START doesn't set TX_ACK in packet mode */ 458 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { 459 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); 460 } 461 } 462 463 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_START_CMD, 0); 464 465 /* 466 * The START command is also a TX command, as the slave 467 * address is sent on the bus. Drop the TX flag if nothing 468 * else needs to be sent in this sequence. 469 */ 470 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 471 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) 472 == 1) { 473 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 474 } else { 475 /* 476 * Increase the start index in the TX pool buffer to 477 * skip the address byte. 478 */ 479 pool_start++; 480 } 481 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 482 if (bus->regs[reg_dma_len] == 0) { 483 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 484 } 485 } else { 486 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 487 } 488 489 /* No slave found */ 490 if (!i2c_bus_busy(bus->bus)) { 491 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 492 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 493 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); 494 } 495 return; 496 } 497 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 498 } 499 500 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD)) { 501 aspeed_i2c_set_state(bus, I2CD_MTXD); 502 if (aspeed_i2c_bus_send(bus, pool_start)) { 503 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); 504 i2c_end_transfer(bus->bus); 505 } else { 506 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); 507 } 508 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 509 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 510 } 511 512 if ((SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) || 513 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) && 514 !SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE)) { 515 aspeed_i2c_handle_rx_cmd(bus); 516 } 517 518 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD)) { 519 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { 520 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); 521 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, ABNORMAL, 1); 522 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 523 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 524 } 525 } else { 526 aspeed_i2c_set_state(bus, I2CD_MSTOP); 527 i2c_end_transfer(bus->bus); 528 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); 529 } 530 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0); 531 aspeed_i2c_set_state(bus, I2CD_IDLE); 532 } 533 534 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 535 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); 536 } 537 } 538 539 static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset, 540 uint64_t value, unsigned size) 541 { 542 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 543 bool handle_rx; 544 bool w1t; 545 546 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); 547 548 switch (offset) { 549 case A_I2CC_FUN_CTRL: 550 if (SHARED_FIELD_EX32(value, SLAVE_EN)) { 551 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 552 __func__); 553 break; 554 } 555 bus->regs[R_I2CD_FUN_CTRL] = value & 0x007dc3ff; 556 break; 557 case A_I2CC_AC_TIMING: 558 bus->regs[R_I2CC_AC_TIMING] = value & 0x1ffff0ff; 559 break; 560 case A_I2CC_MS_TXRX_BYTE_BUF: 561 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_BUF, 562 value); 563 break; 564 case A_I2CC_POOL_CTRL: 565 bus->regs[R_I2CC_POOL_CTRL] &= ~0xffffff; 566 bus->regs[R_I2CC_POOL_CTRL] |= (value & 0xffffff); 567 break; 568 case A_I2CM_INTR_CTRL: 569 bus->regs[R_I2CM_INTR_CTRL] = value & 0x0007f07f; 570 break; 571 case A_I2CM_INTR_STS: 572 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_INTR_STS, RX_DONE) 573 && SHARED_FIELD_EX32(value, RX_DONE); 574 575 /* In packet mode, clearing PKT_CMD_DONE clears other interrupts. */ 576 if (aspeed_i2c_bus_pkt_mode_en(bus) && 577 FIELD_EX32(value, I2CM_INTR_STS, PKT_CMD_DONE)) { 578 bus->regs[R_I2CM_INTR_STS] &= 0xf0001000; 579 if (!bus->regs[R_I2CM_INTR_STS]) { 580 bus->controller->intr_status &= ~(1 << bus->id); 581 qemu_irq_lower(aic->bus_get_irq(bus)); 582 } 583 break; 584 } 585 bus->regs[R_I2CM_INTR_STS] &= ~(value & 0xf007f07f); 586 if (!bus->regs[R_I2CM_INTR_STS]) { 587 bus->controller->intr_status &= ~(1 << bus->id); 588 qemu_irq_lower(aic->bus_get_irq(bus)); 589 } 590 if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, 591 M_RX_CMD) || 592 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, 593 M_S_RX_CMD_LAST))) { 594 aspeed_i2c_handle_rx_cmd(bus); 595 aspeed_i2c_bus_raise_interrupt(bus); 596 } 597 break; 598 case A_I2CM_CMD: 599 if (!aspeed_i2c_bus_is_enabled(bus)) { 600 break; 601 } 602 603 if (!aspeed_i2c_bus_is_master(bus)) { 604 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 605 __func__); 606 break; 607 } 608 609 if (!aic->has_dma && 610 (SHARED_FIELD_EX32(value, RX_DMA_EN) || 611 SHARED_FIELD_EX32(value, TX_DMA_EN))) { 612 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 613 break; 614 } 615 616 if (bus->regs[R_I2CM_INTR_STS] & 0xffff0000) { 617 qemu_log_mask(LOG_UNIMP, "%s: Packet mode is not implemented\n", 618 __func__); 619 break; 620 } 621 622 value &= 0xff0ffbfb; 623 if (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, W1_CTRL)) { 624 bus->regs[R_I2CM_CMD] |= value; 625 } else { 626 bus->regs[R_I2CM_CMD] = value; 627 } 628 629 aspeed_i2c_bus_handle_cmd(bus, value); 630 aspeed_i2c_bus_raise_interrupt(bus); 631 break; 632 case A_I2CM_DMA_TX_ADDR: 633 bus->regs[R_I2CM_DMA_TX_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR, 634 ADDR); 635 bus->regs[R_I2CC_DMA_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR); 636 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, 637 TX_BUF_LEN) + 1; 638 break; 639 case A_I2CM_DMA_RX_ADDR: 640 bus->regs[R_I2CM_DMA_RX_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR, 641 ADDR); 642 bus->regs[R_I2CC_DMA_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR); 643 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, 644 RX_BUF_LEN) + 1; 645 break; 646 case A_I2CM_DMA_LEN: 647 w1t = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T) || 648 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T); 649 /* If none of the w1t bits are set, just write to the reg as normal. */ 650 if (!w1t) { 651 bus->regs[R_I2CM_DMA_LEN] = value; 652 break; 653 } 654 if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) { 655 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN, 656 FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN)); 657 } 658 if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) { 659 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN, 660 FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN)); 661 } 662 break; 663 case A_I2CM_DMA_LEN_STS: 664 /* Writes clear to 0 */ 665 bus->regs[R_I2CM_DMA_LEN_STS] = 0; 666 break; 667 case A_I2CC_DMA_ADDR: 668 case A_I2CC_DMA_LEN: 669 /* RO */ 670 break; 671 case A_I2CS_DMA_LEN_STS: 672 case A_I2CS_DMA_TX_ADDR: 673 case A_I2CS_DMA_RX_ADDR: 674 case A_I2CS_DEV_ADDR: 675 case A_I2CS_INTR_CTRL: 676 case A_I2CS_INTR_STS: 677 case A_I2CS_CMD: 678 case A_I2CS_DMA_LEN: 679 qemu_log_mask(LOG_UNIMP, "%s: Slave mode is not implemented\n", 680 __func__); 681 break; 682 default: 683 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 684 __func__, offset); 685 } 686 } 687 688 static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset, 689 uint64_t value, unsigned size) 690 { 691 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 692 bool handle_rx; 693 694 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); 695 696 switch (offset) { 697 case A_I2CD_FUN_CTRL: 698 if (SHARED_FIELD_EX32(value, SLAVE_EN)) { 699 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 700 __func__); 701 break; 702 } 703 bus->regs[R_I2CD_FUN_CTRL] = value & 0x0071C3FF; 704 break; 705 case A_I2CD_AC_TIMING1: 706 bus->regs[R_I2CD_AC_TIMING1] = value & 0xFFFFF0F; 707 break; 708 case A_I2CD_AC_TIMING2: 709 bus->regs[R_I2CD_AC_TIMING2] = value & 0x7; 710 break; 711 case A_I2CD_INTR_CTRL: 712 bus->regs[R_I2CD_INTR_CTRL] = value & 0x7FFF; 713 break; 714 case A_I2CD_INTR_STS: 715 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_INTR_STS, RX_DONE) 716 && SHARED_FIELD_EX32(value, RX_DONE); 717 bus->regs[R_I2CD_INTR_STS] &= ~(value & 0x7FFF); 718 if (!bus->regs[R_I2CD_INTR_STS]) { 719 bus->controller->intr_status &= ~(1 << bus->id); 720 qemu_irq_lower(aic->bus_get_irq(bus)); 721 } 722 if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, 723 M_RX_CMD) || 724 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, 725 M_S_RX_CMD_LAST))) { 726 aspeed_i2c_handle_rx_cmd(bus); 727 aspeed_i2c_bus_raise_interrupt(bus); 728 } 729 break; 730 case A_I2CD_DEV_ADDR: 731 bus->regs[R_I2CD_DEV_ADDR] = value; 732 break; 733 case A_I2CD_POOL_CTRL: 734 bus->regs[R_I2CD_POOL_CTRL] &= ~0xffffff; 735 bus->regs[R_I2CD_POOL_CTRL] |= (value & 0xffffff); 736 break; 737 738 case A_I2CD_BYTE_BUF: 739 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_BYTE_BUF, TX_BUF, value); 740 break; 741 case A_I2CD_CMD: 742 if (!aspeed_i2c_bus_is_enabled(bus)) { 743 break; 744 } 745 746 if (!aspeed_i2c_bus_is_master(bus)) { 747 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 748 __func__); 749 break; 750 } 751 752 if (!aic->has_dma && 753 (SHARED_FIELD_EX32(value, RX_DMA_EN) || 754 SHARED_FIELD_EX32(value, TX_DMA_EN))) { 755 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 756 break; 757 } 758 759 bus->regs[R_I2CD_CMD] &= ~0xFFFF; 760 bus->regs[R_I2CD_CMD] |= value & 0xFFFF; 761 762 aspeed_i2c_bus_handle_cmd(bus, value); 763 aspeed_i2c_bus_raise_interrupt(bus); 764 break; 765 case A_I2CD_DMA_ADDR: 766 if (!aic->has_dma) { 767 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 768 break; 769 } 770 771 bus->regs[R_I2CD_DMA_ADDR] = value & 0x3ffffffc; 772 break; 773 774 case A_I2CD_DMA_LEN: 775 if (!aic->has_dma) { 776 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 777 break; 778 } 779 780 bus->regs[R_I2CD_DMA_LEN] = value & 0xfff; 781 if (!bus->regs[R_I2CD_DMA_LEN]) { 782 qemu_log_mask(LOG_UNIMP, "%s: invalid DMA length\n", __func__); 783 } 784 break; 785 786 default: 787 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 788 __func__, offset); 789 } 790 } 791 792 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, 793 uint64_t value, unsigned size) 794 { 795 AspeedI2CBus *bus = opaque; 796 if (aspeed_i2c_is_new_mode(bus->controller)) { 797 aspeed_i2c_bus_new_write(bus, offset, value, size); 798 } else { 799 aspeed_i2c_bus_old_write(bus, offset, value, size); 800 } 801 } 802 803 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, 804 unsigned size) 805 { 806 AspeedI2CState *s = opaque; 807 808 switch (offset) { 809 case A_I2C_CTRL_STATUS: 810 return s->intr_status; 811 case A_I2C_CTRL_GLOBAL: 812 return s->ctrl_global; 813 case A_I2C_CTRL_NEW_CLK_DIVIDER: 814 if (aspeed_i2c_is_new_mode(s)) { 815 return s->new_clk_divider; 816 } 817 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 818 __func__, offset); 819 break; 820 default: 821 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 822 __func__, offset); 823 break; 824 } 825 826 return -1; 827 } 828 829 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, 830 uint64_t value, unsigned size) 831 { 832 AspeedI2CState *s = opaque; 833 834 switch (offset) { 835 case A_I2C_CTRL_GLOBAL: 836 s->ctrl_global = value; 837 break; 838 case A_I2C_CTRL_NEW_CLK_DIVIDER: 839 if (aspeed_i2c_is_new_mode(s)) { 840 s->new_clk_divider = value; 841 } else { 842 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx 843 "\n", __func__, offset); 844 } 845 break; 846 case A_I2C_CTRL_STATUS: 847 default: 848 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 849 __func__, offset); 850 break; 851 } 852 } 853 854 static const MemoryRegionOps aspeed_i2c_bus_ops = { 855 .read = aspeed_i2c_bus_read, 856 .write = aspeed_i2c_bus_write, 857 .endianness = DEVICE_LITTLE_ENDIAN, 858 }; 859 860 static const MemoryRegionOps aspeed_i2c_ctrl_ops = { 861 .read = aspeed_i2c_ctrl_read, 862 .write = aspeed_i2c_ctrl_write, 863 .endianness = DEVICE_LITTLE_ENDIAN, 864 }; 865 866 static uint64_t aspeed_i2c_pool_read(void *opaque, hwaddr offset, 867 unsigned size) 868 { 869 AspeedI2CState *s = opaque; 870 uint64_t ret = 0; 871 int i; 872 873 for (i = 0; i < size; i++) { 874 ret |= (uint64_t) s->pool[offset + i] << (8 * i); 875 } 876 877 return ret; 878 } 879 880 static void aspeed_i2c_pool_write(void *opaque, hwaddr offset, 881 uint64_t value, unsigned size) 882 { 883 AspeedI2CState *s = opaque; 884 int i; 885 886 for (i = 0; i < size; i++) { 887 s->pool[offset + i] = (value >> (8 * i)) & 0xFF; 888 } 889 } 890 891 static const MemoryRegionOps aspeed_i2c_pool_ops = { 892 .read = aspeed_i2c_pool_read, 893 .write = aspeed_i2c_pool_write, 894 .endianness = DEVICE_LITTLE_ENDIAN, 895 .valid = { 896 .min_access_size = 1, 897 .max_access_size = 4, 898 }, 899 }; 900 901 static const VMStateDescription aspeed_i2c_bus_vmstate = { 902 .name = TYPE_ASPEED_I2C, 903 .version_id = 5, 904 .minimum_version_id = 5, 905 .fields = (VMStateField[]) { 906 VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus, ASPEED_I2C_NEW_NUM_REG), 907 VMSTATE_END_OF_LIST() 908 } 909 }; 910 911 static const VMStateDescription aspeed_i2c_vmstate = { 912 .name = TYPE_ASPEED_I2C, 913 .version_id = 2, 914 .minimum_version_id = 2, 915 .fields = (VMStateField[]) { 916 VMSTATE_UINT32(intr_status, AspeedI2CState), 917 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, 918 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, 919 AspeedI2CBus), 920 VMSTATE_UINT8_ARRAY(pool, AspeedI2CState, ASPEED_I2C_MAX_POOL_SIZE), 921 VMSTATE_END_OF_LIST() 922 } 923 }; 924 925 static void aspeed_i2c_reset(DeviceState *dev) 926 { 927 AspeedI2CState *s = ASPEED_I2C(dev); 928 929 s->intr_status = 0; 930 } 931 932 static void aspeed_i2c_instance_init(Object *obj) 933 { 934 AspeedI2CState *s = ASPEED_I2C(obj); 935 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 936 int i; 937 938 for (i = 0; i < aic->num_busses; i++) { 939 object_initialize_child(obj, "bus[*]", &s->busses[i], 940 TYPE_ASPEED_I2C_BUS); 941 } 942 } 943 944 /* 945 * Address Definitions (AST2400 and AST2500) 946 * 947 * 0x000 ... 0x03F: Global Register 948 * 0x040 ... 0x07F: Device 1 949 * 0x080 ... 0x0BF: Device 2 950 * 0x0C0 ... 0x0FF: Device 3 951 * 0x100 ... 0x13F: Device 4 952 * 0x140 ... 0x17F: Device 5 953 * 0x180 ... 0x1BF: Device 6 954 * 0x1C0 ... 0x1FF: Device 7 955 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver) 956 * 0x300 ... 0x33F: Device 8 957 * 0x340 ... 0x37F: Device 9 958 * 0x380 ... 0x3BF: Device 10 959 * 0x3C0 ... 0x3FF: Device 11 960 * 0x400 ... 0x43F: Device 12 961 * 0x440 ... 0x47F: Device 13 962 * 0x480 ... 0x4BF: Device 14 963 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver) 964 */ 965 static void aspeed_i2c_realize(DeviceState *dev, Error **errp) 966 { 967 int i; 968 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 969 AspeedI2CState *s = ASPEED_I2C(dev); 970 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 971 972 sysbus_init_irq(sbd, &s->irq); 973 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, 974 "aspeed.i2c", 0x1000); 975 sysbus_init_mmio(sbd, &s->iomem); 976 977 for (i = 0; i < aic->num_busses; i++) { 978 Object *bus = OBJECT(&s->busses[i]); 979 int offset = i < aic->gap ? 1 : 5; 980 981 if (!object_property_set_link(bus, "controller", OBJECT(s), errp)) { 982 return; 983 } 984 985 if (!object_property_set_uint(bus, "bus-id", i, errp)) { 986 return; 987 } 988 989 if (!sysbus_realize(SYS_BUS_DEVICE(bus), errp)) { 990 return; 991 } 992 993 memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), 994 &s->busses[i].mr); 995 } 996 997 memory_region_init_io(&s->pool_iomem, OBJECT(s), &aspeed_i2c_pool_ops, s, 998 "aspeed.i2c-pool", aic->pool_size); 999 memory_region_add_subregion(&s->iomem, aic->pool_base, &s->pool_iomem); 1000 1001 if (aic->has_dma) { 1002 if (!s->dram_mr) { 1003 error_setg(errp, TYPE_ASPEED_I2C ": 'dram' link not set"); 1004 return; 1005 } 1006 1007 address_space_init(&s->dram_as, s->dram_mr, 1008 TYPE_ASPEED_I2C "-dma-dram"); 1009 } 1010 } 1011 1012 static Property aspeed_i2c_properties[] = { 1013 DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, 1014 TYPE_MEMORY_REGION, MemoryRegion *), 1015 DEFINE_PROP_END_OF_LIST(), 1016 }; 1017 1018 static void aspeed_i2c_class_init(ObjectClass *klass, void *data) 1019 { 1020 DeviceClass *dc = DEVICE_CLASS(klass); 1021 1022 dc->vmsd = &aspeed_i2c_vmstate; 1023 dc->reset = aspeed_i2c_reset; 1024 device_class_set_props(dc, aspeed_i2c_properties); 1025 dc->realize = aspeed_i2c_realize; 1026 dc->desc = "Aspeed I2C Controller"; 1027 } 1028 1029 static const TypeInfo aspeed_i2c_info = { 1030 .name = TYPE_ASPEED_I2C, 1031 .parent = TYPE_SYS_BUS_DEVICE, 1032 .instance_init = aspeed_i2c_instance_init, 1033 .instance_size = sizeof(AspeedI2CState), 1034 .class_init = aspeed_i2c_class_init, 1035 .class_size = sizeof(AspeedI2CClass), 1036 .abstract = true, 1037 }; 1038 1039 static void aspeed_i2c_bus_reset(DeviceState *dev) 1040 { 1041 AspeedI2CBus *s = ASPEED_I2C_BUS(dev); 1042 1043 memset(s->regs, 0, sizeof(s->regs)); 1044 i2c_end_transfer(s->bus); 1045 } 1046 1047 static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp) 1048 { 1049 AspeedI2CBus *s = ASPEED_I2C_BUS(dev); 1050 AspeedI2CClass *aic; 1051 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id); 1052 1053 if (!s->controller) { 1054 error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set"); 1055 return; 1056 } 1057 1058 aic = ASPEED_I2C_GET_CLASS(s->controller); 1059 1060 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 1061 1062 s->bus = i2c_init_bus(dev, name); 1063 1064 memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops, 1065 s, name, aic->reg_size); 1066 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); 1067 } 1068 1069 static Property aspeed_i2c_bus_properties[] = { 1070 DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0), 1071 DEFINE_PROP_LINK("controller", AspeedI2CBus, controller, TYPE_ASPEED_I2C, 1072 AspeedI2CState *), 1073 DEFINE_PROP_END_OF_LIST(), 1074 }; 1075 1076 static void aspeed_i2c_bus_class_init(ObjectClass *klass, void *data) 1077 { 1078 DeviceClass *dc = DEVICE_CLASS(klass); 1079 1080 dc->desc = "Aspeed I2C Bus"; 1081 dc->realize = aspeed_i2c_bus_realize; 1082 dc->reset = aspeed_i2c_bus_reset; 1083 device_class_set_props(dc, aspeed_i2c_bus_properties); 1084 } 1085 1086 static const TypeInfo aspeed_i2c_bus_info = { 1087 .name = TYPE_ASPEED_I2C_BUS, 1088 .parent = TYPE_SYS_BUS_DEVICE, 1089 .instance_size = sizeof(AspeedI2CBus), 1090 .class_init = aspeed_i2c_bus_class_init, 1091 }; 1092 1093 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) 1094 { 1095 return bus->controller->irq; 1096 } 1097 1098 static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) 1099 { 1100 uint8_t *pool_page = 1101 &bus->controller->pool[ARRAY_FIELD_EX32(bus->regs, I2CD_FUN_CTRL, 1102 POOL_PAGE_SEL) * 0x100]; 1103 1104 return &pool_page[ARRAY_FIELD_EX32(bus->regs, I2CD_POOL_CTRL, OFFSET)]; 1105 } 1106 1107 static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) 1108 { 1109 DeviceClass *dc = DEVICE_CLASS(klass); 1110 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1111 1112 dc->desc = "ASPEED 2400 I2C Controller"; 1113 1114 aic->num_busses = 14; 1115 aic->reg_size = 0x40; 1116 aic->gap = 7; 1117 aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; 1118 aic->pool_size = 0x800; 1119 aic->pool_base = 0x800; 1120 aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; 1121 } 1122 1123 static const TypeInfo aspeed_2400_i2c_info = { 1124 .name = TYPE_ASPEED_2400_I2C, 1125 .parent = TYPE_ASPEED_I2C, 1126 .class_init = aspeed_2400_i2c_class_init, 1127 }; 1128 1129 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) 1130 { 1131 return bus->controller->irq; 1132 } 1133 1134 static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) 1135 { 1136 return &bus->controller->pool[bus->id * 0x10]; 1137 } 1138 1139 static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) 1140 { 1141 DeviceClass *dc = DEVICE_CLASS(klass); 1142 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1143 1144 dc->desc = "ASPEED 2500 I2C Controller"; 1145 1146 aic->num_busses = 14; 1147 aic->reg_size = 0x40; 1148 aic->gap = 7; 1149 aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; 1150 aic->pool_size = 0x100; 1151 aic->pool_base = 0x200; 1152 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 1153 aic->check_sram = true; 1154 aic->has_dma = true; 1155 } 1156 1157 static const TypeInfo aspeed_2500_i2c_info = { 1158 .name = TYPE_ASPEED_2500_I2C, 1159 .parent = TYPE_ASPEED_I2C, 1160 .class_init = aspeed_2500_i2c_class_init, 1161 }; 1162 1163 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) 1164 { 1165 return bus->irq; 1166 } 1167 1168 static uint8_t *aspeed_2600_i2c_bus_pool_base(AspeedI2CBus *bus) 1169 { 1170 return &bus->controller->pool[bus->id * 0x20]; 1171 } 1172 1173 static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) 1174 { 1175 DeviceClass *dc = DEVICE_CLASS(klass); 1176 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1177 1178 dc->desc = "ASPEED 2600 I2C Controller"; 1179 1180 aic->num_busses = 16; 1181 aic->reg_size = 0x80; 1182 aic->gap = -1; /* no gap */ 1183 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 1184 aic->pool_size = 0x200; 1185 aic->pool_base = 0xC00; 1186 aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; 1187 aic->has_dma = true; 1188 } 1189 1190 static const TypeInfo aspeed_2600_i2c_info = { 1191 .name = TYPE_ASPEED_2600_I2C, 1192 .parent = TYPE_ASPEED_I2C, 1193 .class_init = aspeed_2600_i2c_class_init, 1194 }; 1195 1196 static void aspeed_1030_i2c_class_init(ObjectClass *klass, void *data) 1197 { 1198 DeviceClass *dc = DEVICE_CLASS(klass); 1199 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1200 1201 dc->desc = "ASPEED 1030 I2C Controller"; 1202 1203 aic->num_busses = 14; 1204 aic->reg_size = 0x80; 1205 aic->gap = -1; /* no gap */ 1206 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 1207 aic->pool_size = 0x200; 1208 aic->pool_base = 0xC00; 1209 aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; 1210 aic->has_dma = true; 1211 } 1212 1213 static const TypeInfo aspeed_1030_i2c_info = { 1214 .name = TYPE_ASPEED_1030_I2C, 1215 .parent = TYPE_ASPEED_I2C, 1216 .class_init = aspeed_1030_i2c_class_init, 1217 }; 1218 1219 static void aspeed_i2c_register_types(void) 1220 { 1221 type_register_static(&aspeed_i2c_bus_info); 1222 type_register_static(&aspeed_i2c_info); 1223 type_register_static(&aspeed_2400_i2c_info); 1224 type_register_static(&aspeed_2500_i2c_info); 1225 type_register_static(&aspeed_2600_i2c_info); 1226 type_register_static(&aspeed_1030_i2c_info); 1227 } 1228 1229 type_init(aspeed_i2c_register_types) 1230 1231 1232 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr) 1233 { 1234 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 1235 I2CBus *bus = NULL; 1236 1237 if (busnr >= 0 && busnr < aic->num_busses) { 1238 bus = s->busses[busnr].bus; 1239 } 1240 1241 return bus; 1242 } 1243