1 /* 2 * ARM Aspeed I2C controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "qemu/cutils.h" 25 #include "qemu/log.h" 26 #include "qemu/module.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "hw/i2c/aspeed_i2c.h" 30 #include "hw/irq.h" 31 #include "hw/qdev-properties.h" 32 #include "hw/registerfields.h" 33 #include "trace.h" 34 35 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) 36 { 37 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 38 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 39 uint32_t intr_ctrl_reg = aspeed_i2c_bus_intr_ctrl_offset(bus); 40 bool raise_irq; 41 42 if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT)) { 43 g_autofree char *buf = g_strdup_printf("%s%s%s%s%s%s", 44 aspeed_i2c_bus_pkt_mode_en(bus) && 45 ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ? 46 "pktdone|" : "", 47 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_NAK) ? 48 "nak|" : "", 49 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_ACK) ? 50 "ack|" : "", 51 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE) ? 52 "done|" : "", 53 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, NORMAL_STOP) ? 54 "normal|" : "", 55 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, ABNORMAL) ? 56 "abnormal" : ""); 57 58 trace_aspeed_i2c_bus_raise_interrupt(bus->regs[reg_intr_sts], buf); 59 } 60 61 raise_irq = bus->regs[reg_intr_sts] & bus->regs[intr_ctrl_reg]; 62 63 /* In packet mode we don't mask off INTR_STS */ 64 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { 65 bus->regs[reg_intr_sts] &= bus->regs[intr_ctrl_reg]; 66 } 67 68 if (raise_irq) { 69 bus->controller->intr_status |= 1 << bus->id; 70 qemu_irq_raise(aic->bus_get_irq(bus)); 71 } 72 } 73 74 static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, 75 unsigned size) 76 { 77 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 78 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; 79 80 switch (offset) { 81 case A_I2CD_FUN_CTRL: 82 case A_I2CD_AC_TIMING1: 83 case A_I2CD_AC_TIMING2: 84 case A_I2CD_INTR_CTRL: 85 case A_I2CD_INTR_STS: 86 case A_I2CD_DEV_ADDR: 87 case A_I2CD_POOL_CTRL: 88 case A_I2CD_BYTE_BUF: 89 /* Value is already set, don't do anything. */ 90 break; 91 case A_I2CD_CMD: 92 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); 93 break; 94 case A_I2CD_DMA_ADDR: 95 if (!aic->has_dma) { 96 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 97 value = -1; 98 } 99 break; 100 case A_I2CD_DMA_LEN: 101 if (!aic->has_dma) { 102 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 103 value = -1; 104 } 105 break; 106 107 default: 108 qemu_log_mask(LOG_GUEST_ERROR, 109 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 110 value = -1; 111 break; 112 } 113 114 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); 115 return value; 116 } 117 118 static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, 119 unsigned size) 120 { 121 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; 122 123 switch (offset) { 124 case A_I2CC_FUN_CTRL: 125 case A_I2CC_AC_TIMING: 126 case A_I2CC_POOL_CTRL: 127 case A_I2CM_INTR_CTRL: 128 case A_I2CM_INTR_STS: 129 case A_I2CC_MS_TXRX_BYTE_BUF: 130 case A_I2CM_DMA_LEN: 131 case A_I2CM_DMA_TX_ADDR: 132 case A_I2CM_DMA_RX_ADDR: 133 case A_I2CM_DMA_LEN_STS: 134 case A_I2CC_DMA_ADDR: 135 case A_I2CC_DMA_LEN: 136 /* Value is already set, don't do anything. */ 137 break; 138 case A_I2CM_CMD: 139 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); 140 break; 141 default: 142 qemu_log_mask(LOG_GUEST_ERROR, 143 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 144 value = -1; 145 break; 146 } 147 148 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); 149 return value; 150 } 151 152 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, 153 unsigned size) 154 { 155 AspeedI2CBus *bus = opaque; 156 if (aspeed_i2c_is_new_mode(bus->controller)) { 157 return aspeed_i2c_bus_new_read(bus, offset, size); 158 } 159 return aspeed_i2c_bus_old_read(bus, offset, size); 160 } 161 162 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) 163 { 164 if (aspeed_i2c_is_new_mode(bus->controller)) { 165 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_STATE, 166 state); 167 } else { 168 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_CMD, TX_STATE, state); 169 } 170 } 171 172 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) 173 { 174 if (aspeed_i2c_is_new_mode(bus->controller)) { 175 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, 176 TX_STATE); 177 } 178 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, TX_STATE); 179 } 180 181 static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data) 182 { 183 MemTxResult result; 184 AspeedI2CState *s = bus->controller; 185 uint32_t reg_dma_addr = aspeed_i2c_bus_dma_addr_offset(bus); 186 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 187 188 result = address_space_read(&s->dram_as, bus->regs[reg_dma_addr], 189 MEMTXATTRS_UNSPECIFIED, data, 1); 190 if (result != MEMTX_OK) { 191 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n", 192 __func__, bus->regs[reg_dma_addr]); 193 return -1; 194 } 195 196 bus->regs[reg_dma_addr]++; 197 bus->regs[reg_dma_len]--; 198 return 0; 199 } 200 201 static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) 202 { 203 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 204 int ret = -1; 205 int i; 206 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 207 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 208 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 209 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 210 int pool_tx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, 211 TX_COUNT); 212 213 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 214 for (i = pool_start; i < pool_tx_count; i++) { 215 uint8_t *pool_base = aic->bus_pool_base(bus); 216 217 trace_aspeed_i2c_bus_send("BUF", i + 1, pool_tx_count, 218 pool_base[i]); 219 ret = i2c_send(bus->bus, pool_base[i]); 220 if (ret) { 221 break; 222 } 223 } 224 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_BUFF_EN, 0); 225 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 226 /* In new mode, clear how many bytes we TXed */ 227 if (aspeed_i2c_is_new_mode(bus->controller)) { 228 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); 229 } 230 while (bus->regs[reg_dma_len]) { 231 uint8_t data; 232 aspeed_i2c_dma_read(bus, &data); 233 trace_aspeed_i2c_bus_send("DMA", bus->regs[reg_dma_len], 234 bus->regs[reg_dma_len], data); 235 ret = i2c_send(bus->bus, data); 236 if (ret) { 237 break; 238 } 239 /* In new mode, keep track of how many bytes we TXed */ 240 if (aspeed_i2c_is_new_mode(bus->controller)) { 241 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 242 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, 243 TX_LEN) + 1); 244 } 245 } 246 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); 247 } else { 248 trace_aspeed_i2c_bus_send("BYTE", pool_start, 1, 249 bus->regs[reg_byte_buf]); 250 ret = i2c_send(bus->bus, bus->regs[reg_byte_buf]); 251 } 252 253 return ret; 254 } 255 256 static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) 257 { 258 AspeedI2CState *s = bus->controller; 259 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 260 uint8_t data; 261 int i; 262 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 263 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 264 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 265 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 266 uint32_t reg_dma_addr = aspeed_i2c_bus_dma_addr_offset(bus); 267 int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, 268 RX_COUNT); 269 270 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { 271 uint8_t *pool_base = aic->bus_pool_base(bus); 272 273 for (i = 0; i < pool_rx_count; i++) { 274 pool_base[i] = i2c_recv(bus->bus); 275 trace_aspeed_i2c_bus_recv("BUF", i + 1, pool_rx_count, 276 pool_base[i]); 277 } 278 279 /* Update RX count */ 280 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_pool_ctrl, RX_COUNT, i & 0xff); 281 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_BUFF_EN, 0); 282 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { 283 uint8_t data; 284 /* In new mode, clear how many bytes we RXed */ 285 if (aspeed_i2c_is_new_mode(bus->controller)) { 286 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); 287 } 288 289 while (bus->regs[reg_dma_len]) { 290 MemTxResult result; 291 292 data = i2c_recv(bus->bus); 293 trace_aspeed_i2c_bus_recv("DMA", bus->regs[reg_dma_len], 294 bus->regs[reg_dma_len], data); 295 result = address_space_write(&s->dram_as, bus->regs[reg_dma_addr], 296 MEMTXATTRS_UNSPECIFIED, &data, 1); 297 if (result != MEMTX_OK) { 298 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n", 299 __func__, bus->regs[reg_dma_addr]); 300 return; 301 } 302 bus->regs[reg_dma_addr]++; 303 bus->regs[reg_dma_len]--; 304 /* In new mode, keep track of how many bytes we RXed */ 305 if (aspeed_i2c_is_new_mode(bus->controller)) { 306 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 307 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, 308 RX_LEN) + 1); 309 } 310 } 311 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_DMA_EN, 0); 312 } else { 313 data = i2c_recv(bus->bus); 314 trace_aspeed_i2c_bus_recv("BYTE", 1, 1, bus->regs[reg_byte_buf]); 315 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); 316 } 317 } 318 319 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) 320 { 321 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 322 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 323 324 aspeed_i2c_set_state(bus, I2CD_MRXD); 325 aspeed_i2c_bus_recv(bus); 326 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); 327 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) { 328 i2c_nack(bus->bus); 329 } 330 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_RX_CMD, 0); 331 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_S_RX_CMD_LAST, 0); 332 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 333 } 334 335 static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) 336 { 337 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 338 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 339 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 340 341 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 342 return (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_DEV_ADDR) << 1) | 343 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD); 344 } 345 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 346 uint8_t *pool_base = aic->bus_pool_base(bus); 347 348 return pool_base[0]; 349 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 350 uint8_t data; 351 352 aspeed_i2c_dma_read(bus, &data); 353 return data; 354 } else { 355 return bus->regs[reg_byte_buf]; 356 } 357 } 358 359 static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) 360 { 361 AspeedI2CState *s = bus->controller; 362 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 363 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 364 bool dma_en = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) || 365 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) || 366 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) || 367 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN); 368 if (!aic->check_sram) { 369 return true; 370 } 371 372 /* 373 * AST2500: SRAM must be enabled before using the Buffer Pool or 374 * DMA mode. 375 */ 376 if (!FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, SRAM_EN) && dma_en) { 377 qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__); 378 return false; 379 } 380 381 return true; 382 } 383 384 static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) 385 { 386 g_autofree char *cmd_flags = NULL; 387 uint32_t count; 388 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 389 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 390 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 391 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 392 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { 393 count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT); 394 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { 395 count = bus->regs[reg_dma_len]; 396 } else { /* BYTE mode */ 397 count = 1; 398 } 399 400 cmd_flags = g_strdup_printf("%s%s%s%s%s%s%s%s%s", 401 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD) ? "start|" : "", 402 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) ? "rxdma|" : "", 403 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) ? "txdma|" : "", 404 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) ? "rxbuf|" : "", 405 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN) ? "txbuf|" : "", 406 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD) ? "tx|" : "", 407 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) ? "rx|" : "", 408 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST) ? "last|" : "", 409 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD) ? "stop|" : ""); 410 411 trace_aspeed_i2c_bus_cmd(bus->regs[reg_cmd], cmd_flags, count, 412 bus->regs[reg_intr_sts]); 413 } 414 415 /* 416 * The state machine needs some refinement. It is only used to track 417 * invalid STOP commands for the moment. 418 */ 419 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 420 { 421 uint8_t pool_start = 0; 422 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 423 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 424 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 425 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 426 427 if (!aspeed_i2c_check_sram(bus)) { 428 return; 429 } 430 431 if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_CMD)) { 432 aspeed_i2c_bus_cmd_dump(bus); 433 } 434 435 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD)) { 436 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? 437 I2CD_MSTARTR : I2CD_MSTART; 438 uint8_t addr; 439 440 aspeed_i2c_set_state(bus, state); 441 442 addr = aspeed_i2c_get_addr(bus); 443 if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), 444 extract32(addr, 0, 1))) { 445 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); 446 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 447 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 448 } 449 } else { 450 /* START doesn't set TX_ACK in packet mode */ 451 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { 452 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); 453 } 454 } 455 456 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_START_CMD, 0); 457 458 /* 459 * The START command is also a TX command, as the slave 460 * address is sent on the bus. Drop the TX flag if nothing 461 * else needs to be sent in this sequence. 462 */ 463 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 464 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) 465 == 1) { 466 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 467 } else { 468 /* 469 * Increase the start index in the TX pool buffer to 470 * skip the address byte. 471 */ 472 pool_start++; 473 } 474 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 475 if (bus->regs[reg_dma_len] == 0) { 476 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 477 } 478 } else { 479 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 480 } 481 482 /* No slave found */ 483 if (!i2c_bus_busy(bus->bus)) { 484 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 485 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 486 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); 487 } 488 return; 489 } 490 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 491 } 492 493 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD)) { 494 aspeed_i2c_set_state(bus, I2CD_MTXD); 495 if (aspeed_i2c_bus_send(bus, pool_start)) { 496 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); 497 i2c_end_transfer(bus->bus); 498 } else { 499 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); 500 } 501 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 502 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 503 } 504 505 if ((SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) || 506 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) && 507 !SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE)) { 508 aspeed_i2c_handle_rx_cmd(bus); 509 } 510 511 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD)) { 512 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { 513 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); 514 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, ABNORMAL, 1); 515 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 516 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 517 } 518 } else { 519 aspeed_i2c_set_state(bus, I2CD_MSTOP); 520 i2c_end_transfer(bus->bus); 521 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); 522 } 523 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0); 524 aspeed_i2c_set_state(bus, I2CD_IDLE); 525 } 526 527 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 528 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); 529 } 530 } 531 532 static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset, 533 uint64_t value, unsigned size) 534 { 535 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 536 bool handle_rx; 537 bool w1t; 538 539 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); 540 541 switch (offset) { 542 case A_I2CC_FUN_CTRL: 543 if (SHARED_FIELD_EX32(value, SLAVE_EN)) { 544 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 545 __func__); 546 break; 547 } 548 bus->regs[R_I2CD_FUN_CTRL] = value & 0x007dc3ff; 549 break; 550 case A_I2CC_AC_TIMING: 551 bus->regs[R_I2CC_AC_TIMING] = value & 0x1ffff0ff; 552 break; 553 case A_I2CC_MS_TXRX_BYTE_BUF: 554 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_BUF, 555 value); 556 break; 557 case A_I2CC_POOL_CTRL: 558 bus->regs[R_I2CC_POOL_CTRL] &= ~0xffffff; 559 bus->regs[R_I2CC_POOL_CTRL] |= (value & 0xffffff); 560 break; 561 case A_I2CM_INTR_CTRL: 562 bus->regs[R_I2CM_INTR_CTRL] = value & 0x0007f07f; 563 break; 564 case A_I2CM_INTR_STS: 565 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_INTR_STS, RX_DONE) 566 && SHARED_FIELD_EX32(value, RX_DONE); 567 568 /* In packet mode, clearing PKT_CMD_DONE clears other interrupts. */ 569 if (aspeed_i2c_bus_pkt_mode_en(bus) && 570 FIELD_EX32(value, I2CM_INTR_STS, PKT_CMD_DONE)) { 571 bus->regs[R_I2CM_INTR_STS] &= 0xf0001000; 572 if (!bus->regs[R_I2CM_INTR_STS]) { 573 bus->controller->intr_status &= ~(1 << bus->id); 574 qemu_irq_lower(aic->bus_get_irq(bus)); 575 } 576 break; 577 } 578 bus->regs[R_I2CM_INTR_STS] &= ~(value & 0xf007f07f); 579 if (!bus->regs[R_I2CM_INTR_STS]) { 580 bus->controller->intr_status &= ~(1 << bus->id); 581 qemu_irq_lower(aic->bus_get_irq(bus)); 582 } 583 if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, 584 M_RX_CMD) || 585 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, 586 M_S_RX_CMD_LAST))) { 587 aspeed_i2c_handle_rx_cmd(bus); 588 aspeed_i2c_bus_raise_interrupt(bus); 589 } 590 break; 591 case A_I2CM_CMD: 592 if (!aspeed_i2c_bus_is_enabled(bus)) { 593 break; 594 } 595 596 if (!aspeed_i2c_bus_is_master(bus)) { 597 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 598 __func__); 599 break; 600 } 601 602 if (!aic->has_dma && 603 (SHARED_FIELD_EX32(value, RX_DMA_EN) || 604 SHARED_FIELD_EX32(value, TX_DMA_EN))) { 605 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 606 break; 607 } 608 609 if (bus->regs[R_I2CM_INTR_STS] & 0xffff0000) { 610 qemu_log_mask(LOG_UNIMP, "%s: Packet mode is not implemented\n", 611 __func__); 612 break; 613 } 614 615 value &= 0xff0ffbfb; 616 if (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, W1_CTRL)) { 617 bus->regs[R_I2CM_CMD] |= value; 618 } else { 619 bus->regs[R_I2CM_CMD] = value; 620 } 621 622 aspeed_i2c_bus_handle_cmd(bus, value); 623 aspeed_i2c_bus_raise_interrupt(bus); 624 break; 625 case A_I2CM_DMA_TX_ADDR: 626 bus->regs[R_I2CM_DMA_TX_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR, 627 ADDR); 628 bus->regs[R_I2CC_DMA_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR); 629 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, 630 TX_BUF_LEN) + 1; 631 break; 632 case A_I2CM_DMA_RX_ADDR: 633 bus->regs[R_I2CM_DMA_RX_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR, 634 ADDR); 635 bus->regs[R_I2CC_DMA_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR); 636 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, 637 RX_BUF_LEN) + 1; 638 break; 639 case A_I2CM_DMA_LEN: 640 w1t = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T) || 641 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T); 642 /* If none of the w1t bits are set, just write to the reg as normal. */ 643 if (!w1t) { 644 bus->regs[R_I2CM_DMA_LEN] = value; 645 break; 646 } 647 if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) { 648 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN, 649 FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN)); 650 } 651 if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) { 652 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN, 653 FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN)); 654 } 655 break; 656 case A_I2CM_DMA_LEN_STS: 657 /* Writes clear to 0 */ 658 bus->regs[R_I2CM_DMA_LEN_STS] = 0; 659 break; 660 case A_I2CC_DMA_ADDR: 661 case A_I2CC_DMA_LEN: 662 /* RO */ 663 break; 664 case A_I2CS_DMA_LEN_STS: 665 case A_I2CS_DMA_TX_ADDR: 666 case A_I2CS_DMA_RX_ADDR: 667 case A_I2CS_DEV_ADDR: 668 case A_I2CS_INTR_CTRL: 669 case A_I2CS_INTR_STS: 670 case A_I2CS_CMD: 671 case A_I2CS_DMA_LEN: 672 qemu_log_mask(LOG_UNIMP, "%s: Slave mode is not implemented\n", 673 __func__); 674 break; 675 default: 676 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 677 __func__, offset); 678 } 679 } 680 681 static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset, 682 uint64_t value, unsigned size) 683 { 684 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 685 bool handle_rx; 686 687 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); 688 689 switch (offset) { 690 case A_I2CD_FUN_CTRL: 691 if (SHARED_FIELD_EX32(value, SLAVE_EN)) { 692 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 693 __func__); 694 break; 695 } 696 bus->regs[R_I2CD_FUN_CTRL] = value & 0x0071C3FF; 697 break; 698 case A_I2CD_AC_TIMING1: 699 bus->regs[R_I2CD_AC_TIMING1] = value & 0xFFFFF0F; 700 break; 701 case A_I2CD_AC_TIMING2: 702 bus->regs[R_I2CD_AC_TIMING2] = value & 0x7; 703 break; 704 case A_I2CD_INTR_CTRL: 705 bus->regs[R_I2CD_INTR_CTRL] = value & 0x7FFF; 706 break; 707 case A_I2CD_INTR_STS: 708 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_INTR_STS, RX_DONE) 709 && SHARED_FIELD_EX32(value, RX_DONE); 710 bus->regs[R_I2CD_INTR_STS] &= ~(value & 0x7FFF); 711 if (!bus->regs[R_I2CD_INTR_STS]) { 712 bus->controller->intr_status &= ~(1 << bus->id); 713 qemu_irq_lower(aic->bus_get_irq(bus)); 714 } 715 if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, 716 M_RX_CMD) || 717 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, 718 M_S_RX_CMD_LAST))) { 719 aspeed_i2c_handle_rx_cmd(bus); 720 aspeed_i2c_bus_raise_interrupt(bus); 721 } 722 break; 723 case A_I2CD_DEV_ADDR: 724 bus->regs[R_I2CD_DEV_ADDR] = value; 725 break; 726 case A_I2CD_POOL_CTRL: 727 bus->regs[R_I2CD_POOL_CTRL] &= ~0xffffff; 728 bus->regs[R_I2CD_POOL_CTRL] |= (value & 0xffffff); 729 break; 730 731 case A_I2CD_BYTE_BUF: 732 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_BYTE_BUF, TX_BUF, value); 733 break; 734 case A_I2CD_CMD: 735 if (!aspeed_i2c_bus_is_enabled(bus)) { 736 break; 737 } 738 739 if (!aspeed_i2c_bus_is_master(bus)) { 740 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 741 __func__); 742 break; 743 } 744 745 if (!aic->has_dma && 746 (SHARED_FIELD_EX32(value, RX_DMA_EN) || 747 SHARED_FIELD_EX32(value, TX_DMA_EN))) { 748 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 749 break; 750 } 751 752 bus->regs[R_I2CD_CMD] &= ~0xFFFF; 753 bus->regs[R_I2CD_CMD] |= value & 0xFFFF; 754 755 aspeed_i2c_bus_handle_cmd(bus, value); 756 aspeed_i2c_bus_raise_interrupt(bus); 757 break; 758 case A_I2CD_DMA_ADDR: 759 if (!aic->has_dma) { 760 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 761 break; 762 } 763 764 bus->regs[R_I2CD_DMA_ADDR] = value & 0x3ffffffc; 765 break; 766 767 case A_I2CD_DMA_LEN: 768 if (!aic->has_dma) { 769 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 770 break; 771 } 772 773 bus->regs[R_I2CD_DMA_LEN] = value & 0xfff; 774 if (!bus->regs[R_I2CD_DMA_LEN]) { 775 qemu_log_mask(LOG_UNIMP, "%s: invalid DMA length\n", __func__); 776 } 777 break; 778 779 default: 780 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 781 __func__, offset); 782 } 783 } 784 785 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, 786 uint64_t value, unsigned size) 787 { 788 AspeedI2CBus *bus = opaque; 789 if (aspeed_i2c_is_new_mode(bus->controller)) { 790 aspeed_i2c_bus_new_write(bus, offset, value, size); 791 } else { 792 aspeed_i2c_bus_old_write(bus, offset, value, size); 793 } 794 } 795 796 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, 797 unsigned size) 798 { 799 AspeedI2CState *s = opaque; 800 801 switch (offset) { 802 case A_I2C_CTRL_STATUS: 803 return s->intr_status; 804 case A_I2C_CTRL_GLOBAL: 805 return s->ctrl_global; 806 case A_I2C_CTRL_NEW_CLK_DIVIDER: 807 if (aspeed_i2c_is_new_mode(s)) { 808 return s->new_clk_divider; 809 } 810 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 811 __func__, offset); 812 break; 813 default: 814 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 815 __func__, offset); 816 break; 817 } 818 819 return -1; 820 } 821 822 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, 823 uint64_t value, unsigned size) 824 { 825 AspeedI2CState *s = opaque; 826 827 switch (offset) { 828 case A_I2C_CTRL_GLOBAL: 829 s->ctrl_global = value; 830 break; 831 case A_I2C_CTRL_NEW_CLK_DIVIDER: 832 if (aspeed_i2c_is_new_mode(s)) { 833 s->new_clk_divider = value; 834 } else { 835 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx 836 "\n", __func__, offset); 837 } 838 break; 839 case A_I2C_CTRL_STATUS: 840 default: 841 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 842 __func__, offset); 843 break; 844 } 845 } 846 847 static const MemoryRegionOps aspeed_i2c_bus_ops = { 848 .read = aspeed_i2c_bus_read, 849 .write = aspeed_i2c_bus_write, 850 .endianness = DEVICE_LITTLE_ENDIAN, 851 }; 852 853 static const MemoryRegionOps aspeed_i2c_ctrl_ops = { 854 .read = aspeed_i2c_ctrl_read, 855 .write = aspeed_i2c_ctrl_write, 856 .endianness = DEVICE_LITTLE_ENDIAN, 857 }; 858 859 static uint64_t aspeed_i2c_pool_read(void *opaque, hwaddr offset, 860 unsigned size) 861 { 862 AspeedI2CState *s = opaque; 863 uint64_t ret = 0; 864 int i; 865 866 for (i = 0; i < size; i++) { 867 ret |= (uint64_t) s->pool[offset + i] << (8 * i); 868 } 869 870 return ret; 871 } 872 873 static void aspeed_i2c_pool_write(void *opaque, hwaddr offset, 874 uint64_t value, unsigned size) 875 { 876 AspeedI2CState *s = opaque; 877 int i; 878 879 for (i = 0; i < size; i++) { 880 s->pool[offset + i] = (value >> (8 * i)) & 0xFF; 881 } 882 } 883 884 static const MemoryRegionOps aspeed_i2c_pool_ops = { 885 .read = aspeed_i2c_pool_read, 886 .write = aspeed_i2c_pool_write, 887 .endianness = DEVICE_LITTLE_ENDIAN, 888 .valid = { 889 .min_access_size = 1, 890 .max_access_size = 4, 891 }, 892 }; 893 894 static const VMStateDescription aspeed_i2c_bus_vmstate = { 895 .name = TYPE_ASPEED_I2C, 896 .version_id = 5, 897 .minimum_version_id = 5, 898 .fields = (VMStateField[]) { 899 VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus, ASPEED_I2C_NEW_NUM_REG), 900 VMSTATE_END_OF_LIST() 901 } 902 }; 903 904 static const VMStateDescription aspeed_i2c_vmstate = { 905 .name = TYPE_ASPEED_I2C, 906 .version_id = 2, 907 .minimum_version_id = 2, 908 .fields = (VMStateField[]) { 909 VMSTATE_UINT32(intr_status, AspeedI2CState), 910 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, 911 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, 912 AspeedI2CBus), 913 VMSTATE_UINT8_ARRAY(pool, AspeedI2CState, ASPEED_I2C_MAX_POOL_SIZE), 914 VMSTATE_END_OF_LIST() 915 } 916 }; 917 918 static void aspeed_i2c_reset(DeviceState *dev) 919 { 920 AspeedI2CState *s = ASPEED_I2C(dev); 921 922 s->intr_status = 0; 923 } 924 925 static void aspeed_i2c_instance_init(Object *obj) 926 { 927 AspeedI2CState *s = ASPEED_I2C(obj); 928 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 929 int i; 930 931 for (i = 0; i < aic->num_busses; i++) { 932 object_initialize_child(obj, "bus[*]", &s->busses[i], 933 TYPE_ASPEED_I2C_BUS); 934 } 935 } 936 937 /* 938 * Address Definitions (AST2400 and AST2500) 939 * 940 * 0x000 ... 0x03F: Global Register 941 * 0x040 ... 0x07F: Device 1 942 * 0x080 ... 0x0BF: Device 2 943 * 0x0C0 ... 0x0FF: Device 3 944 * 0x100 ... 0x13F: Device 4 945 * 0x140 ... 0x17F: Device 5 946 * 0x180 ... 0x1BF: Device 6 947 * 0x1C0 ... 0x1FF: Device 7 948 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver) 949 * 0x300 ... 0x33F: Device 8 950 * 0x340 ... 0x37F: Device 9 951 * 0x380 ... 0x3BF: Device 10 952 * 0x3C0 ... 0x3FF: Device 11 953 * 0x400 ... 0x43F: Device 12 954 * 0x440 ... 0x47F: Device 13 955 * 0x480 ... 0x4BF: Device 14 956 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver) 957 */ 958 static void aspeed_i2c_realize(DeviceState *dev, Error **errp) 959 { 960 int i; 961 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 962 AspeedI2CState *s = ASPEED_I2C(dev); 963 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 964 965 sysbus_init_irq(sbd, &s->irq); 966 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, 967 "aspeed.i2c", 0x1000); 968 sysbus_init_mmio(sbd, &s->iomem); 969 970 for (i = 0; i < aic->num_busses; i++) { 971 Object *bus = OBJECT(&s->busses[i]); 972 int offset = i < aic->gap ? 1 : 5; 973 974 if (!object_property_set_link(bus, "controller", OBJECT(s), errp)) { 975 return; 976 } 977 978 if (!object_property_set_uint(bus, "bus-id", i, errp)) { 979 return; 980 } 981 982 if (!sysbus_realize(SYS_BUS_DEVICE(bus), errp)) { 983 return; 984 } 985 986 memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), 987 &s->busses[i].mr); 988 } 989 990 memory_region_init_io(&s->pool_iomem, OBJECT(s), &aspeed_i2c_pool_ops, s, 991 "aspeed.i2c-pool", aic->pool_size); 992 memory_region_add_subregion(&s->iomem, aic->pool_base, &s->pool_iomem); 993 994 if (aic->has_dma) { 995 if (!s->dram_mr) { 996 error_setg(errp, TYPE_ASPEED_I2C ": 'dram' link not set"); 997 return; 998 } 999 1000 address_space_init(&s->dram_as, s->dram_mr, 1001 TYPE_ASPEED_I2C "-dma-dram"); 1002 } 1003 } 1004 1005 static Property aspeed_i2c_properties[] = { 1006 DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, 1007 TYPE_MEMORY_REGION, MemoryRegion *), 1008 DEFINE_PROP_END_OF_LIST(), 1009 }; 1010 1011 static void aspeed_i2c_class_init(ObjectClass *klass, void *data) 1012 { 1013 DeviceClass *dc = DEVICE_CLASS(klass); 1014 1015 dc->vmsd = &aspeed_i2c_vmstate; 1016 dc->reset = aspeed_i2c_reset; 1017 device_class_set_props(dc, aspeed_i2c_properties); 1018 dc->realize = aspeed_i2c_realize; 1019 dc->desc = "Aspeed I2C Controller"; 1020 } 1021 1022 static const TypeInfo aspeed_i2c_info = { 1023 .name = TYPE_ASPEED_I2C, 1024 .parent = TYPE_SYS_BUS_DEVICE, 1025 .instance_init = aspeed_i2c_instance_init, 1026 .instance_size = sizeof(AspeedI2CState), 1027 .class_init = aspeed_i2c_class_init, 1028 .class_size = sizeof(AspeedI2CClass), 1029 .abstract = true, 1030 }; 1031 1032 static void aspeed_i2c_bus_reset(DeviceState *dev) 1033 { 1034 AspeedI2CBus *s = ASPEED_I2C_BUS(dev); 1035 1036 memset(s->regs, 0, sizeof(s->regs)); 1037 i2c_end_transfer(s->bus); 1038 } 1039 1040 static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp) 1041 { 1042 AspeedI2CBus *s = ASPEED_I2C_BUS(dev); 1043 AspeedI2CClass *aic; 1044 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id); 1045 1046 if (!s->controller) { 1047 error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set"); 1048 return; 1049 } 1050 1051 aic = ASPEED_I2C_GET_CLASS(s->controller); 1052 1053 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 1054 1055 s->bus = i2c_init_bus(dev, name); 1056 1057 memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops, 1058 s, name, aic->reg_size); 1059 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); 1060 } 1061 1062 static Property aspeed_i2c_bus_properties[] = { 1063 DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0), 1064 DEFINE_PROP_LINK("controller", AspeedI2CBus, controller, TYPE_ASPEED_I2C, 1065 AspeedI2CState *), 1066 DEFINE_PROP_END_OF_LIST(), 1067 }; 1068 1069 static void aspeed_i2c_bus_class_init(ObjectClass *klass, void *data) 1070 { 1071 DeviceClass *dc = DEVICE_CLASS(klass); 1072 1073 dc->desc = "Aspeed I2C Bus"; 1074 dc->realize = aspeed_i2c_bus_realize; 1075 dc->reset = aspeed_i2c_bus_reset; 1076 device_class_set_props(dc, aspeed_i2c_bus_properties); 1077 } 1078 1079 static const TypeInfo aspeed_i2c_bus_info = { 1080 .name = TYPE_ASPEED_I2C_BUS, 1081 .parent = TYPE_SYS_BUS_DEVICE, 1082 .instance_size = sizeof(AspeedI2CBus), 1083 .class_init = aspeed_i2c_bus_class_init, 1084 }; 1085 1086 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) 1087 { 1088 return bus->controller->irq; 1089 } 1090 1091 static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) 1092 { 1093 uint8_t *pool_page = 1094 &bus->controller->pool[ARRAY_FIELD_EX32(bus->regs, I2CD_FUN_CTRL, 1095 POOL_PAGE_SEL) * 0x100]; 1096 1097 return &pool_page[ARRAY_FIELD_EX32(bus->regs, I2CD_POOL_CTRL, OFFSET)]; 1098 } 1099 1100 static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) 1101 { 1102 DeviceClass *dc = DEVICE_CLASS(klass); 1103 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1104 1105 dc->desc = "ASPEED 2400 I2C Controller"; 1106 1107 aic->num_busses = 14; 1108 aic->reg_size = 0x40; 1109 aic->gap = 7; 1110 aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; 1111 aic->pool_size = 0x800; 1112 aic->pool_base = 0x800; 1113 aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; 1114 } 1115 1116 static const TypeInfo aspeed_2400_i2c_info = { 1117 .name = TYPE_ASPEED_2400_I2C, 1118 .parent = TYPE_ASPEED_I2C, 1119 .class_init = aspeed_2400_i2c_class_init, 1120 }; 1121 1122 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) 1123 { 1124 return bus->controller->irq; 1125 } 1126 1127 static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) 1128 { 1129 return &bus->controller->pool[bus->id * 0x10]; 1130 } 1131 1132 static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) 1133 { 1134 DeviceClass *dc = DEVICE_CLASS(klass); 1135 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1136 1137 dc->desc = "ASPEED 2500 I2C Controller"; 1138 1139 aic->num_busses = 14; 1140 aic->reg_size = 0x40; 1141 aic->gap = 7; 1142 aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; 1143 aic->pool_size = 0x100; 1144 aic->pool_base = 0x200; 1145 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 1146 aic->check_sram = true; 1147 aic->has_dma = true; 1148 } 1149 1150 static const TypeInfo aspeed_2500_i2c_info = { 1151 .name = TYPE_ASPEED_2500_I2C, 1152 .parent = TYPE_ASPEED_I2C, 1153 .class_init = aspeed_2500_i2c_class_init, 1154 }; 1155 1156 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) 1157 { 1158 return bus->irq; 1159 } 1160 1161 static uint8_t *aspeed_2600_i2c_bus_pool_base(AspeedI2CBus *bus) 1162 { 1163 return &bus->controller->pool[bus->id * 0x20]; 1164 } 1165 1166 static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) 1167 { 1168 DeviceClass *dc = DEVICE_CLASS(klass); 1169 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1170 1171 dc->desc = "ASPEED 2600 I2C Controller"; 1172 1173 aic->num_busses = 16; 1174 aic->reg_size = 0x80; 1175 aic->gap = -1; /* no gap */ 1176 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 1177 aic->pool_size = 0x200; 1178 aic->pool_base = 0xC00; 1179 aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; 1180 aic->has_dma = true; 1181 } 1182 1183 static const TypeInfo aspeed_2600_i2c_info = { 1184 .name = TYPE_ASPEED_2600_I2C, 1185 .parent = TYPE_ASPEED_I2C, 1186 .class_init = aspeed_2600_i2c_class_init, 1187 }; 1188 1189 static void aspeed_1030_i2c_class_init(ObjectClass *klass, void *data) 1190 { 1191 DeviceClass *dc = DEVICE_CLASS(klass); 1192 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1193 1194 dc->desc = "ASPEED 1030 I2C Controller"; 1195 1196 aic->num_busses = 14; 1197 aic->reg_size = 0x80; 1198 aic->gap = -1; /* no gap */ 1199 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 1200 aic->pool_size = 0x200; 1201 aic->pool_base = 0xC00; 1202 aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; 1203 aic->has_dma = true; 1204 } 1205 1206 static const TypeInfo aspeed_1030_i2c_info = { 1207 .name = TYPE_ASPEED_1030_I2C, 1208 .parent = TYPE_ASPEED_I2C, 1209 .class_init = aspeed_1030_i2c_class_init, 1210 }; 1211 1212 static void aspeed_i2c_register_types(void) 1213 { 1214 type_register_static(&aspeed_i2c_bus_info); 1215 type_register_static(&aspeed_i2c_info); 1216 type_register_static(&aspeed_2400_i2c_info); 1217 type_register_static(&aspeed_2500_i2c_info); 1218 type_register_static(&aspeed_2600_i2c_info); 1219 type_register_static(&aspeed_1030_i2c_info); 1220 } 1221 1222 type_init(aspeed_i2c_register_types) 1223 1224 1225 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr) 1226 { 1227 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 1228 I2CBus *bus = NULL; 1229 1230 if (busnr >= 0 && busnr < aic->num_busses) { 1231 bus = s->busses[busnr].bus; 1232 } 1233 1234 return bus; 1235 } 1236