1 /* 2 * ARM Aspeed I2C controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "hw/i2c/aspeed_i2c.h" 27 #include "hw/irq.h" 28 29 /* I2C Global Register */ 30 31 #define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */ 32 #define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target 33 Assignment */ 34 #define I2C_CTRL_GLOBAL 0x0C /* Global Control Register */ 35 #define I2C_CTRL_SRAM_EN BIT(0) 36 37 /* I2C Device (Bus) Register */ 38 39 #define I2CD_FUN_CTRL_REG 0x00 /* I2CD Function Control */ 40 #define I2CD_POOL_PAGE_SEL(x) (((x) >> 20) & 0x7) /* AST2400 */ 41 #define I2CD_M_SDA_LOCK_EN (0x1 << 16) 42 #define I2CD_MULTI_MASTER_DIS (0x1 << 15) 43 #define I2CD_M_SCL_DRIVE_EN (0x1 << 14) 44 #define I2CD_MSB_STS (0x1 << 9) 45 #define I2CD_SDA_DRIVE_1T_EN (0x1 << 8) 46 #define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) 47 #define I2CD_M_HIGH_SPEED_EN (0x1 << 6) 48 #define I2CD_DEF_ADDR_EN (0x1 << 5) 49 #define I2CD_DEF_ALERT_EN (0x1 << 4) 50 #define I2CD_DEF_ARP_EN (0x1 << 3) 51 #define I2CD_DEF_GCALL_EN (0x1 << 2) 52 #define I2CD_SLAVE_EN (0x1 << 1) 53 #define I2CD_MASTER_EN (0x1) 54 55 #define I2CD_AC_TIMING_REG1 0x04 /* Clock and AC Timing Control #1 */ 56 #define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control #1 */ 57 #define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */ 58 #define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */ 59 60 #define I2CD_INTR_SLAVE_ADDR_MATCH (0x1 << 31) /* 0: addr1 1: addr2 */ 61 #define I2CD_INTR_SLAVE_ADDR_RX_PENDING (0x1 << 30) 62 /* bits[19-16] Reserved */ 63 64 /* All bits below are cleared by writing 1 */ 65 #define I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15) 66 #define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) 67 #define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) 68 #define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */ 69 #define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) /* Removed */ 70 #define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */ 71 #define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */ 72 #define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */ 73 #define I2CD_INTR_SLAVE_ADDR_RX_MATCH (0x1 << 7) /* use RX_DONE */ 74 #define I2CD_INTR_SCL_TIMEOUT (0x1 << 6) 75 #define I2CD_INTR_ABNORMAL (0x1 << 5) 76 #define I2CD_INTR_NORMAL_STOP (0x1 << 4) 77 #define I2CD_INTR_ARBIT_LOSS (0x1 << 3) 78 #define I2CD_INTR_RX_DONE (0x1 << 2) 79 #define I2CD_INTR_TX_NAK (0x1 << 1) 80 #define I2CD_INTR_TX_ACK (0x1 << 0) 81 82 #define I2CD_CMD_REG 0x14 /* I2CD Command/Status */ 83 #define I2CD_SDA_OE (0x1 << 28) 84 #define I2CD_SDA_O (0x1 << 27) 85 #define I2CD_SCL_OE (0x1 << 26) 86 #define I2CD_SCL_O (0x1 << 25) 87 #define I2CD_TX_TIMING (0x1 << 24) 88 #define I2CD_TX_STATUS (0x1 << 23) 89 90 #define I2CD_TX_STATE_SHIFT 19 /* Tx State Machine */ 91 #define I2CD_TX_STATE_MASK 0xf 92 #define I2CD_IDLE 0x0 93 #define I2CD_MACTIVE 0x8 94 #define I2CD_MSTART 0x9 95 #define I2CD_MSTARTR 0xa 96 #define I2CD_MSTOP 0xb 97 #define I2CD_MTXD 0xc 98 #define I2CD_MRXACK 0xd 99 #define I2CD_MRXD 0xe 100 #define I2CD_MTXACK 0xf 101 #define I2CD_SWAIT 0x1 102 #define I2CD_SRXD 0x4 103 #define I2CD_STXACK 0x5 104 #define I2CD_STXD 0x6 105 #define I2CD_SRXACK 0x7 106 #define I2CD_RECOVER 0x3 107 108 #define I2CD_SCL_LINE_STS (0x1 << 18) 109 #define I2CD_SDA_LINE_STS (0x1 << 17) 110 #define I2CD_BUS_BUSY_STS (0x1 << 16) 111 #define I2CD_SDA_OE_OUT_DIR (0x1 << 15) 112 #define I2CD_SDA_O_OUT_DIR (0x1 << 14) 113 #define I2CD_SCL_OE_OUT_DIR (0x1 << 13) 114 #define I2CD_SCL_O_OUT_DIR (0x1 << 12) 115 #define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11) 116 #define I2CD_S_ALT_EN (0x1 << 10) 117 118 /* Command Bit */ 119 #define I2CD_RX_DMA_ENABLE (0x1 << 9) 120 #define I2CD_TX_DMA_ENABLE (0x1 << 8) 121 #define I2CD_RX_BUFF_ENABLE (0x1 << 7) 122 #define I2CD_TX_BUFF_ENABLE (0x1 << 6) 123 #define I2CD_M_STOP_CMD (0x1 << 5) 124 #define I2CD_M_S_RX_CMD_LAST (0x1 << 4) 125 #define I2CD_M_RX_CMD (0x1 << 3) 126 #define I2CD_S_TX_CMD (0x1 << 2) 127 #define I2CD_M_TX_CMD (0x1 << 1) 128 #define I2CD_M_START_CMD (0x1) 129 130 #define I2CD_DEV_ADDR_REG 0x18 /* Slave Device Address */ 131 #define I2CD_POOL_CTRL_REG 0x1c /* Pool Buffer Control */ 132 #define I2CD_POOL_RX_COUNT(x) (((x) >> 24) & 0xff) 133 #define I2CD_POOL_RX_SIZE(x) ((((x) >> 16) & 0xff) + 1) 134 #define I2CD_POOL_TX_COUNT(x) ((((x) >> 8) & 0xff) + 1) 135 #define I2CD_POOL_OFFSET(x) (((x) & 0x3f) << 2) /* AST2400 */ 136 #define I2CD_BYTE_BUF_REG 0x20 /* Transmit/Receive Byte Buffer */ 137 #define I2CD_BYTE_BUF_TX_SHIFT 0 138 #define I2CD_BYTE_BUF_TX_MASK 0xff 139 #define I2CD_BYTE_BUF_RX_SHIFT 8 140 #define I2CD_BYTE_BUF_RX_MASK 0xff 141 142 143 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) 144 { 145 return bus->ctrl & I2CD_MASTER_EN; 146 } 147 148 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) 149 { 150 return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN); 151 } 152 153 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) 154 { 155 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 156 157 bus->intr_status &= bus->intr_ctrl; 158 if (bus->intr_status) { 159 bus->controller->intr_status |= 1 << bus->id; 160 qemu_irq_raise(aic->bus_get_irq(bus)); 161 } 162 } 163 164 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, 165 unsigned size) 166 { 167 AspeedI2CBus *bus = opaque; 168 169 switch (offset) { 170 case I2CD_FUN_CTRL_REG: 171 return bus->ctrl; 172 case I2CD_AC_TIMING_REG1: 173 return bus->timing[0]; 174 case I2CD_AC_TIMING_REG2: 175 return bus->timing[1]; 176 case I2CD_INTR_CTRL_REG: 177 return bus->intr_ctrl; 178 case I2CD_INTR_STS_REG: 179 return bus->intr_status; 180 case I2CD_POOL_CTRL_REG: 181 return bus->pool_ctrl; 182 case I2CD_BYTE_BUF_REG: 183 return bus->buf; 184 case I2CD_CMD_REG: 185 return bus->cmd | (i2c_bus_busy(bus->bus) << 16); 186 default: 187 qemu_log_mask(LOG_GUEST_ERROR, 188 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 189 return -1; 190 } 191 } 192 193 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) 194 { 195 bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT); 196 bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT; 197 } 198 199 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) 200 { 201 return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK; 202 } 203 204 static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) 205 { 206 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 207 int ret = -1; 208 int i; 209 210 if (bus->cmd & I2CD_TX_BUFF_ENABLE) { 211 for (i = pool_start; i < I2CD_POOL_TX_COUNT(bus->pool_ctrl); i++) { 212 uint8_t *pool_base = aic->bus_pool_base(bus); 213 214 ret = i2c_send(bus->bus, pool_base[i]); 215 if (ret) { 216 break; 217 } 218 } 219 bus->cmd &= ~I2CD_TX_BUFF_ENABLE; 220 } else { 221 ret = i2c_send(bus->bus, bus->buf); 222 } 223 224 return ret; 225 } 226 227 static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) 228 { 229 AspeedI2CState *s = bus->controller; 230 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 231 uint8_t data; 232 int i; 233 234 if (bus->cmd & I2CD_RX_BUFF_ENABLE) { 235 uint8_t *pool_base = aic->bus_pool_base(bus); 236 237 for (i = 0; i < I2CD_POOL_RX_SIZE(bus->pool_ctrl); i++) { 238 pool_base[i] = i2c_recv(bus->bus); 239 } 240 241 /* Update RX count */ 242 bus->pool_ctrl &= ~(0xff << 24); 243 bus->pool_ctrl |= (i & 0xff) << 24; 244 bus->cmd &= ~I2CD_RX_BUFF_ENABLE; 245 } else { 246 data = i2c_recv(bus->bus); 247 bus->buf = (data & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; 248 } 249 } 250 251 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) 252 { 253 aspeed_i2c_set_state(bus, I2CD_MRXD); 254 aspeed_i2c_bus_recv(bus); 255 bus->intr_status |= I2CD_INTR_RX_DONE; 256 if (bus->cmd & I2CD_M_S_RX_CMD_LAST) { 257 i2c_nack(bus->bus); 258 } 259 bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST); 260 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 261 } 262 263 static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) 264 { 265 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 266 267 if (bus->cmd & I2CD_TX_BUFF_ENABLE) { 268 uint8_t *pool_base = aic->bus_pool_base(bus); 269 270 return pool_base[0]; 271 } else { 272 return bus->buf; 273 } 274 } 275 276 static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) 277 { 278 AspeedI2CState *s = bus->controller; 279 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 280 281 if (!aic->check_sram) { 282 return true; 283 } 284 285 /* 286 * AST2500: SRAM must be enabled before using the Buffer Pool or 287 * DMA mode. 288 */ 289 if (!(s->ctrl_global & I2C_CTRL_SRAM_EN) && 290 (bus->cmd & (I2CD_RX_DMA_ENABLE | I2CD_TX_DMA_ENABLE | 291 I2CD_RX_BUFF_ENABLE | I2CD_TX_BUFF_ENABLE))) { 292 qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__); 293 return false; 294 } 295 296 return true; 297 } 298 299 /* 300 * The state machine needs some refinement. It is only used to track 301 * invalid STOP commands for the moment. 302 */ 303 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 304 { 305 uint8_t pool_start = 0; 306 307 bus->cmd &= ~0xFFFF; 308 bus->cmd |= value & 0xFFFF; 309 310 if (!aspeed_i2c_check_sram(bus)) { 311 return; 312 } 313 314 if (bus->cmd & I2CD_M_START_CMD) { 315 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? 316 I2CD_MSTARTR : I2CD_MSTART; 317 uint8_t addr; 318 319 aspeed_i2c_set_state(bus, state); 320 321 addr = aspeed_i2c_get_addr(bus); 322 323 if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), 324 extract32(addr, 0, 1))) { 325 bus->intr_status |= I2CD_INTR_TX_NAK; 326 } else { 327 bus->intr_status |= I2CD_INTR_TX_ACK; 328 } 329 330 bus->cmd &= ~I2CD_M_START_CMD; 331 332 /* 333 * The START command is also a TX command, as the slave 334 * address is sent on the bus. Drop the TX flag if nothing 335 * else needs to be sent in this sequence. 336 */ 337 if (bus->cmd & I2CD_TX_BUFF_ENABLE) { 338 if (I2CD_POOL_TX_COUNT(bus->pool_ctrl) == 1) { 339 bus->cmd &= ~I2CD_M_TX_CMD; 340 } else { 341 /* 342 * Increase the start index in the TX pool buffer to 343 * skip the address byte. 344 */ 345 pool_start++; 346 } 347 } else { 348 bus->cmd &= ~I2CD_M_TX_CMD; 349 } 350 351 /* No slave found */ 352 if (!i2c_bus_busy(bus->bus)) { 353 return; 354 } 355 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 356 } 357 358 if (bus->cmd & I2CD_M_TX_CMD) { 359 aspeed_i2c_set_state(bus, I2CD_MTXD); 360 if (aspeed_i2c_bus_send(bus, pool_start)) { 361 bus->intr_status |= (I2CD_INTR_TX_NAK); 362 i2c_end_transfer(bus->bus); 363 } else { 364 bus->intr_status |= I2CD_INTR_TX_ACK; 365 } 366 bus->cmd &= ~I2CD_M_TX_CMD; 367 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 368 } 369 370 if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) && 371 !(bus->intr_status & I2CD_INTR_RX_DONE)) { 372 aspeed_i2c_handle_rx_cmd(bus); 373 } 374 375 if (bus->cmd & I2CD_M_STOP_CMD) { 376 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { 377 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); 378 bus->intr_status |= I2CD_INTR_ABNORMAL; 379 } else { 380 aspeed_i2c_set_state(bus, I2CD_MSTOP); 381 i2c_end_transfer(bus->bus); 382 bus->intr_status |= I2CD_INTR_NORMAL_STOP; 383 } 384 bus->cmd &= ~I2CD_M_STOP_CMD; 385 aspeed_i2c_set_state(bus, I2CD_IDLE); 386 } 387 } 388 389 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, 390 uint64_t value, unsigned size) 391 { 392 AspeedI2CBus *bus = opaque; 393 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 394 bool handle_rx; 395 396 switch (offset) { 397 case I2CD_FUN_CTRL_REG: 398 if (value & I2CD_SLAVE_EN) { 399 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 400 __func__); 401 break; 402 } 403 bus->ctrl = value & 0x0071C3FF; 404 break; 405 case I2CD_AC_TIMING_REG1: 406 bus->timing[0] = value & 0xFFFFF0F; 407 break; 408 case I2CD_AC_TIMING_REG2: 409 bus->timing[1] = value & 0x7; 410 break; 411 case I2CD_INTR_CTRL_REG: 412 bus->intr_ctrl = value & 0x7FFF; 413 break; 414 case I2CD_INTR_STS_REG: 415 handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) && 416 (value & I2CD_INTR_RX_DONE); 417 bus->intr_status &= ~(value & 0x7FFF); 418 if (!bus->intr_status) { 419 bus->controller->intr_status &= ~(1 << bus->id); 420 qemu_irq_lower(aic->bus_get_irq(bus)); 421 } 422 if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) { 423 aspeed_i2c_handle_rx_cmd(bus); 424 aspeed_i2c_bus_raise_interrupt(bus); 425 } 426 break; 427 case I2CD_DEV_ADDR_REG: 428 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 429 __func__); 430 break; 431 case I2CD_POOL_CTRL_REG: 432 bus->pool_ctrl &= ~0xffffff; 433 bus->pool_ctrl |= (value & 0xffffff); 434 break; 435 436 case I2CD_BYTE_BUF_REG: 437 bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT; 438 break; 439 case I2CD_CMD_REG: 440 if (!aspeed_i2c_bus_is_enabled(bus)) { 441 break; 442 } 443 444 if (!aspeed_i2c_bus_is_master(bus)) { 445 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 446 __func__); 447 break; 448 } 449 450 aspeed_i2c_bus_handle_cmd(bus, value); 451 aspeed_i2c_bus_raise_interrupt(bus); 452 break; 453 454 default: 455 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 456 __func__, offset); 457 } 458 } 459 460 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, 461 unsigned size) 462 { 463 AspeedI2CState *s = opaque; 464 465 switch (offset) { 466 case I2C_CTRL_STATUS: 467 return s->intr_status; 468 case I2C_CTRL_GLOBAL: 469 return s->ctrl_global; 470 default: 471 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 472 __func__, offset); 473 break; 474 } 475 476 return -1; 477 } 478 479 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, 480 uint64_t value, unsigned size) 481 { 482 AspeedI2CState *s = opaque; 483 484 switch (offset) { 485 case I2C_CTRL_GLOBAL: 486 s->ctrl_global = value; 487 break; 488 case I2C_CTRL_STATUS: 489 default: 490 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 491 __func__, offset); 492 break; 493 } 494 } 495 496 static const MemoryRegionOps aspeed_i2c_bus_ops = { 497 .read = aspeed_i2c_bus_read, 498 .write = aspeed_i2c_bus_write, 499 .endianness = DEVICE_LITTLE_ENDIAN, 500 }; 501 502 static const MemoryRegionOps aspeed_i2c_ctrl_ops = { 503 .read = aspeed_i2c_ctrl_read, 504 .write = aspeed_i2c_ctrl_write, 505 .endianness = DEVICE_LITTLE_ENDIAN, 506 }; 507 508 static uint64_t aspeed_i2c_pool_read(void *opaque, hwaddr offset, 509 unsigned size) 510 { 511 AspeedI2CState *s = opaque; 512 uint64_t ret = 0; 513 int i; 514 515 for (i = 0; i < size; i++) { 516 ret |= (uint64_t) s->pool[offset + i] << (8 * i); 517 } 518 519 return ret; 520 } 521 522 static void aspeed_i2c_pool_write(void *opaque, hwaddr offset, 523 uint64_t value, unsigned size) 524 { 525 AspeedI2CState *s = opaque; 526 int i; 527 528 for (i = 0; i < size; i++) { 529 s->pool[offset + i] = (value >> (8 * i)) & 0xFF; 530 } 531 } 532 533 static const MemoryRegionOps aspeed_i2c_pool_ops = { 534 .read = aspeed_i2c_pool_read, 535 .write = aspeed_i2c_pool_write, 536 .endianness = DEVICE_LITTLE_ENDIAN, 537 .valid = { 538 .min_access_size = 1, 539 .max_access_size = 4, 540 }, 541 }; 542 543 static const VMStateDescription aspeed_i2c_bus_vmstate = { 544 .name = TYPE_ASPEED_I2C, 545 .version_id = 2, 546 .minimum_version_id = 2, 547 .fields = (VMStateField[]) { 548 VMSTATE_UINT8(id, AspeedI2CBus), 549 VMSTATE_UINT32(ctrl, AspeedI2CBus), 550 VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2), 551 VMSTATE_UINT32(intr_ctrl, AspeedI2CBus), 552 VMSTATE_UINT32(intr_status, AspeedI2CBus), 553 VMSTATE_UINT32(cmd, AspeedI2CBus), 554 VMSTATE_UINT32(buf, AspeedI2CBus), 555 VMSTATE_UINT32(pool_ctrl, AspeedI2CBus), 556 VMSTATE_END_OF_LIST() 557 } 558 }; 559 560 static const VMStateDescription aspeed_i2c_vmstate = { 561 .name = TYPE_ASPEED_I2C, 562 .version_id = 2, 563 .minimum_version_id = 2, 564 .fields = (VMStateField[]) { 565 VMSTATE_UINT32(intr_status, AspeedI2CState), 566 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, 567 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, 568 AspeedI2CBus), 569 VMSTATE_UINT8_ARRAY(pool, AspeedI2CState, ASPEED_I2C_MAX_POOL_SIZE), 570 VMSTATE_END_OF_LIST() 571 } 572 }; 573 574 static void aspeed_i2c_reset(DeviceState *dev) 575 { 576 int i; 577 AspeedI2CState *s = ASPEED_I2C(dev); 578 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 579 580 s->intr_status = 0; 581 582 for (i = 0; i < aic->num_busses; i++) { 583 s->busses[i].intr_ctrl = 0; 584 s->busses[i].intr_status = 0; 585 s->busses[i].cmd = 0; 586 s->busses[i].buf = 0; 587 i2c_end_transfer(s->busses[i].bus); 588 } 589 } 590 591 /* 592 * Address Definitions (AST2400 and AST2500) 593 * 594 * 0x000 ... 0x03F: Global Register 595 * 0x040 ... 0x07F: Device 1 596 * 0x080 ... 0x0BF: Device 2 597 * 0x0C0 ... 0x0FF: Device 3 598 * 0x100 ... 0x13F: Device 4 599 * 0x140 ... 0x17F: Device 5 600 * 0x180 ... 0x1BF: Device 6 601 * 0x1C0 ... 0x1FF: Device 7 602 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver) 603 * 0x300 ... 0x33F: Device 8 604 * 0x340 ... 0x37F: Device 9 605 * 0x380 ... 0x3BF: Device 10 606 * 0x3C0 ... 0x3FF: Device 11 607 * 0x400 ... 0x43F: Device 12 608 * 0x440 ... 0x47F: Device 13 609 * 0x480 ... 0x4BF: Device 14 610 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver) 611 */ 612 static void aspeed_i2c_realize(DeviceState *dev, Error **errp) 613 { 614 int i; 615 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 616 AspeedI2CState *s = ASPEED_I2C(dev); 617 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 618 619 sysbus_init_irq(sbd, &s->irq); 620 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, 621 "aspeed.i2c", 0x1000); 622 sysbus_init_mmio(sbd, &s->iomem); 623 624 for (i = 0; i < aic->num_busses; i++) { 625 char name[32]; 626 int offset = i < aic->gap ? 1 : 5; 627 628 sysbus_init_irq(sbd, &s->busses[i].irq); 629 snprintf(name, sizeof(name), "aspeed.i2c.%d", i); 630 s->busses[i].controller = s; 631 s->busses[i].id = i; 632 s->busses[i].bus = i2c_init_bus(dev, name); 633 memory_region_init_io(&s->busses[i].mr, OBJECT(dev), 634 &aspeed_i2c_bus_ops, &s->busses[i], name, 635 aic->reg_size); 636 memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), 637 &s->busses[i].mr); 638 } 639 640 memory_region_init_io(&s->pool_iomem, OBJECT(s), &aspeed_i2c_pool_ops, s, 641 "aspeed.i2c-pool", aic->pool_size); 642 memory_region_add_subregion(&s->iomem, aic->pool_base, &s->pool_iomem); 643 } 644 645 static void aspeed_i2c_class_init(ObjectClass *klass, void *data) 646 { 647 DeviceClass *dc = DEVICE_CLASS(klass); 648 649 dc->vmsd = &aspeed_i2c_vmstate; 650 dc->reset = aspeed_i2c_reset; 651 dc->realize = aspeed_i2c_realize; 652 dc->desc = "Aspeed I2C Controller"; 653 } 654 655 static const TypeInfo aspeed_i2c_info = { 656 .name = TYPE_ASPEED_I2C, 657 .parent = TYPE_SYS_BUS_DEVICE, 658 .instance_size = sizeof(AspeedI2CState), 659 .class_init = aspeed_i2c_class_init, 660 .class_size = sizeof(AspeedI2CClass), 661 .abstract = true, 662 }; 663 664 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) 665 { 666 return bus->controller->irq; 667 } 668 669 static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) 670 { 671 uint8_t *pool_page = 672 &bus->controller->pool[I2CD_POOL_PAGE_SEL(bus->ctrl) * 0x100]; 673 674 return &pool_page[I2CD_POOL_OFFSET(bus->pool_ctrl)]; 675 } 676 677 static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) 678 { 679 DeviceClass *dc = DEVICE_CLASS(klass); 680 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 681 682 dc->desc = "ASPEED 2400 I2C Controller"; 683 684 aic->num_busses = 14; 685 aic->reg_size = 0x40; 686 aic->gap = 7; 687 aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; 688 aic->pool_size = 0x800; 689 aic->pool_base = 0x800; 690 aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; 691 } 692 693 static const TypeInfo aspeed_2400_i2c_info = { 694 .name = TYPE_ASPEED_2400_I2C, 695 .parent = TYPE_ASPEED_I2C, 696 .class_init = aspeed_2400_i2c_class_init, 697 }; 698 699 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) 700 { 701 return bus->controller->irq; 702 } 703 704 static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) 705 { 706 return &bus->controller->pool[bus->id * 0x10]; 707 } 708 709 static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) 710 { 711 DeviceClass *dc = DEVICE_CLASS(klass); 712 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 713 714 dc->desc = "ASPEED 2500 I2C Controller"; 715 716 aic->num_busses = 14; 717 aic->reg_size = 0x40; 718 aic->gap = 7; 719 aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; 720 aic->pool_size = 0x100; 721 aic->pool_base = 0x200; 722 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 723 aic->check_sram = true; 724 } 725 726 static const TypeInfo aspeed_2500_i2c_info = { 727 .name = TYPE_ASPEED_2500_I2C, 728 .parent = TYPE_ASPEED_I2C, 729 .class_init = aspeed_2500_i2c_class_init, 730 }; 731 732 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) 733 { 734 return bus->irq; 735 } 736 737 static uint8_t *aspeed_2600_i2c_bus_pool_base(AspeedI2CBus *bus) 738 { 739 return &bus->controller->pool[bus->id * 0x20]; 740 } 741 742 static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) 743 { 744 DeviceClass *dc = DEVICE_CLASS(klass); 745 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 746 747 dc->desc = "ASPEED 2600 I2C Controller"; 748 749 aic->num_busses = 16; 750 aic->reg_size = 0x80; 751 aic->gap = -1; /* no gap */ 752 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 753 aic->pool_size = 0x200; 754 aic->pool_base = 0xC00; 755 aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; 756 } 757 758 static const TypeInfo aspeed_2600_i2c_info = { 759 .name = TYPE_ASPEED_2600_I2C, 760 .parent = TYPE_ASPEED_I2C, 761 .class_init = aspeed_2600_i2c_class_init, 762 }; 763 764 static void aspeed_i2c_register_types(void) 765 { 766 type_register_static(&aspeed_i2c_info); 767 type_register_static(&aspeed_2400_i2c_info); 768 type_register_static(&aspeed_2500_i2c_info); 769 type_register_static(&aspeed_2600_i2c_info); 770 } 771 772 type_init(aspeed_i2c_register_types) 773 774 775 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr) 776 { 777 AspeedI2CState *s = ASPEED_I2C(dev); 778 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 779 I2CBus *bus = NULL; 780 781 if (busnr >= 0 && busnr < aic->num_busses) { 782 bus = s->busses[busnr].bus; 783 } 784 785 return bus; 786 } 787