1 /* 2 * ARM Aspeed I2C controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "qemu/log.h" 24 #include "hw/i2c/aspeed_i2c.h" 25 26 /* I2C Global Register */ 27 28 #define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */ 29 #define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target 30 Assignment */ 31 32 /* I2C Device (Bus) Register */ 33 34 #define I2CD_FUN_CTRL_REG 0x00 /* I2CD Function Control */ 35 #define I2CD_BUFF_SEL_MASK (0x7 << 20) 36 #define I2CD_BUFF_SEL(x) (x << 20) 37 #define I2CD_M_SDA_LOCK_EN (0x1 << 16) 38 #define I2CD_MULTI_MASTER_DIS (0x1 << 15) 39 #define I2CD_M_SCL_DRIVE_EN (0x1 << 14) 40 #define I2CD_MSB_STS (0x1 << 9) 41 #define I2CD_SDA_DRIVE_1T_EN (0x1 << 8) 42 #define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) 43 #define I2CD_M_HIGH_SPEED_EN (0x1 << 6) 44 #define I2CD_DEF_ADDR_EN (0x1 << 5) 45 #define I2CD_DEF_ALERT_EN (0x1 << 4) 46 #define I2CD_DEF_ARP_EN (0x1 << 3) 47 #define I2CD_DEF_GCALL_EN (0x1 << 2) 48 #define I2CD_SLAVE_EN (0x1 << 1) 49 #define I2CD_MASTER_EN (0x1) 50 51 #define I2CD_AC_TIMING_REG1 0x04 /* Clock and AC Timing Control #1 */ 52 #define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control #1 */ 53 #define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */ 54 #define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */ 55 56 #define I2CD_INTR_SLAVE_ADDR_MATCH (0x1 << 31) /* 0: addr1 1: addr2 */ 57 #define I2CD_INTR_SLAVE_ADDR_RX_PENDING (0x1 << 30) 58 /* bits[19-16] Reserved */ 59 60 /* All bits below are cleared by writing 1 */ 61 #define I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15) 62 #define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) 63 #define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) 64 #define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */ 65 #define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) /* Removed */ 66 #define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */ 67 #define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */ 68 #define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */ 69 #define I2CD_INTR_SLAVE_ADDR_RX_MATCH (0x1 << 7) /* use RX_DONE */ 70 #define I2CD_INTR_SCL_TIMEOUT (0x1 << 6) 71 #define I2CD_INTR_ABNORMAL (0x1 << 5) 72 #define I2CD_INTR_NORMAL_STOP (0x1 << 4) 73 #define I2CD_INTR_ARBIT_LOSS (0x1 << 3) 74 #define I2CD_INTR_RX_DONE (0x1 << 2) 75 #define I2CD_INTR_TX_NAK (0x1 << 1) 76 #define I2CD_INTR_TX_ACK (0x1 << 0) 77 78 #define I2CD_CMD_REG 0x14 /* I2CD Command/Status */ 79 #define I2CD_SDA_OE (0x1 << 28) 80 #define I2CD_SDA_O (0x1 << 27) 81 #define I2CD_SCL_OE (0x1 << 26) 82 #define I2CD_SCL_O (0x1 << 25) 83 #define I2CD_TX_TIMING (0x1 << 24) 84 #define I2CD_TX_STATUS (0x1 << 23) 85 86 #define I2CD_TX_STATE_SHIFT 19 /* Tx State Machine */ 87 #define I2CD_TX_STATE_MASK 0xf 88 #define I2CD_IDLE 0x0 89 #define I2CD_MACTIVE 0x8 90 #define I2CD_MSTART 0x9 91 #define I2CD_MSTARTR 0xa 92 #define I2CD_MSTOP 0xb 93 #define I2CD_MTXD 0xc 94 #define I2CD_MRXACK 0xd 95 #define I2CD_MRXD 0xe 96 #define I2CD_MTXACK 0xf 97 #define I2CD_SWAIT 0x1 98 #define I2CD_SRXD 0x4 99 #define I2CD_STXACK 0x5 100 #define I2CD_STXD 0x6 101 #define I2CD_SRXACK 0x7 102 #define I2CD_RECOVER 0x3 103 104 #define I2CD_SCL_LINE_STS (0x1 << 18) 105 #define I2CD_SDA_LINE_STS (0x1 << 17) 106 #define I2CD_BUS_BUSY_STS (0x1 << 16) 107 #define I2CD_SDA_OE_OUT_DIR (0x1 << 15) 108 #define I2CD_SDA_O_OUT_DIR (0x1 << 14) 109 #define I2CD_SCL_OE_OUT_DIR (0x1 << 13) 110 #define I2CD_SCL_O_OUT_DIR (0x1 << 12) 111 #define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11) 112 #define I2CD_S_ALT_EN (0x1 << 10) 113 #define I2CD_RX_DMA_ENABLE (0x1 << 9) 114 #define I2CD_TX_DMA_ENABLE (0x1 << 8) 115 116 /* Command Bit */ 117 #define I2CD_M_STOP_CMD (0x1 << 5) 118 #define I2CD_M_S_RX_CMD_LAST (0x1 << 4) 119 #define I2CD_M_RX_CMD (0x1 << 3) 120 #define I2CD_S_TX_CMD (0x1 << 2) 121 #define I2CD_M_TX_CMD (0x1 << 1) 122 #define I2CD_M_START_CMD (0x1) 123 124 #define I2CD_DEV_ADDR_REG 0x18 /* Slave Device Address */ 125 #define I2CD_BUF_CTRL_REG 0x1c /* Pool Buffer Control */ 126 #define I2CD_BYTE_BUF_REG 0x20 /* Transmit/Receive Byte Buffer */ 127 #define I2CD_BYTE_BUF_TX_SHIFT 0 128 #define I2CD_BYTE_BUF_TX_MASK 0xff 129 #define I2CD_BYTE_BUF_RX_SHIFT 8 130 #define I2CD_BYTE_BUF_RX_MASK 0xff 131 132 133 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) 134 { 135 return bus->ctrl & I2CD_MASTER_EN; 136 } 137 138 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) 139 { 140 return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN); 141 } 142 143 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) 144 { 145 bus->intr_status &= bus->intr_ctrl; 146 if (bus->intr_status) { 147 bus->controller->intr_status |= 1 << bus->id; 148 qemu_irq_raise(bus->controller->irq); 149 } 150 } 151 152 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, 153 unsigned size) 154 { 155 AspeedI2CBus *bus = opaque; 156 157 switch (offset) { 158 case I2CD_FUN_CTRL_REG: 159 return bus->ctrl; 160 case I2CD_AC_TIMING_REG1: 161 return bus->timing[0]; 162 case I2CD_AC_TIMING_REG2: 163 return bus->timing[1]; 164 case I2CD_INTR_CTRL_REG: 165 return bus->intr_ctrl; 166 case I2CD_INTR_STS_REG: 167 return bus->intr_status; 168 case I2CD_BYTE_BUF_REG: 169 return bus->buf; 170 case I2CD_CMD_REG: 171 return bus->cmd | (i2c_bus_busy(bus->bus) << 16); 172 default: 173 qemu_log_mask(LOG_GUEST_ERROR, 174 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 175 return -1; 176 } 177 } 178 179 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) 180 { 181 bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT); 182 bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT; 183 } 184 185 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) 186 { 187 return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK; 188 } 189 190 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) 191 { 192 uint8_t ret; 193 194 aspeed_i2c_set_state(bus, I2CD_MRXD); 195 ret = i2c_recv(bus->bus); 196 bus->intr_status |= I2CD_INTR_RX_DONE; 197 bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; 198 if (bus->cmd & I2CD_M_S_RX_CMD_LAST) { 199 i2c_nack(bus->bus); 200 } 201 bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST); 202 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 203 } 204 205 /* 206 * The state machine needs some refinement. It is only used to track 207 * invalid STOP commands for the moment. 208 */ 209 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 210 { 211 bus->cmd &= ~0xFFFF; 212 bus->cmd |= value & 0xFFFF; 213 214 if (bus->cmd & I2CD_M_START_CMD) { 215 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? 216 I2CD_MSTARTR : I2CD_MSTART; 217 218 aspeed_i2c_set_state(bus, state); 219 220 if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7), 221 extract32(bus->buf, 0, 1))) { 222 bus->intr_status |= I2CD_INTR_TX_NAK; 223 } else { 224 bus->intr_status |= I2CD_INTR_TX_ACK; 225 } 226 227 /* START command is also a TX command, as the slave address is 228 * sent on the bus */ 229 bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD); 230 231 /* No slave found */ 232 if (!i2c_bus_busy(bus->bus)) { 233 return; 234 } 235 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 236 } 237 238 if (bus->cmd & I2CD_M_TX_CMD) { 239 aspeed_i2c_set_state(bus, I2CD_MTXD); 240 if (i2c_send(bus->bus, bus->buf)) { 241 bus->intr_status |= (I2CD_INTR_TX_NAK); 242 i2c_end_transfer(bus->bus); 243 } else { 244 bus->intr_status |= I2CD_INTR_TX_ACK; 245 } 246 bus->cmd &= ~I2CD_M_TX_CMD; 247 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 248 } 249 250 if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) && 251 !(bus->intr_status & I2CD_INTR_RX_DONE)) { 252 aspeed_i2c_handle_rx_cmd(bus); 253 } 254 255 if (bus->cmd & I2CD_M_STOP_CMD) { 256 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { 257 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); 258 bus->intr_status |= I2CD_INTR_ABNORMAL; 259 } else { 260 aspeed_i2c_set_state(bus, I2CD_MSTOP); 261 i2c_end_transfer(bus->bus); 262 bus->intr_status |= I2CD_INTR_NORMAL_STOP; 263 } 264 bus->cmd &= ~I2CD_M_STOP_CMD; 265 aspeed_i2c_set_state(bus, I2CD_IDLE); 266 } 267 } 268 269 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, 270 uint64_t value, unsigned size) 271 { 272 AspeedI2CBus *bus = opaque; 273 bool handle_rx; 274 275 switch (offset) { 276 case I2CD_FUN_CTRL_REG: 277 if (value & I2CD_SLAVE_EN) { 278 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 279 __func__); 280 break; 281 } 282 bus->ctrl = value & 0x0071C3FF; 283 break; 284 case I2CD_AC_TIMING_REG1: 285 bus->timing[0] = value & 0xFFFFF0F; 286 break; 287 case I2CD_AC_TIMING_REG2: 288 bus->timing[1] = value & 0x7; 289 break; 290 case I2CD_INTR_CTRL_REG: 291 bus->intr_ctrl = value & 0x7FFF; 292 break; 293 case I2CD_INTR_STS_REG: 294 handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) && 295 (value & I2CD_INTR_RX_DONE); 296 bus->intr_status &= ~(value & 0x7FFF); 297 if (!bus->intr_status) { 298 bus->controller->intr_status &= ~(1 << bus->id); 299 qemu_irq_lower(bus->controller->irq); 300 } 301 if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) { 302 aspeed_i2c_handle_rx_cmd(bus); 303 aspeed_i2c_bus_raise_interrupt(bus); 304 } 305 break; 306 case I2CD_DEV_ADDR_REG: 307 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 308 __func__); 309 break; 310 case I2CD_BYTE_BUF_REG: 311 bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT; 312 break; 313 case I2CD_CMD_REG: 314 if (!aspeed_i2c_bus_is_enabled(bus)) { 315 break; 316 } 317 318 if (!aspeed_i2c_bus_is_master(bus)) { 319 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 320 __func__); 321 break; 322 } 323 324 aspeed_i2c_bus_handle_cmd(bus, value); 325 aspeed_i2c_bus_raise_interrupt(bus); 326 break; 327 328 default: 329 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 330 __func__, offset); 331 } 332 } 333 334 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, 335 unsigned size) 336 { 337 AspeedI2CState *s = opaque; 338 339 switch (offset) { 340 case I2C_CTRL_STATUS: 341 return s->intr_status; 342 default: 343 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 344 __func__, offset); 345 break; 346 } 347 348 return -1; 349 } 350 351 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, 352 uint64_t value, unsigned size) 353 { 354 switch (offset) { 355 case I2C_CTRL_STATUS: 356 default: 357 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 358 __func__, offset); 359 break; 360 } 361 } 362 363 static const MemoryRegionOps aspeed_i2c_bus_ops = { 364 .read = aspeed_i2c_bus_read, 365 .write = aspeed_i2c_bus_write, 366 .endianness = DEVICE_LITTLE_ENDIAN, 367 }; 368 369 static const MemoryRegionOps aspeed_i2c_ctrl_ops = { 370 .read = aspeed_i2c_ctrl_read, 371 .write = aspeed_i2c_ctrl_write, 372 .endianness = DEVICE_LITTLE_ENDIAN, 373 }; 374 375 static const VMStateDescription aspeed_i2c_bus_vmstate = { 376 .name = TYPE_ASPEED_I2C, 377 .version_id = 1, 378 .minimum_version_id = 1, 379 .fields = (VMStateField[]) { 380 VMSTATE_UINT8(id, AspeedI2CBus), 381 VMSTATE_UINT32(ctrl, AspeedI2CBus), 382 VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2), 383 VMSTATE_UINT32(intr_ctrl, AspeedI2CBus), 384 VMSTATE_UINT32(intr_status, AspeedI2CBus), 385 VMSTATE_UINT32(cmd, AspeedI2CBus), 386 VMSTATE_UINT32(buf, AspeedI2CBus), 387 VMSTATE_END_OF_LIST() 388 } 389 }; 390 391 static const VMStateDescription aspeed_i2c_vmstate = { 392 .name = TYPE_ASPEED_I2C, 393 .version_id = 1, 394 .minimum_version_id = 1, 395 .fields = (VMStateField[]) { 396 VMSTATE_UINT32(intr_status, AspeedI2CState), 397 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, 398 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, 399 AspeedI2CBus), 400 VMSTATE_END_OF_LIST() 401 } 402 }; 403 404 static void aspeed_i2c_reset(DeviceState *dev) 405 { 406 int i; 407 AspeedI2CState *s = ASPEED_I2C(dev); 408 409 s->intr_status = 0; 410 411 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) { 412 s->busses[i].intr_ctrl = 0; 413 s->busses[i].intr_status = 0; 414 s->busses[i].cmd = 0; 415 s->busses[i].buf = 0; 416 i2c_end_transfer(s->busses[i].bus); 417 } 418 } 419 420 /* 421 * Address Definitions 422 * 423 * 0x000 ... 0x03F: Global Register 424 * 0x040 ... 0x07F: Device 1 425 * 0x080 ... 0x0BF: Device 2 426 * 0x0C0 ... 0x0FF: Device 3 427 * 0x100 ... 0x13F: Device 4 428 * 0x140 ... 0x17F: Device 5 429 * 0x180 ... 0x1BF: Device 6 430 * 0x1C0 ... 0x1FF: Device 7 431 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver) 432 * 0x300 ... 0x33F: Device 8 433 * 0x340 ... 0x37F: Device 9 434 * 0x380 ... 0x3BF: Device 10 435 * 0x3C0 ... 0x3FF: Device 11 436 * 0x400 ... 0x43F: Device 12 437 * 0x440 ... 0x47F: Device 13 438 * 0x480 ... 0x4BF: Device 14 439 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver) 440 */ 441 static void aspeed_i2c_realize(DeviceState *dev, Error **errp) 442 { 443 int i; 444 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 445 AspeedI2CState *s = ASPEED_I2C(dev); 446 447 sysbus_init_irq(sbd, &s->irq); 448 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, 449 "aspeed.i2c", 0x1000); 450 sysbus_init_mmio(sbd, &s->iomem); 451 452 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) { 453 char name[16]; 454 int offset = i < 7 ? 1 : 5; 455 snprintf(name, sizeof(name), "aspeed.i2c.%d", i); 456 s->busses[i].controller = s; 457 s->busses[i].id = i; 458 s->busses[i].bus = i2c_init_bus(dev, name); 459 memory_region_init_io(&s->busses[i].mr, OBJECT(dev), 460 &aspeed_i2c_bus_ops, &s->busses[i], name, 0x40); 461 memory_region_add_subregion(&s->iomem, 0x40 * (i + offset), 462 &s->busses[i].mr); 463 } 464 } 465 466 static void aspeed_i2c_class_init(ObjectClass *klass, void *data) 467 { 468 DeviceClass *dc = DEVICE_CLASS(klass); 469 470 dc->vmsd = &aspeed_i2c_vmstate; 471 dc->reset = aspeed_i2c_reset; 472 dc->realize = aspeed_i2c_realize; 473 dc->desc = "Aspeed I2C Controller"; 474 } 475 476 static const TypeInfo aspeed_i2c_info = { 477 .name = TYPE_ASPEED_I2C, 478 .parent = TYPE_SYS_BUS_DEVICE, 479 .instance_size = sizeof(AspeedI2CState), 480 .class_init = aspeed_i2c_class_init, 481 }; 482 483 static void aspeed_i2c_register_types(void) 484 { 485 type_register_static(&aspeed_i2c_info); 486 } 487 488 type_init(aspeed_i2c_register_types) 489 490 491 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr) 492 { 493 AspeedI2CState *s = ASPEED_I2C(dev); 494 I2CBus *bus = NULL; 495 496 if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) { 497 bus = s->busses[busnr].bus; 498 } 499 500 return bus; 501 } 502