1 /* 2 * ARM Aspeed I2C controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "hw/i2c/aspeed_i2c.h" 29 #include "hw/irq.h" 30 #include "hw/qdev-properties.h" 31 32 /* I2C Global Register */ 33 34 #define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */ 35 #define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target 36 Assignment */ 37 #define I2C_CTRL_GLOBAL 0x0C /* Global Control Register */ 38 #define I2C_CTRL_SRAM_EN BIT(0) 39 40 /* I2C Device (Bus) Register */ 41 42 #define I2CD_FUN_CTRL_REG 0x00 /* I2CD Function Control */ 43 #define I2CD_POOL_PAGE_SEL(x) (((x) >> 20) & 0x7) /* AST2400 */ 44 #define I2CD_M_SDA_LOCK_EN (0x1 << 16) 45 #define I2CD_MULTI_MASTER_DIS (0x1 << 15) 46 #define I2CD_M_SCL_DRIVE_EN (0x1 << 14) 47 #define I2CD_MSB_STS (0x1 << 9) 48 #define I2CD_SDA_DRIVE_1T_EN (0x1 << 8) 49 #define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) 50 #define I2CD_M_HIGH_SPEED_EN (0x1 << 6) 51 #define I2CD_DEF_ADDR_EN (0x1 << 5) 52 #define I2CD_DEF_ALERT_EN (0x1 << 4) 53 #define I2CD_DEF_ARP_EN (0x1 << 3) 54 #define I2CD_DEF_GCALL_EN (0x1 << 2) 55 #define I2CD_SLAVE_EN (0x1 << 1) 56 #define I2CD_MASTER_EN (0x1) 57 58 #define I2CD_AC_TIMING_REG1 0x04 /* Clock and AC Timing Control #1 */ 59 #define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control #1 */ 60 #define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */ 61 #define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */ 62 63 #define I2CD_INTR_SLAVE_ADDR_MATCH (0x1 << 31) /* 0: addr1 1: addr2 */ 64 #define I2CD_INTR_SLAVE_ADDR_RX_PENDING (0x1 << 30) 65 /* bits[19-16] Reserved */ 66 67 /* All bits below are cleared by writing 1 */ 68 #define I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15) 69 #define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) 70 #define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) 71 #define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */ 72 #define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) /* Removed */ 73 #define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */ 74 #define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */ 75 #define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */ 76 #define I2CD_INTR_SLAVE_ADDR_RX_MATCH (0x1 << 7) /* use RX_DONE */ 77 #define I2CD_INTR_SCL_TIMEOUT (0x1 << 6) 78 #define I2CD_INTR_ABNORMAL (0x1 << 5) 79 #define I2CD_INTR_NORMAL_STOP (0x1 << 4) 80 #define I2CD_INTR_ARBIT_LOSS (0x1 << 3) 81 #define I2CD_INTR_RX_DONE (0x1 << 2) 82 #define I2CD_INTR_TX_NAK (0x1 << 1) 83 #define I2CD_INTR_TX_ACK (0x1 << 0) 84 85 #define I2CD_CMD_REG 0x14 /* I2CD Command/Status */ 86 #define I2CD_SDA_OE (0x1 << 28) 87 #define I2CD_SDA_O (0x1 << 27) 88 #define I2CD_SCL_OE (0x1 << 26) 89 #define I2CD_SCL_O (0x1 << 25) 90 #define I2CD_TX_TIMING (0x1 << 24) 91 #define I2CD_TX_STATUS (0x1 << 23) 92 93 #define I2CD_TX_STATE_SHIFT 19 /* Tx State Machine */ 94 #define I2CD_TX_STATE_MASK 0xf 95 #define I2CD_IDLE 0x0 96 #define I2CD_MACTIVE 0x8 97 #define I2CD_MSTART 0x9 98 #define I2CD_MSTARTR 0xa 99 #define I2CD_MSTOP 0xb 100 #define I2CD_MTXD 0xc 101 #define I2CD_MRXACK 0xd 102 #define I2CD_MRXD 0xe 103 #define I2CD_MTXACK 0xf 104 #define I2CD_SWAIT 0x1 105 #define I2CD_SRXD 0x4 106 #define I2CD_STXACK 0x5 107 #define I2CD_STXD 0x6 108 #define I2CD_SRXACK 0x7 109 #define I2CD_RECOVER 0x3 110 111 #define I2CD_SCL_LINE_STS (0x1 << 18) 112 #define I2CD_SDA_LINE_STS (0x1 << 17) 113 #define I2CD_BUS_BUSY_STS (0x1 << 16) 114 #define I2CD_SDA_OE_OUT_DIR (0x1 << 15) 115 #define I2CD_SDA_O_OUT_DIR (0x1 << 14) 116 #define I2CD_SCL_OE_OUT_DIR (0x1 << 13) 117 #define I2CD_SCL_O_OUT_DIR (0x1 << 12) 118 #define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11) 119 #define I2CD_S_ALT_EN (0x1 << 10) 120 121 /* Command Bit */ 122 #define I2CD_RX_DMA_ENABLE (0x1 << 9) 123 #define I2CD_TX_DMA_ENABLE (0x1 << 8) 124 #define I2CD_RX_BUFF_ENABLE (0x1 << 7) 125 #define I2CD_TX_BUFF_ENABLE (0x1 << 6) 126 #define I2CD_M_STOP_CMD (0x1 << 5) 127 #define I2CD_M_S_RX_CMD_LAST (0x1 << 4) 128 #define I2CD_M_RX_CMD (0x1 << 3) 129 #define I2CD_S_TX_CMD (0x1 << 2) 130 #define I2CD_M_TX_CMD (0x1 << 1) 131 #define I2CD_M_START_CMD (0x1) 132 133 #define I2CD_DEV_ADDR_REG 0x18 /* Slave Device Address */ 134 #define I2CD_POOL_CTRL_REG 0x1c /* Pool Buffer Control */ 135 #define I2CD_POOL_RX_COUNT(x) (((x) >> 24) & 0xff) 136 #define I2CD_POOL_RX_SIZE(x) ((((x) >> 16) & 0xff) + 1) 137 #define I2CD_POOL_TX_COUNT(x) ((((x) >> 8) & 0xff) + 1) 138 #define I2CD_POOL_OFFSET(x) (((x) & 0x3f) << 2) /* AST2400 */ 139 #define I2CD_BYTE_BUF_REG 0x20 /* Transmit/Receive Byte Buffer */ 140 #define I2CD_BYTE_BUF_TX_SHIFT 0 141 #define I2CD_BYTE_BUF_TX_MASK 0xff 142 #define I2CD_BYTE_BUF_RX_SHIFT 8 143 #define I2CD_BYTE_BUF_RX_MASK 0xff 144 #define I2CD_DMA_ADDR 0x24 /* DMA Buffer Address */ 145 #define I2CD_DMA_LEN 0x28 /* DMA Transfer Length < 4KB */ 146 147 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) 148 { 149 return bus->ctrl & I2CD_MASTER_EN; 150 } 151 152 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) 153 { 154 return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN); 155 } 156 157 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) 158 { 159 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 160 161 bus->intr_status &= bus->intr_ctrl; 162 if (bus->intr_status) { 163 bus->controller->intr_status |= 1 << bus->id; 164 qemu_irq_raise(aic->bus_get_irq(bus)); 165 } 166 } 167 168 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, 169 unsigned size) 170 { 171 AspeedI2CBus *bus = opaque; 172 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 173 174 switch (offset) { 175 case I2CD_FUN_CTRL_REG: 176 return bus->ctrl; 177 case I2CD_AC_TIMING_REG1: 178 return bus->timing[0]; 179 case I2CD_AC_TIMING_REG2: 180 return bus->timing[1]; 181 case I2CD_INTR_CTRL_REG: 182 return bus->intr_ctrl; 183 case I2CD_INTR_STS_REG: 184 return bus->intr_status; 185 case I2CD_POOL_CTRL_REG: 186 return bus->pool_ctrl; 187 case I2CD_BYTE_BUF_REG: 188 return bus->buf; 189 case I2CD_CMD_REG: 190 return bus->cmd | (i2c_bus_busy(bus->bus) << 16); 191 case I2CD_DMA_ADDR: 192 if (!aic->has_dma) { 193 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 194 return -1; 195 } 196 return bus->dma_addr; 197 case I2CD_DMA_LEN: 198 if (!aic->has_dma) { 199 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 200 return -1; 201 } 202 return bus->dma_len; 203 default: 204 qemu_log_mask(LOG_GUEST_ERROR, 205 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 206 return -1; 207 } 208 } 209 210 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) 211 { 212 bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT); 213 bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT; 214 } 215 216 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) 217 { 218 return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK; 219 } 220 221 static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data) 222 { 223 MemTxResult result; 224 AspeedI2CState *s = bus->controller; 225 226 result = address_space_read(&s->dram_as, bus->dma_addr, 227 MEMTXATTRS_UNSPECIFIED, data, 1); 228 if (result != MEMTX_OK) { 229 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n", 230 __func__, bus->dma_addr); 231 return -1; 232 } 233 234 bus->dma_addr++; 235 bus->dma_len--; 236 return 0; 237 } 238 239 static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) 240 { 241 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 242 int ret = -1; 243 int i; 244 245 if (bus->cmd & I2CD_TX_BUFF_ENABLE) { 246 for (i = pool_start; i < I2CD_POOL_TX_COUNT(bus->pool_ctrl); i++) { 247 uint8_t *pool_base = aic->bus_pool_base(bus); 248 249 ret = i2c_send(bus->bus, pool_base[i]); 250 if (ret) { 251 break; 252 } 253 } 254 bus->cmd &= ~I2CD_TX_BUFF_ENABLE; 255 } else if (bus->cmd & I2CD_TX_DMA_ENABLE) { 256 while (bus->dma_len) { 257 uint8_t data; 258 aspeed_i2c_dma_read(bus, &data); 259 ret = i2c_send(bus->bus, data); 260 if (ret) { 261 break; 262 } 263 } 264 bus->cmd &= ~I2CD_TX_DMA_ENABLE; 265 } else { 266 ret = i2c_send(bus->bus, bus->buf); 267 } 268 269 return ret; 270 } 271 272 static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) 273 { 274 AspeedI2CState *s = bus->controller; 275 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 276 uint8_t data; 277 int i; 278 279 if (bus->cmd & I2CD_RX_BUFF_ENABLE) { 280 uint8_t *pool_base = aic->bus_pool_base(bus); 281 282 for (i = 0; i < I2CD_POOL_RX_SIZE(bus->pool_ctrl); i++) { 283 pool_base[i] = i2c_recv(bus->bus); 284 } 285 286 /* Update RX count */ 287 bus->pool_ctrl &= ~(0xff << 24); 288 bus->pool_ctrl |= (i & 0xff) << 24; 289 bus->cmd &= ~I2CD_RX_BUFF_ENABLE; 290 } else if (bus->cmd & I2CD_RX_DMA_ENABLE) { 291 uint8_t data; 292 293 while (bus->dma_len) { 294 MemTxResult result; 295 296 data = i2c_recv(bus->bus); 297 result = address_space_write(&s->dram_as, bus->dma_addr, 298 MEMTXATTRS_UNSPECIFIED, &data, 1); 299 if (result != MEMTX_OK) { 300 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n", 301 __func__, bus->dma_addr); 302 return; 303 } 304 bus->dma_addr++; 305 bus->dma_len--; 306 } 307 bus->cmd &= ~I2CD_RX_DMA_ENABLE; 308 } else { 309 data = i2c_recv(bus->bus); 310 bus->buf = (data & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; 311 } 312 } 313 314 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) 315 { 316 aspeed_i2c_set_state(bus, I2CD_MRXD); 317 aspeed_i2c_bus_recv(bus); 318 bus->intr_status |= I2CD_INTR_RX_DONE; 319 if (bus->cmd & I2CD_M_S_RX_CMD_LAST) { 320 i2c_nack(bus->bus); 321 } 322 bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST); 323 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 324 } 325 326 static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) 327 { 328 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 329 330 if (bus->cmd & I2CD_TX_BUFF_ENABLE) { 331 uint8_t *pool_base = aic->bus_pool_base(bus); 332 333 return pool_base[0]; 334 } else if (bus->cmd & I2CD_TX_DMA_ENABLE) { 335 uint8_t data; 336 337 aspeed_i2c_dma_read(bus, &data); 338 return data; 339 } else { 340 return bus->buf; 341 } 342 } 343 344 static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) 345 { 346 AspeedI2CState *s = bus->controller; 347 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 348 349 if (!aic->check_sram) { 350 return true; 351 } 352 353 /* 354 * AST2500: SRAM must be enabled before using the Buffer Pool or 355 * DMA mode. 356 */ 357 if (!(s->ctrl_global & I2C_CTRL_SRAM_EN) && 358 (bus->cmd & (I2CD_RX_DMA_ENABLE | I2CD_TX_DMA_ENABLE | 359 I2CD_RX_BUFF_ENABLE | I2CD_TX_BUFF_ENABLE))) { 360 qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__); 361 return false; 362 } 363 364 return true; 365 } 366 367 /* 368 * The state machine needs some refinement. It is only used to track 369 * invalid STOP commands for the moment. 370 */ 371 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 372 { 373 uint8_t pool_start = 0; 374 375 bus->cmd &= ~0xFFFF; 376 bus->cmd |= value & 0xFFFF; 377 378 if (!aspeed_i2c_check_sram(bus)) { 379 return; 380 } 381 382 if (bus->cmd & I2CD_M_START_CMD) { 383 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? 384 I2CD_MSTARTR : I2CD_MSTART; 385 uint8_t addr; 386 387 aspeed_i2c_set_state(bus, state); 388 389 addr = aspeed_i2c_get_addr(bus); 390 391 if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), 392 extract32(addr, 0, 1))) { 393 bus->intr_status |= I2CD_INTR_TX_NAK; 394 } else { 395 bus->intr_status |= I2CD_INTR_TX_ACK; 396 } 397 398 bus->cmd &= ~I2CD_M_START_CMD; 399 400 /* 401 * The START command is also a TX command, as the slave 402 * address is sent on the bus. Drop the TX flag if nothing 403 * else needs to be sent in this sequence. 404 */ 405 if (bus->cmd & I2CD_TX_BUFF_ENABLE) { 406 if (I2CD_POOL_TX_COUNT(bus->pool_ctrl) == 1) { 407 bus->cmd &= ~I2CD_M_TX_CMD; 408 } else { 409 /* 410 * Increase the start index in the TX pool buffer to 411 * skip the address byte. 412 */ 413 pool_start++; 414 } 415 } else if (bus->cmd & I2CD_TX_DMA_ENABLE) { 416 if (bus->dma_len == 0) { 417 bus->cmd &= ~I2CD_M_TX_CMD; 418 } 419 } else { 420 bus->cmd &= ~I2CD_M_TX_CMD; 421 } 422 423 /* No slave found */ 424 if (!i2c_bus_busy(bus->bus)) { 425 return; 426 } 427 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 428 } 429 430 if (bus->cmd & I2CD_M_TX_CMD) { 431 aspeed_i2c_set_state(bus, I2CD_MTXD); 432 if (aspeed_i2c_bus_send(bus, pool_start)) { 433 bus->intr_status |= (I2CD_INTR_TX_NAK); 434 i2c_end_transfer(bus->bus); 435 } else { 436 bus->intr_status |= I2CD_INTR_TX_ACK; 437 } 438 bus->cmd &= ~I2CD_M_TX_CMD; 439 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 440 } 441 442 if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) && 443 !(bus->intr_status & I2CD_INTR_RX_DONE)) { 444 aspeed_i2c_handle_rx_cmd(bus); 445 } 446 447 if (bus->cmd & I2CD_M_STOP_CMD) { 448 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { 449 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); 450 bus->intr_status |= I2CD_INTR_ABNORMAL; 451 } else { 452 aspeed_i2c_set_state(bus, I2CD_MSTOP); 453 i2c_end_transfer(bus->bus); 454 bus->intr_status |= I2CD_INTR_NORMAL_STOP; 455 } 456 bus->cmd &= ~I2CD_M_STOP_CMD; 457 aspeed_i2c_set_state(bus, I2CD_IDLE); 458 } 459 } 460 461 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, 462 uint64_t value, unsigned size) 463 { 464 AspeedI2CBus *bus = opaque; 465 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 466 bool handle_rx; 467 468 switch (offset) { 469 case I2CD_FUN_CTRL_REG: 470 if (value & I2CD_SLAVE_EN) { 471 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 472 __func__); 473 break; 474 } 475 bus->ctrl = value & 0x0071C3FF; 476 break; 477 case I2CD_AC_TIMING_REG1: 478 bus->timing[0] = value & 0xFFFFF0F; 479 break; 480 case I2CD_AC_TIMING_REG2: 481 bus->timing[1] = value & 0x7; 482 break; 483 case I2CD_INTR_CTRL_REG: 484 bus->intr_ctrl = value & 0x7FFF; 485 break; 486 case I2CD_INTR_STS_REG: 487 handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) && 488 (value & I2CD_INTR_RX_DONE); 489 bus->intr_status &= ~(value & 0x7FFF); 490 if (!bus->intr_status) { 491 bus->controller->intr_status &= ~(1 << bus->id); 492 qemu_irq_lower(aic->bus_get_irq(bus)); 493 } 494 if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) { 495 aspeed_i2c_handle_rx_cmd(bus); 496 aspeed_i2c_bus_raise_interrupt(bus); 497 } 498 break; 499 case I2CD_DEV_ADDR_REG: 500 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 501 __func__); 502 break; 503 case I2CD_POOL_CTRL_REG: 504 bus->pool_ctrl &= ~0xffffff; 505 bus->pool_ctrl |= (value & 0xffffff); 506 break; 507 508 case I2CD_BYTE_BUF_REG: 509 bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT; 510 break; 511 case I2CD_CMD_REG: 512 if (!aspeed_i2c_bus_is_enabled(bus)) { 513 break; 514 } 515 516 if (!aspeed_i2c_bus_is_master(bus)) { 517 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 518 __func__); 519 break; 520 } 521 522 if (!aic->has_dma && 523 value & (I2CD_RX_DMA_ENABLE | I2CD_TX_DMA_ENABLE)) { 524 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 525 break; 526 } 527 528 aspeed_i2c_bus_handle_cmd(bus, value); 529 aspeed_i2c_bus_raise_interrupt(bus); 530 break; 531 case I2CD_DMA_ADDR: 532 if (!aic->has_dma) { 533 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 534 break; 535 } 536 537 bus->dma_addr = value & 0xfffffffc; 538 break; 539 540 case I2CD_DMA_LEN: 541 if (!aic->has_dma) { 542 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 543 break; 544 } 545 546 bus->dma_len = value & 0xfff; 547 if (!bus->dma_len) { 548 qemu_log_mask(LOG_UNIMP, "%s: invalid DMA length\n", __func__); 549 } 550 break; 551 552 default: 553 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 554 __func__, offset); 555 } 556 } 557 558 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, 559 unsigned size) 560 { 561 AspeedI2CState *s = opaque; 562 563 switch (offset) { 564 case I2C_CTRL_STATUS: 565 return s->intr_status; 566 case I2C_CTRL_GLOBAL: 567 return s->ctrl_global; 568 default: 569 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 570 __func__, offset); 571 break; 572 } 573 574 return -1; 575 } 576 577 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, 578 uint64_t value, unsigned size) 579 { 580 AspeedI2CState *s = opaque; 581 582 switch (offset) { 583 case I2C_CTRL_GLOBAL: 584 s->ctrl_global = value; 585 break; 586 case I2C_CTRL_STATUS: 587 default: 588 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 589 __func__, offset); 590 break; 591 } 592 } 593 594 static const MemoryRegionOps aspeed_i2c_bus_ops = { 595 .read = aspeed_i2c_bus_read, 596 .write = aspeed_i2c_bus_write, 597 .endianness = DEVICE_LITTLE_ENDIAN, 598 }; 599 600 static const MemoryRegionOps aspeed_i2c_ctrl_ops = { 601 .read = aspeed_i2c_ctrl_read, 602 .write = aspeed_i2c_ctrl_write, 603 .endianness = DEVICE_LITTLE_ENDIAN, 604 }; 605 606 static uint64_t aspeed_i2c_pool_read(void *opaque, hwaddr offset, 607 unsigned size) 608 { 609 AspeedI2CState *s = opaque; 610 uint64_t ret = 0; 611 int i; 612 613 for (i = 0; i < size; i++) { 614 ret |= (uint64_t) s->pool[offset + i] << (8 * i); 615 } 616 617 return ret; 618 } 619 620 static void aspeed_i2c_pool_write(void *opaque, hwaddr offset, 621 uint64_t value, unsigned size) 622 { 623 AspeedI2CState *s = opaque; 624 int i; 625 626 for (i = 0; i < size; i++) { 627 s->pool[offset + i] = (value >> (8 * i)) & 0xFF; 628 } 629 } 630 631 static const MemoryRegionOps aspeed_i2c_pool_ops = { 632 .read = aspeed_i2c_pool_read, 633 .write = aspeed_i2c_pool_write, 634 .endianness = DEVICE_LITTLE_ENDIAN, 635 .valid = { 636 .min_access_size = 1, 637 .max_access_size = 4, 638 }, 639 }; 640 641 static const VMStateDescription aspeed_i2c_bus_vmstate = { 642 .name = TYPE_ASPEED_I2C, 643 .version_id = 3, 644 .minimum_version_id = 3, 645 .fields = (VMStateField[]) { 646 VMSTATE_UINT8(id, AspeedI2CBus), 647 VMSTATE_UINT32(ctrl, AspeedI2CBus), 648 VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2), 649 VMSTATE_UINT32(intr_ctrl, AspeedI2CBus), 650 VMSTATE_UINT32(intr_status, AspeedI2CBus), 651 VMSTATE_UINT32(cmd, AspeedI2CBus), 652 VMSTATE_UINT32(buf, AspeedI2CBus), 653 VMSTATE_UINT32(pool_ctrl, AspeedI2CBus), 654 VMSTATE_UINT32(dma_addr, AspeedI2CBus), 655 VMSTATE_UINT32(dma_len, AspeedI2CBus), 656 VMSTATE_END_OF_LIST() 657 } 658 }; 659 660 static const VMStateDescription aspeed_i2c_vmstate = { 661 .name = TYPE_ASPEED_I2C, 662 .version_id = 2, 663 .minimum_version_id = 2, 664 .fields = (VMStateField[]) { 665 VMSTATE_UINT32(intr_status, AspeedI2CState), 666 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, 667 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, 668 AspeedI2CBus), 669 VMSTATE_UINT8_ARRAY(pool, AspeedI2CState, ASPEED_I2C_MAX_POOL_SIZE), 670 VMSTATE_END_OF_LIST() 671 } 672 }; 673 674 static void aspeed_i2c_reset(DeviceState *dev) 675 { 676 int i; 677 AspeedI2CState *s = ASPEED_I2C(dev); 678 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 679 680 s->intr_status = 0; 681 682 for (i = 0; i < aic->num_busses; i++) { 683 s->busses[i].intr_ctrl = 0; 684 s->busses[i].intr_status = 0; 685 s->busses[i].cmd = 0; 686 s->busses[i].buf = 0; 687 s->busses[i].dma_addr = 0; 688 s->busses[i].dma_len = 0; 689 i2c_end_transfer(s->busses[i].bus); 690 } 691 } 692 693 /* 694 * Address Definitions (AST2400 and AST2500) 695 * 696 * 0x000 ... 0x03F: Global Register 697 * 0x040 ... 0x07F: Device 1 698 * 0x080 ... 0x0BF: Device 2 699 * 0x0C0 ... 0x0FF: Device 3 700 * 0x100 ... 0x13F: Device 4 701 * 0x140 ... 0x17F: Device 5 702 * 0x180 ... 0x1BF: Device 6 703 * 0x1C0 ... 0x1FF: Device 7 704 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver) 705 * 0x300 ... 0x33F: Device 8 706 * 0x340 ... 0x37F: Device 9 707 * 0x380 ... 0x3BF: Device 10 708 * 0x3C0 ... 0x3FF: Device 11 709 * 0x400 ... 0x43F: Device 12 710 * 0x440 ... 0x47F: Device 13 711 * 0x480 ... 0x4BF: Device 14 712 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver) 713 */ 714 static void aspeed_i2c_realize(DeviceState *dev, Error **errp) 715 { 716 int i; 717 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 718 AspeedI2CState *s = ASPEED_I2C(dev); 719 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 720 721 sysbus_init_irq(sbd, &s->irq); 722 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, 723 "aspeed.i2c", 0x1000); 724 sysbus_init_mmio(sbd, &s->iomem); 725 726 for (i = 0; i < aic->num_busses; i++) { 727 char name[32]; 728 int offset = i < aic->gap ? 1 : 5; 729 730 sysbus_init_irq(sbd, &s->busses[i].irq); 731 snprintf(name, sizeof(name), "aspeed.i2c.%d", i); 732 s->busses[i].controller = s; 733 s->busses[i].id = i; 734 s->busses[i].bus = i2c_init_bus(dev, name); 735 memory_region_init_io(&s->busses[i].mr, OBJECT(dev), 736 &aspeed_i2c_bus_ops, &s->busses[i], name, 737 aic->reg_size); 738 memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), 739 &s->busses[i].mr); 740 } 741 742 memory_region_init_io(&s->pool_iomem, OBJECT(s), &aspeed_i2c_pool_ops, s, 743 "aspeed.i2c-pool", aic->pool_size); 744 memory_region_add_subregion(&s->iomem, aic->pool_base, &s->pool_iomem); 745 746 if (aic->has_dma) { 747 if (!s->dram_mr) { 748 error_setg(errp, TYPE_ASPEED_I2C ": 'dram' link not set"); 749 return; 750 } 751 752 address_space_init(&s->dram_as, s->dram_mr, "dma-dram"); 753 } 754 } 755 756 static Property aspeed_i2c_properties[] = { 757 DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, 758 TYPE_MEMORY_REGION, MemoryRegion *), 759 DEFINE_PROP_END_OF_LIST(), 760 }; 761 762 static void aspeed_i2c_class_init(ObjectClass *klass, void *data) 763 { 764 DeviceClass *dc = DEVICE_CLASS(klass); 765 766 dc->vmsd = &aspeed_i2c_vmstate; 767 dc->reset = aspeed_i2c_reset; 768 dc->props = aspeed_i2c_properties; 769 dc->realize = aspeed_i2c_realize; 770 dc->desc = "Aspeed I2C Controller"; 771 } 772 773 static const TypeInfo aspeed_i2c_info = { 774 .name = TYPE_ASPEED_I2C, 775 .parent = TYPE_SYS_BUS_DEVICE, 776 .instance_size = sizeof(AspeedI2CState), 777 .class_init = aspeed_i2c_class_init, 778 .class_size = sizeof(AspeedI2CClass), 779 .abstract = true, 780 }; 781 782 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) 783 { 784 return bus->controller->irq; 785 } 786 787 static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) 788 { 789 uint8_t *pool_page = 790 &bus->controller->pool[I2CD_POOL_PAGE_SEL(bus->ctrl) * 0x100]; 791 792 return &pool_page[I2CD_POOL_OFFSET(bus->pool_ctrl)]; 793 } 794 795 static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) 796 { 797 DeviceClass *dc = DEVICE_CLASS(klass); 798 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 799 800 dc->desc = "ASPEED 2400 I2C Controller"; 801 802 aic->num_busses = 14; 803 aic->reg_size = 0x40; 804 aic->gap = 7; 805 aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; 806 aic->pool_size = 0x800; 807 aic->pool_base = 0x800; 808 aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; 809 } 810 811 static const TypeInfo aspeed_2400_i2c_info = { 812 .name = TYPE_ASPEED_2400_I2C, 813 .parent = TYPE_ASPEED_I2C, 814 .class_init = aspeed_2400_i2c_class_init, 815 }; 816 817 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) 818 { 819 return bus->controller->irq; 820 } 821 822 static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) 823 { 824 return &bus->controller->pool[bus->id * 0x10]; 825 } 826 827 static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) 828 { 829 DeviceClass *dc = DEVICE_CLASS(klass); 830 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 831 832 dc->desc = "ASPEED 2500 I2C Controller"; 833 834 aic->num_busses = 14; 835 aic->reg_size = 0x40; 836 aic->gap = 7; 837 aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; 838 aic->pool_size = 0x100; 839 aic->pool_base = 0x200; 840 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 841 aic->check_sram = true; 842 aic->has_dma = true; 843 } 844 845 static const TypeInfo aspeed_2500_i2c_info = { 846 .name = TYPE_ASPEED_2500_I2C, 847 .parent = TYPE_ASPEED_I2C, 848 .class_init = aspeed_2500_i2c_class_init, 849 }; 850 851 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) 852 { 853 return bus->irq; 854 } 855 856 static uint8_t *aspeed_2600_i2c_bus_pool_base(AspeedI2CBus *bus) 857 { 858 return &bus->controller->pool[bus->id * 0x20]; 859 } 860 861 static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) 862 { 863 DeviceClass *dc = DEVICE_CLASS(klass); 864 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 865 866 dc->desc = "ASPEED 2600 I2C Controller"; 867 868 aic->num_busses = 16; 869 aic->reg_size = 0x80; 870 aic->gap = -1; /* no gap */ 871 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 872 aic->pool_size = 0x200; 873 aic->pool_base = 0xC00; 874 aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; 875 aic->has_dma = true; 876 } 877 878 static const TypeInfo aspeed_2600_i2c_info = { 879 .name = TYPE_ASPEED_2600_I2C, 880 .parent = TYPE_ASPEED_I2C, 881 .class_init = aspeed_2600_i2c_class_init, 882 }; 883 884 static void aspeed_i2c_register_types(void) 885 { 886 type_register_static(&aspeed_i2c_info); 887 type_register_static(&aspeed_2400_i2c_info); 888 type_register_static(&aspeed_2500_i2c_info); 889 type_register_static(&aspeed_2600_i2c_info); 890 } 891 892 type_init(aspeed_i2c_register_types) 893 894 895 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr) 896 { 897 AspeedI2CState *s = ASPEED_I2C(dev); 898 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 899 I2CBus *bus = NULL; 900 901 if (busnr >= 0 && busnr < aic->num_busses) { 902 bus = s->busses[busnr].bus; 903 } 904 905 return bus; 906 } 907