1 /* 2 * ARM Aspeed I2C controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "qemu/cutils.h" 25 #include "qemu/log.h" 26 #include "qemu/module.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "hw/i2c/aspeed_i2c.h" 30 #include "hw/irq.h" 31 #include "hw/qdev-properties.h" 32 #include "hw/registerfields.h" 33 #include "trace.h" 34 35 /* Enable SLAVE_ADDR_RX_MATCH always */ 36 #define R_I2CD_INTR_STS_ALWAYS_ENABLE R_I2CD_INTR_STS_SLAVE_ADDR_RX_MATCH_MASK 37 38 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) 39 { 40 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 41 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 42 uint32_t intr_ctrl_reg = aspeed_i2c_bus_intr_ctrl_offset(bus); 43 uint32_t intr_ctrl_mask = bus->regs[intr_ctrl_reg] | 44 R_I2CD_INTR_STS_ALWAYS_ENABLE; 45 bool raise_irq; 46 47 if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT)) { 48 g_autofree char *buf = g_strdup_printf("%s%s%s%s%s%s%s", 49 aspeed_i2c_bus_pkt_mode_en(bus) && 50 ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ? 51 "pktdone|" : "", 52 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_NAK) ? 53 "nak|" : "", 54 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_ACK) ? 55 "ack|" : "", 56 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE) ? 57 "done|" : "", 58 ARRAY_FIELD_EX32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH) ? 59 "slave-match|" : "", 60 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, NORMAL_STOP) ? 61 "stop|" : "", 62 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, ABNORMAL) ? 63 "abnormal" : ""); 64 65 trace_aspeed_i2c_bus_raise_interrupt(bus->regs[reg_intr_sts], buf); 66 } 67 68 raise_irq = bus->regs[reg_intr_sts] & intr_ctrl_mask ; 69 70 /* In packet mode we don't mask off INTR_STS */ 71 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { 72 bus->regs[reg_intr_sts] &= intr_ctrl_mask; 73 } 74 75 if (raise_irq) { 76 bus->controller->intr_status |= 1 << bus->id; 77 qemu_irq_raise(aic->bus_get_irq(bus)); 78 } 79 } 80 81 static inline void aspeed_i2c_bus_raise_slave_interrupt(AspeedI2CBus *bus) 82 { 83 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 84 85 if (!bus->regs[R_I2CS_INTR_STS]) { 86 return; 87 } 88 89 bus->controller->intr_status |= 1 << bus->id; 90 qemu_irq_raise(aic->bus_get_irq(bus)); 91 } 92 93 static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, 94 unsigned size) 95 { 96 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 97 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; 98 99 switch (offset) { 100 case A_I2CD_FUN_CTRL: 101 case A_I2CD_AC_TIMING1: 102 case A_I2CD_AC_TIMING2: 103 case A_I2CD_INTR_CTRL: 104 case A_I2CD_INTR_STS: 105 case A_I2CD_DEV_ADDR: 106 case A_I2CD_POOL_CTRL: 107 case A_I2CD_BYTE_BUF: 108 /* Value is already set, don't do anything. */ 109 break; 110 case A_I2CD_CMD: 111 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); 112 break; 113 case A_I2CD_DMA_ADDR: 114 if (!aic->has_dma) { 115 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 116 value = -1; 117 break; 118 } 119 120 value = extract64(bus->dma_dram_offset, 0, 32); 121 break; 122 case A_I2CD_DMA_LEN: 123 if (!aic->has_dma) { 124 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 125 value = -1; 126 } 127 break; 128 129 default: 130 qemu_log_mask(LOG_GUEST_ERROR, 131 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 132 value = -1; 133 break; 134 } 135 136 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); 137 return value; 138 } 139 140 static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, 141 unsigned size) 142 { 143 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; 144 145 switch (offset) { 146 case A_I2CC_FUN_CTRL: 147 case A_I2CC_AC_TIMING: 148 case A_I2CC_POOL_CTRL: 149 case A_I2CM_INTR_CTRL: 150 case A_I2CM_INTR_STS: 151 case A_I2CC_MS_TXRX_BYTE_BUF: 152 case A_I2CM_DMA_LEN: 153 case A_I2CM_DMA_TX_ADDR: 154 case A_I2CM_DMA_RX_ADDR: 155 case A_I2CM_DMA_LEN_STS: 156 case A_I2CC_DMA_LEN: 157 case A_I2CS_DEV_ADDR: 158 case A_I2CS_DMA_RX_ADDR: 159 case A_I2CS_DMA_LEN: 160 case A_I2CS_CMD: 161 case A_I2CS_INTR_CTRL: 162 case A_I2CS_DMA_LEN_STS: 163 /* Value is already set, don't do anything. */ 164 break; 165 case A_I2CC_DMA_ADDR: 166 value = extract64(bus->dma_dram_offset, 0, 32); 167 break; 168 case A_I2CS_INTR_STS: 169 break; 170 case A_I2CM_CMD: 171 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); 172 break; 173 default: 174 qemu_log_mask(LOG_GUEST_ERROR, 175 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 176 value = -1; 177 break; 178 } 179 180 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); 181 return value; 182 } 183 184 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, 185 unsigned size) 186 { 187 AspeedI2CBus *bus = opaque; 188 if (aspeed_i2c_is_new_mode(bus->controller)) { 189 return aspeed_i2c_bus_new_read(bus, offset, size); 190 } 191 return aspeed_i2c_bus_old_read(bus, offset, size); 192 } 193 194 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) 195 { 196 if (aspeed_i2c_is_new_mode(bus->controller)) { 197 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_STATE, 198 state); 199 } else { 200 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_CMD, TX_STATE, state); 201 } 202 } 203 204 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) 205 { 206 if (aspeed_i2c_is_new_mode(bus->controller)) { 207 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, 208 TX_STATE); 209 } 210 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, TX_STATE); 211 } 212 213 static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data) 214 { 215 MemTxResult result; 216 AspeedI2CState *s = bus->controller; 217 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 218 219 result = address_space_read(&s->dram_as, bus->dma_dram_offset, 220 MEMTXATTRS_UNSPECIFIED, data, 1); 221 if (result != MEMTX_OK) { 222 qemu_log_mask(LOG_GUEST_ERROR, 223 "%s: DRAM read failed @%" PRIx64 "\n", 224 __func__, bus->dma_dram_offset); 225 return -1; 226 } 227 228 bus->dma_dram_offset++; 229 bus->regs[reg_dma_len]--; 230 return 0; 231 } 232 233 static int aspeed_i2c_bus_send(AspeedI2CBus *bus) 234 { 235 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 236 int ret = -1; 237 int i; 238 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 239 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 240 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 241 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 242 int pool_tx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, 243 TX_COUNT) + 1; 244 245 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 246 for (i = 0; i < pool_tx_count; i++) { 247 uint8_t *pool_base = aic->bus_pool_base(bus); 248 249 trace_aspeed_i2c_bus_send("BUF", i + 1, pool_tx_count, 250 pool_base[i]); 251 ret = i2c_send(bus->bus, pool_base[i]); 252 if (ret) { 253 break; 254 } 255 } 256 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_BUFF_EN, 0); 257 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 258 /* In new mode, clear how many bytes we TXed */ 259 if (aspeed_i2c_is_new_mode(bus->controller)) { 260 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); 261 } 262 while (bus->regs[reg_dma_len]) { 263 uint8_t data; 264 aspeed_i2c_dma_read(bus, &data); 265 trace_aspeed_i2c_bus_send("DMA", bus->regs[reg_dma_len], 266 bus->regs[reg_dma_len], data); 267 ret = i2c_send(bus->bus, data); 268 if (ret) { 269 break; 270 } 271 /* In new mode, keep track of how many bytes we TXed */ 272 if (aspeed_i2c_is_new_mode(bus->controller)) { 273 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 274 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, 275 TX_LEN) + 1); 276 } 277 } 278 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); 279 } else { 280 trace_aspeed_i2c_bus_send("BYTE", 0, 1, 281 bus->regs[reg_byte_buf]); 282 ret = i2c_send(bus->bus, bus->regs[reg_byte_buf]); 283 } 284 285 return ret; 286 } 287 288 static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) 289 { 290 AspeedI2CState *s = bus->controller; 291 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 292 uint8_t data; 293 int i; 294 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 295 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 296 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 297 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 298 int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, 299 RX_SIZE) + 1; 300 301 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { 302 uint8_t *pool_base = aic->bus_pool_base(bus); 303 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, 304 BUF_ORGANIZATION)) { 305 pool_base += 16; 306 } 307 308 for (i = 0; i < pool_rx_count; i++) { 309 pool_base[i] = i2c_recv(bus->bus); 310 trace_aspeed_i2c_bus_recv("BUF", i + 1, pool_rx_count, 311 pool_base[i]); 312 } 313 314 /* Update RX count */ 315 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_pool_ctrl, RX_COUNT, i & 0xff); 316 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_BUFF_EN, 0); 317 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { 318 /* In new mode, clear how many bytes we RXed */ 319 if (aspeed_i2c_is_new_mode(bus->controller)) { 320 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); 321 } 322 323 while (bus->regs[reg_dma_len]) { 324 MemTxResult result; 325 326 data = i2c_recv(bus->bus); 327 trace_aspeed_i2c_bus_recv("DMA", bus->regs[reg_dma_len], 328 bus->regs[reg_dma_len], data); 329 330 result = address_space_write(&s->dram_as, bus->dma_dram_offset, 331 MEMTXATTRS_UNSPECIFIED, &data, 1); 332 if (result != MEMTX_OK) { 333 qemu_log_mask(LOG_GUEST_ERROR, 334 "%s: DRAM write failed @%" PRIx64 "\n", 335 __func__, bus->dma_dram_offset); 336 return; 337 } 338 339 bus->dma_dram_offset++; 340 bus->regs[reg_dma_len]--; 341 /* In new mode, keep track of how many bytes we RXed */ 342 if (aspeed_i2c_is_new_mode(bus->controller)) { 343 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 344 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, 345 RX_LEN) + 1); 346 } 347 } 348 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_DMA_EN, 0); 349 } else { 350 data = i2c_recv(bus->bus); 351 trace_aspeed_i2c_bus_recv("BYTE", 1, 1, bus->regs[reg_byte_buf]); 352 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); 353 } 354 } 355 356 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) 357 { 358 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 359 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 360 361 aspeed_i2c_set_state(bus, I2CD_MRXD); 362 aspeed_i2c_bus_recv(bus); 363 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); 364 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) { 365 i2c_nack(bus->bus); 366 } 367 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_RX_CMD, 0); 368 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_S_RX_CMD_LAST, 0); 369 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 370 } 371 372 static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) 373 { 374 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 375 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 376 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 377 378 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 379 return (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_DEV_ADDR) << 1) | 380 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD); 381 } 382 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 383 uint8_t *pool_base = aic->bus_pool_base(bus); 384 385 return pool_base[0]; 386 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 387 uint8_t data; 388 389 aspeed_i2c_dma_read(bus, &data); 390 return data; 391 } else { 392 return bus->regs[reg_byte_buf]; 393 } 394 } 395 396 static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) 397 { 398 AspeedI2CState *s = bus->controller; 399 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 400 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 401 bool dma_en = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) || 402 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) || 403 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) || 404 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN); 405 if (!aic->check_sram) { 406 return true; 407 } 408 409 /* 410 * AST2500: SRAM must be enabled before using the Buffer Pool or 411 * DMA mode. 412 */ 413 if (!FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, SRAM_EN) && dma_en) { 414 qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__); 415 return false; 416 } 417 418 return true; 419 } 420 421 static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) 422 { 423 g_autofree char *cmd_flags = NULL; 424 uint32_t count; 425 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 426 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 427 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 428 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 429 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { 430 count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) + 1; 431 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { 432 count = bus->regs[reg_dma_len]; 433 } else { /* BYTE mode */ 434 count = 1; 435 } 436 437 cmd_flags = g_strdup_printf("%s%s%s%s%s%s%s%s%s", 438 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD) ? "start|" : "", 439 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) ? "rxdma|" : "", 440 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) ? "txdma|" : "", 441 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) ? "rxbuf|" : "", 442 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN) ? "txbuf|" : "", 443 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD) ? "tx|" : "", 444 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) ? "rx|" : "", 445 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST) ? "last|" : "", 446 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD) ? "stop|" : ""); 447 448 trace_aspeed_i2c_bus_cmd(bus->regs[reg_cmd], cmd_flags, count, 449 bus->regs[reg_intr_sts]); 450 } 451 452 /* 453 * The state machine needs some refinement. It is only used to track 454 * invalid STOP commands for the moment. 455 */ 456 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 457 { 458 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 459 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 460 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 461 462 if (!aspeed_i2c_check_sram(bus)) { 463 return; 464 } 465 466 if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_CMD)) { 467 aspeed_i2c_bus_cmd_dump(bus); 468 } 469 470 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD)) { 471 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? 472 I2CD_MSTARTR : I2CD_MSTART; 473 uint8_t addr; 474 475 aspeed_i2c_set_state(bus, state); 476 477 addr = aspeed_i2c_get_addr(bus); 478 if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), 479 extract32(addr, 0, 1))) { 480 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); 481 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 482 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 483 } 484 } else { 485 /* START doesn't set TX_ACK in packet mode */ 486 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { 487 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); 488 } 489 } 490 491 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_START_CMD, 0); 492 493 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 494 if (bus->regs[reg_dma_len] == 0) { 495 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 496 } 497 } else if (!SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 498 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 499 } 500 501 /* No slave found */ 502 if (!i2c_bus_busy(bus->bus)) { 503 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 504 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 505 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); 506 } 507 return; 508 } 509 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 510 } 511 512 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD)) { 513 aspeed_i2c_set_state(bus, I2CD_MTXD); 514 if (aspeed_i2c_bus_send(bus)) { 515 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); 516 i2c_end_transfer(bus->bus); 517 } else { 518 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); 519 } 520 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 521 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 522 } 523 524 if ((SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) || 525 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) && 526 !SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE)) { 527 aspeed_i2c_handle_rx_cmd(bus); 528 } 529 530 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD)) { 531 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { 532 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); 533 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, ABNORMAL, 1); 534 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 535 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 536 } 537 } else { 538 aspeed_i2c_set_state(bus, I2CD_MSTOP); 539 i2c_end_transfer(bus->bus); 540 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); 541 } 542 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0); 543 aspeed_i2c_set_state(bus, I2CD_IDLE); 544 545 i2c_schedule_pending_master(bus->bus); 546 } 547 548 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 549 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); 550 } 551 } 552 553 static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset, 554 uint64_t value, unsigned size) 555 { 556 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 557 bool handle_rx; 558 bool w1t; 559 560 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); 561 562 switch (offset) { 563 case A_I2CC_FUN_CTRL: 564 bus->regs[R_I2CC_FUN_CTRL] = value; 565 break; 566 case A_I2CC_AC_TIMING: 567 bus->regs[R_I2CC_AC_TIMING] = value & 0x1ffff0ff; 568 break; 569 case A_I2CC_MS_TXRX_BYTE_BUF: 570 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_BUF, 571 value); 572 break; 573 case A_I2CC_POOL_CTRL: 574 bus->regs[R_I2CC_POOL_CTRL] &= ~0xffffff; 575 bus->regs[R_I2CC_POOL_CTRL] |= (value & 0xffffff); 576 break; 577 case A_I2CM_INTR_CTRL: 578 bus->regs[R_I2CM_INTR_CTRL] = value & 0x0007f07f; 579 break; 580 case A_I2CM_INTR_STS: 581 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_INTR_STS, RX_DONE) 582 && SHARED_FIELD_EX32(value, RX_DONE); 583 584 /* In packet mode, clearing PKT_CMD_DONE clears other interrupts. */ 585 if (aspeed_i2c_bus_pkt_mode_en(bus) && 586 FIELD_EX32(value, I2CM_INTR_STS, PKT_CMD_DONE)) { 587 bus->regs[R_I2CM_INTR_STS] &= 0xf0001000; 588 if (!bus->regs[R_I2CM_INTR_STS]) { 589 bus->controller->intr_status &= ~(1 << bus->id); 590 qemu_irq_lower(aic->bus_get_irq(bus)); 591 } 592 aspeed_i2c_bus_raise_slave_interrupt(bus); 593 break; 594 } 595 bus->regs[R_I2CM_INTR_STS] &= ~(value & 0xf007f07f); 596 if (!bus->regs[R_I2CM_INTR_STS]) { 597 bus->controller->intr_status &= ~(1 << bus->id); 598 qemu_irq_lower(aic->bus_get_irq(bus)); 599 } 600 if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, 601 M_RX_CMD) || 602 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, 603 M_S_RX_CMD_LAST))) { 604 aspeed_i2c_handle_rx_cmd(bus); 605 aspeed_i2c_bus_raise_interrupt(bus); 606 } 607 break; 608 case A_I2CM_CMD: 609 if (!aspeed_i2c_bus_is_enabled(bus)) { 610 break; 611 } 612 613 if (!aspeed_i2c_bus_is_master(bus)) { 614 qemu_log_mask(LOG_GUEST_ERROR, "%s: Master mode is not enabled\n", 615 __func__); 616 break; 617 } 618 619 if (!aic->has_dma && 620 (SHARED_FIELD_EX32(value, RX_DMA_EN) || 621 SHARED_FIELD_EX32(value, TX_DMA_EN))) { 622 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 623 break; 624 } 625 626 if (bus->regs[R_I2CM_INTR_STS] & 0xffff0000) { 627 qemu_log_mask(LOG_UNIMP, "%s: Packet mode is not implemented\n", 628 __func__); 629 break; 630 } 631 632 value &= 0xff0ffbfb; 633 if (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, W1_CTRL)) { 634 bus->regs[R_I2CM_CMD] |= value; 635 } else { 636 bus->regs[R_I2CM_CMD] = value; 637 } 638 639 aspeed_i2c_bus_handle_cmd(bus, value); 640 aspeed_i2c_bus_raise_interrupt(bus); 641 break; 642 case A_I2CM_DMA_TX_ADDR: 643 bus->regs[R_I2CM_DMA_TX_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR, 644 ADDR); 645 bus->dma_dram_offset = 646 deposit64(bus->dma_dram_offset, 0, 32, 647 FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR)); 648 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, 649 TX_BUF_LEN) + 1; 650 break; 651 case A_I2CM_DMA_RX_ADDR: 652 bus->regs[R_I2CM_DMA_RX_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR, 653 ADDR); 654 bus->dma_dram_offset = 655 deposit64(bus->dma_dram_offset, 0, 32, 656 FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR)); 657 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, 658 RX_BUF_LEN) + 1; 659 break; 660 case A_I2CM_DMA_LEN: 661 w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) || 662 FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T); 663 /* If none of the w1t bits are set, just write to the reg as normal. */ 664 if (!w1t) { 665 bus->regs[R_I2CM_DMA_LEN] = value; 666 break; 667 } 668 if (FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) { 669 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN, 670 FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN)); 671 } 672 if (FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) { 673 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN, 674 FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN)); 675 } 676 break; 677 case A_I2CM_DMA_LEN_STS: 678 /* Writes clear to 0 */ 679 bus->regs[R_I2CM_DMA_LEN_STS] = 0; 680 break; 681 case A_I2CC_DMA_ADDR: 682 case A_I2CC_DMA_LEN: 683 /* RO */ 684 break; 685 case A_I2CS_DEV_ADDR: 686 bus->regs[R_I2CS_DEV_ADDR] = value; 687 break; 688 case A_I2CS_DMA_RX_ADDR: 689 bus->regs[R_I2CS_DMA_RX_ADDR] = value; 690 break; 691 case A_I2CS_DMA_LEN: 692 assert(FIELD_EX32(value, I2CS_DMA_LEN, TX_BUF_LEN) == 0); 693 if (FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN_W1T)) { 694 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN, 695 FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN)); 696 } else { 697 bus->regs[R_I2CS_DMA_LEN] = value; 698 } 699 break; 700 case A_I2CS_CMD: 701 if (FIELD_EX32(value, I2CS_CMD, W1_CTRL)) { 702 bus->regs[R_I2CS_CMD] |= value; 703 } else { 704 bus->regs[R_I2CS_CMD] = value; 705 } 706 i2c_slave_set_address(bus->slave, bus->regs[R_I2CS_DEV_ADDR]); 707 break; 708 case A_I2CS_INTR_CTRL: 709 bus->regs[R_I2CS_INTR_CTRL] = value; 710 break; 711 712 case A_I2CS_INTR_STS: 713 if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_CTRL, PKT_CMD_DONE)) { 714 if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE) && 715 FIELD_EX32(value, I2CS_INTR_STS, PKT_CMD_DONE)) { 716 bus->regs[R_I2CS_INTR_STS] &= 0xfffc0000; 717 } 718 } else { 719 bus->regs[R_I2CS_INTR_STS] &= ~value; 720 } 721 if (!bus->regs[R_I2CS_INTR_STS]) { 722 bus->controller->intr_status &= ~(1 << bus->id); 723 qemu_irq_lower(aic->bus_get_irq(bus)); 724 } 725 aspeed_i2c_bus_raise_interrupt(bus); 726 break; 727 case A_I2CS_DMA_LEN_STS: 728 bus->regs[R_I2CS_DMA_LEN_STS] = 0; 729 break; 730 case A_I2CS_DMA_TX_ADDR: 731 qemu_log_mask(LOG_UNIMP, "%s: Slave mode DMA TX is not implemented\n", 732 __func__); 733 break; 734 default: 735 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 736 __func__, offset); 737 } 738 } 739 740 static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset, 741 uint64_t value, unsigned size) 742 { 743 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 744 bool handle_rx; 745 746 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); 747 748 switch (offset) { 749 case A_I2CD_FUN_CTRL: 750 if (SHARED_FIELD_EX32(value, SLAVE_EN)) { 751 i2c_slave_set_address(bus->slave, bus->regs[R_I2CD_DEV_ADDR]); 752 } 753 bus->regs[R_I2CD_FUN_CTRL] = value & 0x0071C3FF; 754 break; 755 case A_I2CD_AC_TIMING1: 756 bus->regs[R_I2CD_AC_TIMING1] = value & 0xFFFFF0F; 757 break; 758 case A_I2CD_AC_TIMING2: 759 bus->regs[R_I2CD_AC_TIMING2] = value & 0x7; 760 break; 761 case A_I2CD_INTR_CTRL: 762 bus->regs[R_I2CD_INTR_CTRL] = value & 0x7FFF; 763 break; 764 case A_I2CD_INTR_STS: 765 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_INTR_STS, RX_DONE) 766 && SHARED_FIELD_EX32(value, RX_DONE); 767 bus->regs[R_I2CD_INTR_STS] &= ~(value & 0x7FFF); 768 if (!bus->regs[R_I2CD_INTR_STS]) { 769 bus->controller->intr_status &= ~(1 << bus->id); 770 qemu_irq_lower(aic->bus_get_irq(bus)); 771 } 772 if (handle_rx) { 773 if (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, M_RX_CMD) || 774 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, 775 M_S_RX_CMD_LAST)) { 776 aspeed_i2c_handle_rx_cmd(bus); 777 aspeed_i2c_bus_raise_interrupt(bus); 778 } else if (aspeed_i2c_get_state(bus) == I2CD_STXD) { 779 i2c_ack(bus->bus); 780 } 781 } 782 break; 783 case A_I2CD_DEV_ADDR: 784 bus->regs[R_I2CD_DEV_ADDR] = value; 785 break; 786 case A_I2CD_POOL_CTRL: 787 bus->regs[R_I2CD_POOL_CTRL] &= ~0xffffff; 788 bus->regs[R_I2CD_POOL_CTRL] |= (value & 0xffffff); 789 break; 790 791 case A_I2CD_BYTE_BUF: 792 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_BYTE_BUF, TX_BUF, value); 793 break; 794 case A_I2CD_CMD: 795 if (!aspeed_i2c_bus_is_enabled(bus)) { 796 break; 797 } 798 799 if (!aspeed_i2c_bus_is_master(bus)) { 800 qemu_log_mask(LOG_GUEST_ERROR, "%s: Master mode is not enabled\n", 801 __func__); 802 break; 803 } 804 805 if (!aic->has_dma && 806 (SHARED_FIELD_EX32(value, RX_DMA_EN) || 807 SHARED_FIELD_EX32(value, TX_DMA_EN))) { 808 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 809 break; 810 } 811 812 bus->regs[R_I2CD_CMD] &= ~0xFFFF; 813 bus->regs[R_I2CD_CMD] |= value & 0xFFFF; 814 815 aspeed_i2c_bus_handle_cmd(bus, value); 816 aspeed_i2c_bus_raise_interrupt(bus); 817 break; 818 case A_I2CD_DMA_ADDR: 819 if (!aic->has_dma) { 820 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 821 break; 822 } 823 824 bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32, 825 value & 0x3ffffffc); 826 break; 827 828 case A_I2CD_DMA_LEN: 829 if (!aic->has_dma) { 830 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 831 break; 832 } 833 834 bus->regs[R_I2CD_DMA_LEN] = value & 0xfff; 835 if (!bus->regs[R_I2CD_DMA_LEN]) { 836 qemu_log_mask(LOG_UNIMP, "%s: invalid DMA length\n", __func__); 837 } 838 break; 839 840 default: 841 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 842 __func__, offset); 843 } 844 } 845 846 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, 847 uint64_t value, unsigned size) 848 { 849 AspeedI2CBus *bus = opaque; 850 if (aspeed_i2c_is_new_mode(bus->controller)) { 851 aspeed_i2c_bus_new_write(bus, offset, value, size); 852 } else { 853 aspeed_i2c_bus_old_write(bus, offset, value, size); 854 } 855 } 856 857 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, 858 unsigned size) 859 { 860 AspeedI2CState *s = opaque; 861 862 switch (offset) { 863 case A_I2C_CTRL_STATUS: 864 return s->intr_status; 865 case A_I2C_CTRL_GLOBAL: 866 return s->ctrl_global; 867 case A_I2C_CTRL_NEW_CLK_DIVIDER: 868 if (aspeed_i2c_is_new_mode(s)) { 869 return s->new_clk_divider; 870 } 871 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 872 __func__, offset); 873 break; 874 default: 875 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 876 __func__, offset); 877 break; 878 } 879 880 return -1; 881 } 882 883 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, 884 uint64_t value, unsigned size) 885 { 886 AspeedI2CState *s = opaque; 887 888 switch (offset) { 889 case A_I2C_CTRL_GLOBAL: 890 s->ctrl_global = value; 891 break; 892 case A_I2C_CTRL_NEW_CLK_DIVIDER: 893 if (aspeed_i2c_is_new_mode(s)) { 894 s->new_clk_divider = value; 895 } else { 896 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx 897 "\n", __func__, offset); 898 } 899 break; 900 case A_I2C_CTRL_STATUS: 901 default: 902 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 903 __func__, offset); 904 break; 905 } 906 } 907 908 static const MemoryRegionOps aspeed_i2c_bus_ops = { 909 .read = aspeed_i2c_bus_read, 910 .write = aspeed_i2c_bus_write, 911 .endianness = DEVICE_LITTLE_ENDIAN, 912 }; 913 914 static const MemoryRegionOps aspeed_i2c_ctrl_ops = { 915 .read = aspeed_i2c_ctrl_read, 916 .write = aspeed_i2c_ctrl_write, 917 .endianness = DEVICE_LITTLE_ENDIAN, 918 }; 919 920 static uint64_t aspeed_i2c_share_pool_read(void *opaque, hwaddr offset, 921 unsigned size) 922 { 923 AspeedI2CState *s = opaque; 924 uint64_t ret = 0; 925 int i; 926 927 for (i = 0; i < size; i++) { 928 ret |= (uint64_t) s->share_pool[offset + i] << (8 * i); 929 } 930 931 return ret; 932 } 933 934 static void aspeed_i2c_share_pool_write(void *opaque, hwaddr offset, 935 uint64_t value, unsigned size) 936 { 937 AspeedI2CState *s = opaque; 938 int i; 939 940 for (i = 0; i < size; i++) { 941 s->share_pool[offset + i] = (value >> (8 * i)) & 0xFF; 942 } 943 } 944 945 static const MemoryRegionOps aspeed_i2c_share_pool_ops = { 946 .read = aspeed_i2c_share_pool_read, 947 .write = aspeed_i2c_share_pool_write, 948 .endianness = DEVICE_LITTLE_ENDIAN, 949 .valid = { 950 .min_access_size = 1, 951 .max_access_size = 4, 952 }, 953 }; 954 955 static uint64_t aspeed_i2c_bus_pool_read(void *opaque, hwaddr offset, 956 unsigned size) 957 { 958 AspeedI2CBus *s = opaque; 959 uint64_t ret = 0; 960 int i; 961 962 for (i = 0; i < size; i++) { 963 ret |= (uint64_t) s->pool[offset + i] << (8 * i); 964 } 965 966 return ret; 967 } 968 969 static void aspeed_i2c_bus_pool_write(void *opaque, hwaddr offset, 970 uint64_t value, unsigned size) 971 { 972 AspeedI2CBus *s = opaque; 973 int i; 974 975 for (i = 0; i < size; i++) { 976 s->pool[offset + i] = (value >> (8 * i)) & 0xFF; 977 } 978 } 979 980 static const MemoryRegionOps aspeed_i2c_bus_pool_ops = { 981 .read = aspeed_i2c_bus_pool_read, 982 .write = aspeed_i2c_bus_pool_write, 983 .endianness = DEVICE_LITTLE_ENDIAN, 984 .valid = { 985 .min_access_size = 1, 986 .max_access_size = 4, 987 }, 988 }; 989 990 static const VMStateDescription aspeed_i2c_bus_vmstate = { 991 .name = TYPE_ASPEED_I2C, 992 .version_id = 6, 993 .minimum_version_id = 6, 994 .fields = (const VMStateField[]) { 995 VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus, ASPEED_I2C_NEW_NUM_REG), 996 VMSTATE_UINT8_ARRAY(pool, AspeedI2CBus, ASPEED_I2C_BUS_POOL_SIZE), 997 VMSTATE_UINT64(dma_dram_offset, AspeedI2CBus), 998 VMSTATE_END_OF_LIST() 999 } 1000 }; 1001 1002 static const VMStateDescription aspeed_i2c_vmstate = { 1003 .name = TYPE_ASPEED_I2C, 1004 .version_id = 3, 1005 .minimum_version_id = 3, 1006 .fields = (const VMStateField[]) { 1007 VMSTATE_UINT32(intr_status, AspeedI2CState), 1008 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, 1009 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, 1010 AspeedI2CBus), 1011 VMSTATE_UINT8_ARRAY(share_pool, AspeedI2CState, 1012 ASPEED_I2C_SHARE_POOL_SIZE), 1013 VMSTATE_END_OF_LIST() 1014 } 1015 }; 1016 1017 static void aspeed_i2c_reset(DeviceState *dev) 1018 { 1019 AspeedI2CState *s = ASPEED_I2C(dev); 1020 1021 s->intr_status = 0; 1022 } 1023 1024 static void aspeed_i2c_instance_init(Object *obj) 1025 { 1026 AspeedI2CState *s = ASPEED_I2C(obj); 1027 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 1028 int i; 1029 1030 for (i = 0; i < aic->num_busses; i++) { 1031 object_initialize_child(obj, "bus[*]", &s->busses[i], 1032 TYPE_ASPEED_I2C_BUS); 1033 } 1034 } 1035 1036 /* 1037 * Address Definitions (AST2400 and AST2500) 1038 * 1039 * 0x000 ... 0x03F: Global Register 1040 * 0x040 ... 0x07F: Device 1 1041 * 0x080 ... 0x0BF: Device 2 1042 * 0x0C0 ... 0x0FF: Device 3 1043 * 0x100 ... 0x13F: Device 4 1044 * 0x140 ... 0x17F: Device 5 1045 * 0x180 ... 0x1BF: Device 6 1046 * 0x1C0 ... 0x1FF: Device 7 1047 * 0x200 ... 0x20F: Device 1 buffer (AST2500 unused in linux driver) 1048 * 0x210 ... 0x21F: Device 2 buffer 1049 * 0x220 ... 0x22F: Device 3 buffer 1050 * 0x230 ... 0x23F: Device 4 buffer 1051 * 0x240 ... 0x24F: Device 5 buffer 1052 * 0x250 ... 0x25F: Device 6 buffer 1053 * 0x260 ... 0x26F: Device 7 buffer 1054 * 0x270 ... 0x27F: Device 8 buffer 1055 * 0x280 ... 0x28F: Device 9 buffer 1056 * 0x290 ... 0x29F: Device 10 buffer 1057 * 0x2A0 ... 0x2AF: Device 11 buffer 1058 * 0x2B0 ... 0x2BF: Device 12 buffer 1059 * 0x2C0 ... 0x2CF: Device 13 buffer 1060 * 0x2D0 ... 0x2DF: Device 14 buffer 1061 * 0x2E0 ... 0x2FF: Reserved 1062 * 0x300 ... 0x33F: Device 8 1063 * 0x340 ... 0x37F: Device 9 1064 * 0x380 ... 0x3BF: Device 10 1065 * 0x3C0 ... 0x3FF: Device 11 1066 * 0x400 ... 0x43F: Device 12 1067 * 0x440 ... 0x47F: Device 13 1068 * 0x480 ... 0x4BF: Device 14 1069 * 0x800 ... 0xFFF: Buffer Pool (AST2400 unused in linux driver) 1070 * 1071 * Address Definitions (AST2600 and AST1030) 1072 * 0x000 ... 0x07F: Global Register 1073 * 0x080 ... 0x0FF: Device 1 1074 * 0x100 ... 0x17F: Device 2 1075 * 0x180 ... 0x1FF: Device 3 1076 * 0x200 ... 0x27F: Device 4 1077 * 0x280 ... 0x2FF: Device 5 1078 * 0x300 ... 0x37F: Device 6 1079 * 0x380 ... 0x3FF: Device 7 1080 * 0x400 ... 0x47F: Device 8 1081 * 0x480 ... 0x4FF: Device 9 1082 * 0x500 ... 0x57F: Device 10 1083 * 0x580 ... 0x5FF: Device 11 1084 * 0x600 ... 0x67F: Device 12 1085 * 0x680 ... 0x6FF: Device 13 1086 * 0x700 ... 0x77F: Device 14 1087 * 0x780 ... 0x7FF: Device 15 (15 and 16 unused in AST1030) 1088 * 0x800 ... 0x87F: Device 16 1089 * 0xC00 ... 0xC1F: Device 1 buffer 1090 * 0xC20 ... 0xC3F: Device 2 buffer 1091 * 0xC40 ... 0xC5F: Device 3 buffer 1092 * 0xC60 ... 0xC7F: Device 4 buffer 1093 * 0xC80 ... 0xC9F: Device 5 buffer 1094 * 0xCA0 ... 0xCBF: Device 6 buffer 1095 * 0xCC0 ... 0xCDF: Device 7 buffer 1096 * 0xCE0 ... 0xCFF: Device 8 buffer 1097 * 0xD00 ... 0xD1F: Device 9 buffer 1098 * 0xD20 ... 0xD3F: Device 10 buffer 1099 * 0xD40 ... 0xD5F: Device 11 buffer 1100 * 0xD60 ... 0xD7F: Device 12 buffer 1101 * 0xD80 ... 0xD9F: Device 13 buffer 1102 * 0xDA0 ... 0xDBF: Device 14 buffer 1103 * 0xDC0 ... 0xDDF: Device 15 buffer (15 and 16 unused in AST1030) 1104 * 0xDE0 ... 0xDFF: Device 16 buffer 1105 * 1106 * Address Definitions (AST2700) 1107 * 0x000 ... 0x0FF: Global Register 1108 * 0x100 ... 0x17F: Device 0 1109 * 0x1A0 ... 0x1BF: Device 0 buffer 1110 * 0x200 ... 0x27F: Device 1 1111 * 0x2A0 ... 0x2BF: Device 1 buffer 1112 * 0x300 ... 0x37F: Device 2 1113 * 0x3A0 ... 0x3BF: Device 2 buffer 1114 * 0x400 ... 0x47F: Device 3 1115 * 0x4A0 ... 0x4BF: Device 3 buffer 1116 * 0x500 ... 0x57F: Device 4 1117 * 0x5A0 ... 0x5BF: Device 4 buffer 1118 * 0x600 ... 0x67F: Device 5 1119 * 0x6A0 ... 0x6BF: Device 5 buffer 1120 * 0x700 ... 0x77F: Device 6 1121 * 0x7A0 ... 0x7BF: Device 6 buffer 1122 * 0x800 ... 0x87F: Device 7 1123 * 0x8A0 ... 0x8BF: Device 7 buffer 1124 * 0x900 ... 0x97F: Device 8 1125 * 0x9A0 ... 0x9BF: Device 8 buffer 1126 * 0xA00 ... 0xA7F: Device 9 1127 * 0xAA0 ... 0xABF: Device 9 buffer 1128 * 0xB00 ... 0xB7F: Device 10 1129 * 0xBA0 ... 0xBBF: Device 10 buffer 1130 * 0xC00 ... 0xC7F: Device 11 1131 * 0xCA0 ... 0xCBF: Device 11 buffer 1132 * 0xD00 ... 0xD7F: Device 12 1133 * 0xDA0 ... 0xDBF: Device 12 buffer 1134 * 0xE00 ... 0xE7F: Device 13 1135 * 0xEA0 ... 0xEBF: Device 13 buffer 1136 * 0xF00 ... 0xF7F: Device 14 1137 * 0xFA0 ... 0xFBF: Device 14 buffer 1138 * 0x1000 ... 0x107F: Device 15 1139 * 0x10A0 ... 0x10BF: Device 15 buffer 1140 */ 1141 static void aspeed_i2c_realize(DeviceState *dev, Error **errp) 1142 { 1143 int i; 1144 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1145 AspeedI2CState *s = ASPEED_I2C(dev); 1146 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 1147 uint32_t reg_offset = aic->reg_size + aic->reg_gap_size; 1148 uint32_t pool_offset = aic->pool_size + aic->pool_gap_size; 1149 1150 sysbus_init_irq(sbd, &s->irq); 1151 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, 1152 "aspeed.i2c", aic->mem_size); 1153 sysbus_init_mmio(sbd, &s->iomem); 1154 1155 for (i = 0; i < aic->num_busses; i++) { 1156 Object *bus = OBJECT(&s->busses[i]); 1157 int offset = i < aic->gap ? 1 : 5; 1158 1159 if (!object_property_set_link(bus, "controller", OBJECT(s), errp)) { 1160 return; 1161 } 1162 1163 if (!object_property_set_uint(bus, "bus-id", i, errp)) { 1164 return; 1165 } 1166 1167 if (!sysbus_realize(SYS_BUS_DEVICE(bus), errp)) { 1168 return; 1169 } 1170 1171 memory_region_add_subregion(&s->iomem, reg_offset * (i + offset), 1172 &s->busses[i].mr); 1173 } 1174 1175 if (aic->has_share_pool) { 1176 memory_region_init_io(&s->pool_iomem, OBJECT(s), 1177 &aspeed_i2c_share_pool_ops, s, 1178 "aspeed.i2c-share-pool", aic->pool_size); 1179 memory_region_add_subregion(&s->iomem, aic->pool_base, 1180 &s->pool_iomem); 1181 } else { 1182 for (i = 0; i < aic->num_busses; i++) { 1183 memory_region_add_subregion(&s->iomem, 1184 aic->pool_base + (pool_offset * i), 1185 &s->busses[i].mr_pool); 1186 } 1187 } 1188 1189 if (aic->has_dma) { 1190 if (!s->dram_mr) { 1191 error_setg(errp, TYPE_ASPEED_I2C ": 'dram' link not set"); 1192 return; 1193 } 1194 1195 address_space_init(&s->dram_as, s->dram_mr, 1196 TYPE_ASPEED_I2C "-dma-dram"); 1197 } 1198 } 1199 1200 static Property aspeed_i2c_properties[] = { 1201 DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, 1202 TYPE_MEMORY_REGION, MemoryRegion *), 1203 DEFINE_PROP_END_OF_LIST(), 1204 }; 1205 1206 static void aspeed_i2c_class_init(ObjectClass *klass, void *data) 1207 { 1208 DeviceClass *dc = DEVICE_CLASS(klass); 1209 1210 dc->vmsd = &aspeed_i2c_vmstate; 1211 device_class_set_legacy_reset(dc, aspeed_i2c_reset); 1212 device_class_set_props(dc, aspeed_i2c_properties); 1213 dc->realize = aspeed_i2c_realize; 1214 dc->desc = "Aspeed I2C Controller"; 1215 } 1216 1217 static const TypeInfo aspeed_i2c_info = { 1218 .name = TYPE_ASPEED_I2C, 1219 .parent = TYPE_SYS_BUS_DEVICE, 1220 .instance_init = aspeed_i2c_instance_init, 1221 .instance_size = sizeof(AspeedI2CState), 1222 .class_init = aspeed_i2c_class_init, 1223 .class_size = sizeof(AspeedI2CClass), 1224 .abstract = true, 1225 }; 1226 1227 static int aspeed_i2c_bus_new_slave_event(AspeedI2CBus *bus, 1228 enum i2c_event event) 1229 { 1230 switch (event) { 1231 case I2C_START_SEND_ASYNC: 1232 if (!SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CS_CMD, RX_DMA_EN)) { 1233 qemu_log_mask(LOG_GUEST_ERROR, 1234 "%s: Slave mode RX DMA is not enabled\n", __func__); 1235 return -1; 1236 } 1237 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 0); 1238 bus->dma_dram_offset = 1239 deposit64(bus->dma_dram_offset, 0, 32, 1240 ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_RX_ADDR, ADDR)); 1241 bus->regs[R_I2CC_DMA_LEN] = 1242 ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN) + 1; 1243 i2c_ack(bus->bus); 1244 break; 1245 case I2C_FINISH: 1246 ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE, 1); 1247 ARRAY_FIELD_DP32(bus->regs, I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 1); 1248 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, NORMAL_STOP, 1); 1249 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CS_INTR_STS, RX_DONE, 1); 1250 aspeed_i2c_bus_raise_slave_interrupt(bus); 1251 break; 1252 default: 1253 qemu_log_mask(LOG_UNIMP, "%s: i2c event %d unimplemented\n", 1254 __func__, event); 1255 return -1; 1256 } 1257 1258 return 0; 1259 } 1260 1261 static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event) 1262 { 1263 BusState *qbus = qdev_get_parent_bus(DEVICE(slave)); 1264 AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent); 1265 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 1266 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 1267 uint32_t reg_dev_addr = aspeed_i2c_bus_dev_addr_offset(bus); 1268 uint32_t dev_addr = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_dev_addr, 1269 SLAVE_DEV_ADDR1); 1270 1271 if (aspeed_i2c_is_new_mode(bus->controller)) { 1272 return aspeed_i2c_bus_new_slave_event(bus, event); 1273 } 1274 1275 switch (event) { 1276 case I2C_START_SEND_ASYNC: 1277 /* Bit[0] == 0 indicates "send". */ 1278 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, dev_addr << 1); 1279 1280 ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1); 1281 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); 1282 1283 aspeed_i2c_set_state(bus, I2CD_STXD); 1284 1285 break; 1286 1287 case I2C_FINISH: 1288 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); 1289 1290 aspeed_i2c_set_state(bus, I2CD_IDLE); 1291 1292 break; 1293 1294 default: 1295 return -1; 1296 } 1297 1298 aspeed_i2c_bus_raise_interrupt(bus); 1299 1300 return 0; 1301 } 1302 1303 static void aspeed_i2c_bus_new_slave_send_async(AspeedI2CBus *bus, uint8_t data) 1304 { 1305 assert(address_space_write(&bus->controller->dram_as, 1306 bus->dma_dram_offset, 1307 MEMTXATTRS_UNSPECIFIED, &data, 1) == MEMTX_OK); 1308 1309 bus->dma_dram_offset++; 1310 bus->regs[R_I2CC_DMA_LEN]--; 1311 ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 1312 ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN) + 1); 1313 i2c_ack(bus->bus); 1314 } 1315 1316 static void aspeed_i2c_bus_slave_send_async(I2CSlave *slave, uint8_t data) 1317 { 1318 BusState *qbus = qdev_get_parent_bus(DEVICE(slave)); 1319 AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent); 1320 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 1321 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 1322 1323 if (aspeed_i2c_is_new_mode(bus->controller)) { 1324 return aspeed_i2c_bus_new_slave_send_async(bus, data); 1325 } 1326 1327 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); 1328 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); 1329 1330 aspeed_i2c_bus_raise_interrupt(bus); 1331 } 1332 1333 static void aspeed_i2c_bus_slave_class_init(ObjectClass *klass, void *data) 1334 { 1335 DeviceClass *dc = DEVICE_CLASS(klass); 1336 I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass); 1337 1338 dc->desc = "Aspeed I2C Bus Slave"; 1339 1340 sc->event = aspeed_i2c_bus_slave_event; 1341 sc->send_async = aspeed_i2c_bus_slave_send_async; 1342 } 1343 1344 static const TypeInfo aspeed_i2c_bus_slave_info = { 1345 .name = TYPE_ASPEED_I2C_BUS_SLAVE, 1346 .parent = TYPE_I2C_SLAVE, 1347 .instance_size = sizeof(AspeedI2CBusSlave), 1348 .class_init = aspeed_i2c_bus_slave_class_init, 1349 }; 1350 1351 static void aspeed_i2c_bus_reset(DeviceState *dev) 1352 { 1353 AspeedI2CBus *s = ASPEED_I2C_BUS(dev); 1354 1355 memset(s->regs, 0, sizeof(s->regs)); 1356 i2c_end_transfer(s->bus); 1357 } 1358 1359 static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp) 1360 { 1361 AspeedI2CBus *s = ASPEED_I2C_BUS(dev); 1362 AspeedI2CClass *aic; 1363 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id); 1364 g_autofree char *pool_name = g_strdup_printf("%s.pool", name); 1365 1366 if (!s->controller) { 1367 error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set"); 1368 return; 1369 } 1370 1371 aic = ASPEED_I2C_GET_CLASS(s->controller); 1372 1373 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 1374 1375 s->bus = i2c_init_bus(dev, name); 1376 s->slave = i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE, 1377 0xff); 1378 1379 memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops, 1380 s, name, aic->reg_size); 1381 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); 1382 1383 memory_region_init_io(&s->mr_pool, OBJECT(s), &aspeed_i2c_bus_pool_ops, 1384 s, pool_name, aic->pool_size); 1385 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr_pool); 1386 } 1387 1388 static Property aspeed_i2c_bus_properties[] = { 1389 DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0), 1390 DEFINE_PROP_LINK("controller", AspeedI2CBus, controller, TYPE_ASPEED_I2C, 1391 AspeedI2CState *), 1392 DEFINE_PROP_END_OF_LIST(), 1393 }; 1394 1395 static void aspeed_i2c_bus_class_init(ObjectClass *klass, void *data) 1396 { 1397 DeviceClass *dc = DEVICE_CLASS(klass); 1398 1399 dc->desc = "Aspeed I2C Bus"; 1400 dc->realize = aspeed_i2c_bus_realize; 1401 device_class_set_legacy_reset(dc, aspeed_i2c_bus_reset); 1402 device_class_set_props(dc, aspeed_i2c_bus_properties); 1403 } 1404 1405 static const TypeInfo aspeed_i2c_bus_info = { 1406 .name = TYPE_ASPEED_I2C_BUS, 1407 .parent = TYPE_SYS_BUS_DEVICE, 1408 .instance_size = sizeof(AspeedI2CBus), 1409 .class_init = aspeed_i2c_bus_class_init, 1410 }; 1411 1412 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) 1413 { 1414 return bus->controller->irq; 1415 } 1416 1417 static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) 1418 { 1419 uint8_t *pool_page = 1420 &bus->controller->share_pool[ARRAY_FIELD_EX32(bus->regs, 1421 I2CD_FUN_CTRL, 1422 POOL_PAGE_SEL) * 0x100]; 1423 1424 return &pool_page[ARRAY_FIELD_EX32(bus->regs, I2CD_POOL_CTRL, OFFSET)]; 1425 } 1426 1427 static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) 1428 { 1429 DeviceClass *dc = DEVICE_CLASS(klass); 1430 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1431 1432 dc->desc = "ASPEED 2400 I2C Controller"; 1433 1434 aic->num_busses = 14; 1435 aic->reg_size = 0x40; 1436 aic->gap = 7; 1437 aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; 1438 aic->has_share_pool = true; 1439 aic->pool_size = 0x800; 1440 aic->pool_base = 0x800; 1441 aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; 1442 aic->mem_size = 0x1000; 1443 } 1444 1445 static const TypeInfo aspeed_2400_i2c_info = { 1446 .name = TYPE_ASPEED_2400_I2C, 1447 .parent = TYPE_ASPEED_I2C, 1448 .class_init = aspeed_2400_i2c_class_init, 1449 }; 1450 1451 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) 1452 { 1453 return bus->controller->irq; 1454 } 1455 1456 static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) 1457 { 1458 return bus->pool; 1459 } 1460 1461 static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) 1462 { 1463 DeviceClass *dc = DEVICE_CLASS(klass); 1464 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1465 1466 dc->desc = "ASPEED 2500 I2C Controller"; 1467 1468 aic->num_busses = 14; 1469 aic->reg_size = 0x40; 1470 aic->gap = 7; 1471 aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; 1472 aic->pool_size = 0x10; 1473 aic->pool_base = 0x200; 1474 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 1475 aic->check_sram = true; 1476 aic->has_dma = true; 1477 aic->mem_size = 0x1000; 1478 } 1479 1480 static const TypeInfo aspeed_2500_i2c_info = { 1481 .name = TYPE_ASPEED_2500_I2C, 1482 .parent = TYPE_ASPEED_I2C, 1483 .class_init = aspeed_2500_i2c_class_init, 1484 }; 1485 1486 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) 1487 { 1488 return bus->irq; 1489 } 1490 1491 static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) 1492 { 1493 DeviceClass *dc = DEVICE_CLASS(klass); 1494 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1495 1496 dc->desc = "ASPEED 2600 I2C Controller"; 1497 1498 aic->num_busses = 16; 1499 aic->reg_size = 0x80; 1500 aic->gap = -1; /* no gap */ 1501 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 1502 aic->pool_size = 0x20; 1503 aic->pool_base = 0xC00; 1504 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 1505 aic->has_dma = true; 1506 aic->mem_size = 0x1000; 1507 } 1508 1509 static const TypeInfo aspeed_2600_i2c_info = { 1510 .name = TYPE_ASPEED_2600_I2C, 1511 .parent = TYPE_ASPEED_I2C, 1512 .class_init = aspeed_2600_i2c_class_init, 1513 }; 1514 1515 static void aspeed_1030_i2c_class_init(ObjectClass *klass, void *data) 1516 { 1517 DeviceClass *dc = DEVICE_CLASS(klass); 1518 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1519 1520 dc->desc = "ASPEED 1030 I2C Controller"; 1521 1522 aic->num_busses = 14; 1523 aic->reg_size = 0x80; 1524 aic->gap = -1; /* no gap */ 1525 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 1526 aic->pool_size = 0x20; 1527 aic->pool_base = 0xC00; 1528 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 1529 aic->has_dma = true; 1530 aic->mem_size = 0x10000; 1531 } 1532 1533 static const TypeInfo aspeed_1030_i2c_info = { 1534 .name = TYPE_ASPEED_1030_I2C, 1535 .parent = TYPE_ASPEED_I2C, 1536 .class_init = aspeed_1030_i2c_class_init, 1537 }; 1538 1539 static void aspeed_2700_i2c_class_init(ObjectClass *klass, void *data) 1540 { 1541 DeviceClass *dc = DEVICE_CLASS(klass); 1542 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1543 1544 dc->desc = "ASPEED 2700 I2C Controller"; 1545 1546 aic->num_busses = 16; 1547 aic->reg_size = 0x80; 1548 aic->reg_gap_size = 0x80; 1549 aic->gap = -1; /* no gap */ 1550 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 1551 aic->pool_size = 0x20; 1552 aic->pool_gap_size = 0xe0; 1553 aic->pool_base = 0x1a0; 1554 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 1555 aic->has_dma = true; 1556 aic->mem_size = 0x2000; 1557 } 1558 1559 static const TypeInfo aspeed_2700_i2c_info = { 1560 .name = TYPE_ASPEED_2700_I2C, 1561 .parent = TYPE_ASPEED_I2C, 1562 .class_init = aspeed_2700_i2c_class_init, 1563 }; 1564 1565 static void aspeed_i2c_register_types(void) 1566 { 1567 type_register_static(&aspeed_i2c_bus_info); 1568 type_register_static(&aspeed_i2c_bus_slave_info); 1569 type_register_static(&aspeed_i2c_info); 1570 type_register_static(&aspeed_2400_i2c_info); 1571 type_register_static(&aspeed_2500_i2c_info); 1572 type_register_static(&aspeed_2600_i2c_info); 1573 type_register_static(&aspeed_1030_i2c_info); 1574 type_register_static(&aspeed_2700_i2c_info); 1575 } 1576 1577 type_init(aspeed_i2c_register_types) 1578 1579 1580 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr) 1581 { 1582 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 1583 I2CBus *bus = NULL; 1584 1585 if (busnr >= 0 && busnr < aic->num_busses) { 1586 bus = s->busses[busnr].bus; 1587 } 1588 1589 return bus; 1590 } 1591