1 /* 2 * ARM Aspeed I2C controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "hw/i2c/aspeed_i2c.h" 29 #include "hw/irq.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/registerfields.h" 32 #include "trace.h" 33 34 /* Tx State Machine */ 35 #define I2CD_TX_STATE_MASK 0xf 36 #define I2CD_IDLE 0x0 37 #define I2CD_MACTIVE 0x8 38 #define I2CD_MSTART 0x9 39 #define I2CD_MSTARTR 0xa 40 #define I2CD_MSTOP 0xb 41 #define I2CD_MTXD 0xc 42 #define I2CD_MRXACK 0xd 43 #define I2CD_MRXD 0xe 44 #define I2CD_MTXACK 0xf 45 #define I2CD_SWAIT 0x1 46 #define I2CD_SRXD 0x4 47 #define I2CD_STXACK 0x5 48 #define I2CD_STXD 0x6 49 #define I2CD_SRXACK 0x7 50 #define I2CD_RECOVER 0x3 51 52 /* I2C Global Register */ 53 REG32(I2C_CTRL_STATUS, 0x0) /* Device Interrupt Status */ 54 REG32(I2C_CTRL_ASSIGN, 0x8) /* Device Interrupt Target Assignment */ 55 REG32(I2C_CTRL_GLOBAL, 0xC) /* Global Control Register */ 56 FIELD(I2C_CTRL_GLOBAL, REG_MODE, 2, 1) 57 FIELD(I2C_CTRL_GLOBAL, SRAM_EN, 0, 1) 58 REG32(I2C_CTRL_NEW_CLK_DIVIDER, 0x10) /* New mode clock divider */ 59 60 /* I2C Old Mode Device (Bus) Register */ 61 REG32(I2CD_FUN_CTRL, 0x0) /* I2CD Function Control */ 62 FIELD(I2CD_FUN_CTRL, POOL_PAGE_SEL, 20, 3) /* AST2400 */ 63 SHARED_FIELD(M_SDA_LOCK_EN, 16, 1) 64 SHARED_FIELD(MULTI_MASTER_DIS, 15, 1) 65 SHARED_FIELD(M_SCL_DRIVE_EN, 14, 1) 66 SHARED_FIELD(MSB_STS, 9, 1) 67 SHARED_FIELD(SDA_DRIVE_IT_EN, 8, 1) 68 SHARED_FIELD(M_SDA_DRIVE_IT_EN, 7, 1) 69 SHARED_FIELD(M_HIGH_SPEED_EN, 6, 1) 70 SHARED_FIELD(DEF_ADDR_EN, 5, 1) 71 SHARED_FIELD(DEF_ALERT_EN, 4, 1) 72 SHARED_FIELD(DEF_ARP_EN, 3, 1) 73 SHARED_FIELD(DEF_GCALL_EN, 2, 1) 74 SHARED_FIELD(SLAVE_EN, 1, 1) 75 SHARED_FIELD(MASTER_EN, 0, 1) 76 REG32(I2CD_AC_TIMING1, 0x04) /* Clock and AC Timing Control #1 */ 77 REG32(I2CD_AC_TIMING2, 0x08) /* Clock and AC Timing Control #2 */ 78 REG32(I2CD_INTR_CTRL, 0x0C) /* I2CD Interrupt Control */ 79 REG32(I2CD_INTR_STS, 0x10) /* I2CD Interrupt Status */ 80 SHARED_FIELD(SLAVE_ADDR_MATCH, 31, 1) /* 0: addr1 1: addr2 */ 81 SHARED_FIELD(SLAVE_ADDR_RX_PENDING, 29, 1) 82 SHARED_FIELD(SLAVE_INACTIVE_TIMEOUT, 15, 1) 83 SHARED_FIELD(SDA_DL_TIMEOUT, 14, 1) 84 SHARED_FIELD(BUS_RECOVER_DONE, 13, 1) 85 SHARED_FIELD(SMBUS_ALERT, 12, 1) /* Bus [0-3] only */ 86 FIELD(I2CD_INTR_STS, SMBUS_ARP_ADDR, 11, 1) /* Removed */ 87 FIELD(I2CD_INTR_STS, SMBUS_DEV_ALERT_ADDR, 10, 1) /* Removed */ 88 FIELD(I2CD_INTR_STS, SMBUS_DEF_ADDR, 9, 1) /* Removed */ 89 FIELD(I2CD_INTR_STS, GCALL_ADDR, 8, 1) /* Removed */ 90 FIELD(I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) /* use RX_DONE */ 91 SHARED_FIELD(SCL_TIMEOUT, 6, 1) 92 SHARED_FIELD(ABNORMAL, 5, 1) 93 SHARED_FIELD(NORMAL_STOP, 4, 1) 94 SHARED_FIELD(ARBIT_LOSS, 3, 1) 95 SHARED_FIELD(RX_DONE, 2, 1) 96 SHARED_FIELD(TX_NAK, 1, 1) 97 SHARED_FIELD(TX_ACK, 0, 1) 98 REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */ 99 SHARED_FIELD(SDA_OE, 28, 1) 100 SHARED_FIELD(SDA_O, 27, 1) 101 SHARED_FIELD(SCL_OE, 26, 1) 102 SHARED_FIELD(SCL_O, 25, 1) 103 SHARED_FIELD(TX_TIMING, 23, 2) 104 SHARED_FIELD(TX_STATE, 19, 4) 105 SHARED_FIELD(SCL_LINE_STS, 18, 1) 106 SHARED_FIELD(SDA_LINE_STS, 17, 1) 107 SHARED_FIELD(BUS_BUSY_STS, 16, 1) 108 SHARED_FIELD(SDA_OE_OUT_DIR, 15, 1) 109 SHARED_FIELD(SDA_O_OUT_DIR, 14, 1) 110 SHARED_FIELD(SCL_OE_OUT_DIR, 13, 1) 111 SHARED_FIELD(SCL_O_OUT_DIR, 12, 1) 112 SHARED_FIELD(BUS_RECOVER_CMD_EN, 11, 1) 113 SHARED_FIELD(S_ALT_EN, 10, 1) 114 /* Command Bits */ 115 SHARED_FIELD(RX_DMA_EN, 9, 1) 116 SHARED_FIELD(TX_DMA_EN, 8, 1) 117 SHARED_FIELD(RX_BUFF_EN, 7, 1) 118 SHARED_FIELD(TX_BUFF_EN, 6, 1) 119 SHARED_FIELD(M_STOP_CMD, 5, 1) 120 SHARED_FIELD(M_S_RX_CMD_LAST, 4, 1) 121 SHARED_FIELD(M_RX_CMD, 3, 1) 122 SHARED_FIELD(S_TX_CMD, 2, 1) 123 SHARED_FIELD(M_TX_CMD, 1, 1) 124 SHARED_FIELD(M_START_CMD, 0, 1) 125 REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */ 126 REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */ 127 SHARED_FIELD(RX_COUNT, 24, 5) 128 SHARED_FIELD(RX_SIZE, 16, 5) 129 SHARED_FIELD(TX_COUNT, 9, 5) 130 FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */ 131 REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */ 132 SHARED_FIELD(RX_BUF, 8, 8) 133 SHARED_FIELD(TX_BUF, 0, 8) 134 REG32(I2CD_DMA_ADDR, 0x24) /* DMA Buffer Address */ 135 REG32(I2CD_DMA_LEN, 0x28) /* DMA Transfer Length < 4KB */ 136 137 /* I2C New Mode Device (Bus) Register */ 138 REG32(I2CC_FUN_CTRL, 0x0) 139 FIELD(I2CC_FUN_CTRL, RB_EARLY_DONE_EN, 22, 1) 140 FIELD(I2CC_FUN_CTRL, DMA_DIS_AUTO_RECOVER, 21, 1) 141 FIELD(I2CC_FUN_CTRL, S_SAVE_ADDR, 20, 1) 142 FIELD(I2CC_FUN_CTRL, M_PKT_RETRY_CNT, 18, 2) 143 /* 17:0 shared with I2CD_FUN_CTRL[17:0] */ 144 REG32(I2CC_AC_TIMING, 0x04) 145 REG32(I2CC_MS_TXRX_BYTE_BUF, 0x08) 146 /* 31:16 shared with I2CD_CMD[31:16] */ 147 /* 15:0 shared with I2CD_BYTE_BUF[15:0] */ 148 REG32(I2CC_POOL_CTRL, 0x0c) 149 /* 31:0 shared with I2CD_POOL_CTRL[31:0] */ 150 REG32(I2CM_INTR_CTRL, 0x10) 151 REG32(I2CM_INTR_STS, 0x14) 152 FIELD(I2CM_INTR_STS, PKT_STATE, 28, 4) 153 FIELD(I2CM_INTR_STS, PKT_CMD_TIMEOUT, 18, 1) 154 FIELD(I2CM_INTR_STS, PKT_CMD_FAIL, 17, 1) 155 FIELD(I2CM_INTR_STS, PKT_CMD_DONE, 16, 1) 156 FIELD(I2CM_INTR_STS, BUS_RECOVER_FAIL, 15, 1) 157 /* 14:0 shared with I2CD_INTR_STS[14:0] */ 158 REG32(I2CM_CMD, 0x18) 159 FIELD(I2CM_CMD, W1_CTRL, 31, 1) 160 FIELD(I2CM_CMD, PKT_DEV_ADDR, 24, 7) 161 FIELD(I2CM_CMD, HS_MASTER_MODE_LSB, 17, 3) 162 FIELD(I2CM_CMD, PKT_OP_EN, 16, 1) 163 /* 15:0 shared with I2CD_CMD[15:0] */ 164 REG32(I2CM_DMA_LEN, 0x1c) 165 FIELD(I2CM_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) 166 FIELD(I2CM_DMA_LEN, RX_BUF_LEN, 16, 11) 167 FIELD(I2CM_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) 168 FIELD(I2CM_DMA_LEN, TX_BUF_LEN, 0, 11) 169 REG32(I2CS_INTR_CTRL, 0x20) 170 REG32(I2CS_INTR_STS, 0x24) 171 /* 31:29 shared with I2CD_INTR_STS[31:29] */ 172 FIELD(I2CS_INTR_STS, SLAVE_PARKING_STS, 24, 2) 173 FIELD(I2CS_INTR_STS, SLAVE_ADDR3_NAK, 22, 1) 174 FIELD(I2CS_INTR_STS, SLAVE_ADDR2_NAK, 21, 1) 175 FIELD(I2CS_INTR_STS, SLAVE_ADDR1_NAK, 20, 1) 176 FIELD(I2CS_INTR_STS, SLAVE_ADDR_INDICATOR, 18, 2) 177 FIELD(I2CS_INTR_STS, PKT_CMD_FAIL, 17, 1) 178 FIELD(I2CS_INTR_STS, PKT_CMD_DONE, 16, 1) 179 /* 14:0 shared with I2CD_INTR_STS[14:0] */ 180 REG32(I2CS_CMD, 0x28) 181 FIELD(I2CS_CMD, W1_CTRL, 31, 1) 182 FIELD(I2CS_CMD, PKT_MODE_ACTIVE_ADDR, 17, 2) 183 FIELD(I2CS_CMD, PKT_MODE_EN, 16, 1) 184 FIELD(I2CS_CMD, AUTO_NAK_INACTIVE_ADDR, 15, 1) 185 FIELD(I2CS_CMD, AUTO_NAK_ACTIVE_ADDR, 14, 1) 186 /* 13:0 shared with I2CD_CMD[13:0] */ 187 REG32(I2CS_DMA_LEN, 0x2c) 188 FIELD(I2CS_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) 189 FIELD(I2CS_DMA_LEN, RX_BUF_LEN, 16, 11) 190 FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) 191 FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11) 192 REG32(I2CM_DMA_TX_ADDR, 0x30) 193 FIELD(I2CM_DMA_TX_ADDR, ADDR, 0, 31) 194 REG32(I2CM_DMA_RX_ADDR, 0x34) 195 FIELD(I2CM_DMA_RX_ADDR, ADDR, 0, 31) 196 REG32(I2CS_DMA_TX_ADDR, 0x38) 197 FIELD(I2CS_DMA_TX_ADDR, ADDR, 0, 31) 198 REG32(I2CS_DMA_RX_ADDR, 0x3c) 199 FIELD(I2CS_DMA_RX_ADDR, ADDR, 0, 31) 200 REG32(I2CS_DEV_ADDR, 0x40) 201 REG32(I2CM_DMA_LEN_STS, 0x48) 202 FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13) 203 FIELD(I2CM_DMA_LEN_STS, TX_LEN, 0, 13) 204 REG32(I2CS_DMA_LEN_STS, 0x4c) 205 FIELD(I2CS_DMA_LEN_STS, RX_LEN, 16, 13) 206 FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13) 207 REG32(I2CC_DMA_ADDR, 0x50) 208 REG32(I2CC_DMA_LEN, 0x54) 209 210 static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s) 211 { 212 return FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, REG_MODE); 213 } 214 215 static inline bool aspeed_i2c_bus_pkt_mode_en(AspeedI2CBus *bus) 216 { 217 if (aspeed_i2c_is_new_mode(bus->controller)) { 218 return ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_OP_EN); 219 } 220 return false; 221 } 222 223 static inline uint32_t aspeed_i2c_bus_ctrl_offset(AspeedI2CBus *bus) 224 { 225 if (aspeed_i2c_is_new_mode(bus->controller)) { 226 return R_I2CC_FUN_CTRL; 227 } 228 return R_I2CD_FUN_CTRL; 229 } 230 231 static inline uint32_t aspeed_i2c_bus_cmd_offset(AspeedI2CBus *bus) 232 { 233 if (aspeed_i2c_is_new_mode(bus->controller)) { 234 return R_I2CM_CMD; 235 } 236 return R_I2CD_CMD; 237 } 238 239 static inline uint32_t aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus *bus) 240 { 241 if (aspeed_i2c_is_new_mode(bus->controller)) { 242 return R_I2CM_INTR_CTRL; 243 } 244 return R_I2CD_INTR_CTRL; 245 } 246 247 static inline uint32_t aspeed_i2c_bus_intr_sts_offset(AspeedI2CBus *bus) 248 { 249 if (aspeed_i2c_is_new_mode(bus->controller)) { 250 return R_I2CM_INTR_STS; 251 } 252 return R_I2CD_INTR_STS; 253 } 254 255 static inline uint32_t aspeed_i2c_bus_pool_ctrl_offset(AspeedI2CBus *bus) 256 { 257 if (aspeed_i2c_is_new_mode(bus->controller)) { 258 return R_I2CC_POOL_CTRL; 259 } 260 return R_I2CD_POOL_CTRL; 261 } 262 263 static inline uint32_t aspeed_i2c_bus_byte_buf_offset(AspeedI2CBus *bus) 264 { 265 if (aspeed_i2c_is_new_mode(bus->controller)) { 266 return R_I2CC_MS_TXRX_BYTE_BUF; 267 } 268 return R_I2CD_BYTE_BUF; 269 } 270 271 static inline uint32_t aspeed_i2c_bus_dma_len_offset(AspeedI2CBus *bus) 272 { 273 if (aspeed_i2c_is_new_mode(bus->controller)) { 274 return R_I2CC_DMA_LEN; 275 } 276 return R_I2CD_DMA_LEN; 277 } 278 279 static inline uint32_t aspeed_i2c_bus_dma_addr_offset(AspeedI2CBus *bus) 280 { 281 if (aspeed_i2c_is_new_mode(bus->controller)) { 282 return R_I2CC_DMA_ADDR; 283 } 284 return R_I2CD_DMA_ADDR; 285 } 286 287 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) 288 { 289 return SHARED_ARRAY_FIELD_EX32(bus->regs, aspeed_i2c_bus_ctrl_offset(bus), 290 MASTER_EN); 291 } 292 293 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) 294 { 295 uint32_t ctrl_reg = aspeed_i2c_bus_ctrl_offset(bus); 296 return SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, MASTER_EN) || 297 SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, SLAVE_EN); 298 } 299 300 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) 301 { 302 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 303 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 304 uint32_t intr_ctrl_reg = aspeed_i2c_bus_intr_ctrl_offset(bus); 305 bool raise_irq; 306 307 trace_aspeed_i2c_bus_raise_interrupt(bus->regs[reg_intr_sts], 308 aspeed_i2c_bus_pkt_mode_en(bus) && 309 ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ? 310 "pktdone|" : "", 311 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_NAK) ? "nak|" : "", 312 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_ACK) ? "ack|" : "", 313 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE) ? "done|" 314 : "", 315 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, NORMAL_STOP) ? 316 "normal|" : "", 317 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, ABNORMAL) ? "abnormal" 318 : ""); 319 raise_irq = bus->regs[reg_intr_sts] & bus->regs[intr_ctrl_reg]; 320 /* In packet mode we don't mask off INTR_STS */ 321 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { 322 bus->regs[reg_intr_sts] &= bus->regs[intr_ctrl_reg]; 323 } 324 if (raise_irq) { 325 bus->controller->intr_status |= 1 << bus->id; 326 qemu_irq_raise(aic->bus_get_irq(bus)); 327 } 328 } 329 330 static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, 331 unsigned size) 332 { 333 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 334 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; 335 336 switch (offset) { 337 case A_I2CD_FUN_CTRL: 338 case A_I2CD_AC_TIMING1: 339 case A_I2CD_AC_TIMING2: 340 case A_I2CD_INTR_CTRL: 341 case A_I2CD_INTR_STS: 342 case A_I2CD_POOL_CTRL: 343 case A_I2CD_BYTE_BUF: 344 /* Value is already set, don't do anything. */ 345 break; 346 case A_I2CD_CMD: 347 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); 348 break; 349 case A_I2CD_DMA_ADDR: 350 if (!aic->has_dma) { 351 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 352 value = -1; 353 } 354 break; 355 case A_I2CD_DMA_LEN: 356 if (!aic->has_dma) { 357 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 358 value = -1; 359 } 360 break; 361 362 default: 363 qemu_log_mask(LOG_GUEST_ERROR, 364 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 365 value = -1; 366 break; 367 } 368 369 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); 370 return value; 371 } 372 373 static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, 374 unsigned size) 375 { 376 uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; 377 378 switch (offset) { 379 case A_I2CC_FUN_CTRL: 380 case A_I2CC_AC_TIMING: 381 case A_I2CC_POOL_CTRL: 382 case A_I2CM_INTR_CTRL: 383 case A_I2CM_INTR_STS: 384 case A_I2CC_MS_TXRX_BYTE_BUF: 385 case A_I2CM_DMA_LEN: 386 case A_I2CM_DMA_TX_ADDR: 387 case A_I2CM_DMA_RX_ADDR: 388 case A_I2CM_DMA_LEN_STS: 389 case A_I2CC_DMA_ADDR: 390 case A_I2CC_DMA_LEN: 391 /* Value is already set, don't do anything. */ 392 break; 393 case A_I2CM_CMD: 394 value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); 395 break; 396 default: 397 qemu_log_mask(LOG_GUEST_ERROR, 398 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 399 value = -1; 400 break; 401 } 402 403 trace_aspeed_i2c_bus_read(bus->id, offset, size, value); 404 return value; 405 } 406 407 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, 408 unsigned size) 409 { 410 AspeedI2CBus *bus = opaque; 411 if (aspeed_i2c_is_new_mode(bus->controller)) { 412 return aspeed_i2c_bus_new_read(bus, offset, size); 413 } 414 return aspeed_i2c_bus_old_read(bus, offset, size); 415 } 416 417 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) 418 { 419 if (aspeed_i2c_is_new_mode(bus->controller)) { 420 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_STATE, 421 state); 422 } else { 423 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_CMD, TX_STATE, state); 424 } 425 } 426 427 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) 428 { 429 if (aspeed_i2c_is_new_mode(bus->controller)) { 430 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, 431 TX_STATE); 432 } 433 return SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, TX_STATE); 434 } 435 436 static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data) 437 { 438 MemTxResult result; 439 AspeedI2CState *s = bus->controller; 440 uint32_t reg_dma_addr = aspeed_i2c_bus_dma_addr_offset(bus); 441 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 442 443 result = address_space_read(&s->dram_as, bus->regs[reg_dma_addr], 444 MEMTXATTRS_UNSPECIFIED, data, 1); 445 if (result != MEMTX_OK) { 446 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n", 447 __func__, bus->regs[reg_dma_addr]); 448 return -1; 449 } 450 451 bus->regs[reg_dma_addr]++; 452 bus->regs[reg_dma_len]--; 453 return 0; 454 } 455 456 static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) 457 { 458 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 459 int ret = -1; 460 int i; 461 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 462 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 463 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 464 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 465 int pool_tx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, 466 TX_COUNT); 467 468 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 469 for (i = pool_start; i < pool_tx_count; i++) { 470 uint8_t *pool_base = aic->bus_pool_base(bus); 471 472 trace_aspeed_i2c_bus_send("BUF", i + 1, pool_tx_count, 473 pool_base[i]); 474 ret = i2c_send(bus->bus, pool_base[i]); 475 if (ret) { 476 break; 477 } 478 } 479 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_BUFF_EN, 0); 480 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 481 /* In new mode, clear how many bytes we TXed */ 482 if (aspeed_i2c_is_new_mode(bus->controller)) { 483 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); 484 } 485 while (bus->regs[reg_dma_len]) { 486 uint8_t data; 487 aspeed_i2c_dma_read(bus, &data); 488 trace_aspeed_i2c_bus_send("DMA", bus->regs[reg_dma_len], 489 bus->regs[reg_dma_len], data); 490 ret = i2c_send(bus->bus, data); 491 if (ret) { 492 break; 493 } 494 /* In new mode, keep track of how many bytes we TXed */ 495 if (aspeed_i2c_is_new_mode(bus->controller)) { 496 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 497 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, 498 TX_LEN) + 1); 499 } 500 } 501 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); 502 } else { 503 trace_aspeed_i2c_bus_send("BYTE", pool_start, 1, 504 bus->regs[reg_byte_buf]); 505 ret = i2c_send(bus->bus, bus->regs[reg_byte_buf]); 506 } 507 508 return ret; 509 } 510 511 static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) 512 { 513 AspeedI2CState *s = bus->controller; 514 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 515 uint8_t data; 516 int i; 517 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 518 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 519 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 520 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 521 uint32_t reg_dma_addr = aspeed_i2c_bus_dma_addr_offset(bus); 522 int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, 523 RX_COUNT); 524 525 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { 526 uint8_t *pool_base = aic->bus_pool_base(bus); 527 528 for (i = 0; i < pool_rx_count; i++) { 529 pool_base[i] = i2c_recv(bus->bus); 530 trace_aspeed_i2c_bus_recv("BUF", i + 1, pool_rx_count, 531 pool_base[i]); 532 } 533 534 /* Update RX count */ 535 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_pool_ctrl, RX_COUNT, i & 0xff); 536 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_BUFF_EN, 0); 537 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { 538 uint8_t data; 539 /* In new mode, clear how many bytes we RXed */ 540 if (aspeed_i2c_is_new_mode(bus->controller)) { 541 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); 542 } 543 544 while (bus->regs[reg_dma_len]) { 545 MemTxResult result; 546 547 data = i2c_recv(bus->bus); 548 trace_aspeed_i2c_bus_recv("DMA", bus->regs[reg_dma_len], 549 bus->regs[reg_dma_len], data); 550 result = address_space_write(&s->dram_as, bus->regs[reg_dma_addr], 551 MEMTXATTRS_UNSPECIFIED, &data, 1); 552 if (result != MEMTX_OK) { 553 qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n", 554 __func__, bus->regs[reg_dma_addr]); 555 return; 556 } 557 bus->regs[reg_dma_addr]++; 558 bus->regs[reg_dma_len]--; 559 /* In new mode, keep track of how many bytes we RXed */ 560 if (aspeed_i2c_is_new_mode(bus->controller)) { 561 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 562 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, 563 RX_LEN) + 1); 564 } 565 } 566 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, RX_DMA_EN, 0); 567 } else { 568 data = i2c_recv(bus->bus); 569 trace_aspeed_i2c_bus_recv("BYTE", 1, 1, bus->regs[reg_byte_buf]); 570 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); 571 } 572 } 573 574 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) 575 { 576 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 577 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 578 579 aspeed_i2c_set_state(bus, I2CD_MRXD); 580 aspeed_i2c_bus_recv(bus); 581 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); 582 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) { 583 i2c_nack(bus->bus); 584 } 585 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_RX_CMD, 0); 586 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_S_RX_CMD_LAST, 0); 587 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 588 } 589 590 static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) 591 { 592 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 593 uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); 594 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 595 596 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 597 return (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_DEV_ADDR) << 1) | 598 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD); 599 } 600 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 601 uint8_t *pool_base = aic->bus_pool_base(bus); 602 603 return pool_base[0]; 604 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 605 uint8_t data; 606 607 aspeed_i2c_dma_read(bus, &data); 608 return data; 609 } else { 610 return bus->regs[reg_byte_buf]; 611 } 612 } 613 614 static bool aspeed_i2c_check_sram(AspeedI2CBus *bus) 615 { 616 AspeedI2CState *s = bus->controller; 617 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 618 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 619 bool dma_en = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) || 620 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) || 621 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) || 622 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN); 623 if (!aic->check_sram) { 624 return true; 625 } 626 627 /* 628 * AST2500: SRAM must be enabled before using the Buffer Pool or 629 * DMA mode. 630 */ 631 if (!FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, SRAM_EN) && dma_en) { 632 qemu_log_mask(LOG_GUEST_ERROR, "%s: SRAM is not enabled\n", __func__); 633 return false; 634 } 635 636 return true; 637 } 638 639 static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) 640 { 641 g_autofree char *cmd_flags = NULL; 642 uint32_t count; 643 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 644 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 645 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 646 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 647 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { 648 count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT); 649 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { 650 count = bus->regs[reg_dma_len]; 651 } else { /* BYTE mode */ 652 count = 1; 653 } 654 655 cmd_flags = g_strdup_printf("%s%s%s%s%s%s%s%s%s", 656 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD) ? "start|" : "", 657 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN) ? "rxdma|" : "", 658 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN) ? "txdma|" : "", 659 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN) ? "rxbuf|" : "", 660 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN) ? "txbuf|" : "", 661 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD) ? "tx|" : "", 662 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) ? "rx|" : "", 663 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST) ? "last|" : "", 664 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD) ? "stop|" : ""); 665 666 trace_aspeed_i2c_bus_cmd(bus->regs[reg_cmd], cmd_flags, count, 667 bus->regs[reg_intr_sts]); 668 } 669 670 /* 671 * The state machine needs some refinement. It is only used to track 672 * invalid STOP commands for the moment. 673 */ 674 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 675 { 676 uint8_t pool_start = 0; 677 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); 678 uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); 679 uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); 680 uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); 681 682 if (!aspeed_i2c_check_sram(bus)) { 683 return; 684 } 685 686 if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_CMD)) { 687 aspeed_i2c_bus_cmd_dump(bus); 688 } 689 690 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_START_CMD)) { 691 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? 692 I2CD_MSTARTR : I2CD_MSTART; 693 uint8_t addr; 694 695 aspeed_i2c_set_state(bus, state); 696 697 addr = aspeed_i2c_get_addr(bus); 698 if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), 699 extract32(addr, 0, 1))) { 700 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); 701 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 702 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 703 } 704 } else { 705 /* START doesn't set TX_ACK in packet mode */ 706 if (!aspeed_i2c_bus_pkt_mode_en(bus)) { 707 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); 708 } 709 } 710 711 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_START_CMD, 0); 712 713 /* 714 * The START command is also a TX command, as the slave 715 * address is sent on the bus. Drop the TX flag if nothing 716 * else needs to be sent in this sequence. 717 */ 718 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { 719 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) 720 == 1) { 721 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 722 } else { 723 /* 724 * Increase the start index in the TX pool buffer to 725 * skip the address byte. 726 */ 727 pool_start++; 728 } 729 } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { 730 if (bus->regs[reg_dma_len] == 0) { 731 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 732 } 733 } else { 734 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 735 } 736 737 /* No slave found */ 738 if (!i2c_bus_busy(bus->bus)) { 739 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 740 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 741 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); 742 } 743 return; 744 } 745 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 746 } 747 748 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD)) { 749 aspeed_i2c_set_state(bus, I2CD_MTXD); 750 if (aspeed_i2c_bus_send(bus, pool_start)) { 751 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); 752 i2c_end_transfer(bus->bus); 753 } else { 754 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_ACK, 1); 755 } 756 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); 757 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 758 } 759 760 if ((SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_RX_CMD) || 761 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_S_RX_CMD_LAST)) && 762 !SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE)) { 763 aspeed_i2c_handle_rx_cmd(bus); 764 } 765 766 if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_STOP_CMD)) { 767 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { 768 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); 769 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, ABNORMAL, 1); 770 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 771 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); 772 } 773 } else { 774 aspeed_i2c_set_state(bus, I2CD_MSTOP); 775 i2c_end_transfer(bus->bus); 776 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); 777 } 778 SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0); 779 aspeed_i2c_set_state(bus, I2CD_IDLE); 780 } 781 782 if (aspeed_i2c_bus_pkt_mode_en(bus)) { 783 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); 784 } 785 } 786 787 static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset, 788 uint64_t value, unsigned size) 789 { 790 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 791 bool handle_rx; 792 bool w1t; 793 794 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); 795 796 switch (offset) { 797 case A_I2CC_FUN_CTRL: 798 if (SHARED_FIELD_EX32(value, SLAVE_EN)) { 799 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 800 __func__); 801 break; 802 } 803 bus->regs[R_I2CD_FUN_CTRL] = value & 0x007dc3ff; 804 break; 805 case A_I2CC_AC_TIMING: 806 bus->regs[R_I2CC_AC_TIMING] = value & 0x1ffff0ff; 807 break; 808 case A_I2CC_MS_TXRX_BYTE_BUF: 809 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CC_MS_TXRX_BYTE_BUF, TX_BUF, 810 value); 811 break; 812 case A_I2CC_POOL_CTRL: 813 bus->regs[R_I2CC_POOL_CTRL] &= ~0xffffff; 814 bus->regs[R_I2CC_POOL_CTRL] |= (value & 0xffffff); 815 break; 816 case A_I2CM_INTR_CTRL: 817 bus->regs[R_I2CM_INTR_CTRL] = value & 0x0007f07f; 818 break; 819 case A_I2CM_INTR_STS: 820 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_INTR_STS, RX_DONE) 821 && SHARED_FIELD_EX32(value, RX_DONE); 822 823 /* In packet mode, clearing PKT_CMD_DONE clears other interrupts. */ 824 if (aspeed_i2c_bus_pkt_mode_en(bus) && 825 FIELD_EX32(value, I2CM_INTR_STS, PKT_CMD_DONE)) { 826 bus->regs[R_I2CM_INTR_STS] &= 0xf0001000; 827 if (!bus->regs[R_I2CM_INTR_STS]) { 828 bus->controller->intr_status &= ~(1 << bus->id); 829 qemu_irq_lower(aic->bus_get_irq(bus)); 830 } 831 break; 832 } 833 bus->regs[R_I2CM_INTR_STS] &= ~(value & 0xf007f07f); 834 if (!bus->regs[R_I2CM_INTR_STS]) { 835 bus->controller->intr_status &= ~(1 << bus->id); 836 qemu_irq_lower(aic->bus_get_irq(bus)); 837 } 838 if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, 839 M_RX_CMD) || 840 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CM_CMD, 841 M_S_RX_CMD_LAST))) { 842 aspeed_i2c_handle_rx_cmd(bus); 843 aspeed_i2c_bus_raise_interrupt(bus); 844 } 845 break; 846 case A_I2CM_CMD: 847 if (!aspeed_i2c_bus_is_enabled(bus)) { 848 break; 849 } 850 851 if (!aspeed_i2c_bus_is_master(bus)) { 852 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 853 __func__); 854 break; 855 } 856 857 if (!aic->has_dma && 858 (SHARED_FIELD_EX32(value, RX_DMA_EN) || 859 SHARED_FIELD_EX32(value, TX_DMA_EN))) { 860 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 861 break; 862 } 863 864 if (bus->regs[R_I2CM_INTR_STS] & 0xffff0000) { 865 qemu_log_mask(LOG_UNIMP, "%s: Packet mode is not implemented\n", 866 __func__); 867 break; 868 } 869 870 value &= 0xff0ffbfb; 871 if (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, W1_CTRL)) { 872 bus->regs[R_I2CM_CMD] |= value; 873 } else { 874 bus->regs[R_I2CM_CMD] = value; 875 } 876 877 aspeed_i2c_bus_handle_cmd(bus, value); 878 aspeed_i2c_bus_raise_interrupt(bus); 879 break; 880 case A_I2CM_DMA_TX_ADDR: 881 bus->regs[R_I2CM_DMA_TX_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR, 882 ADDR); 883 bus->regs[R_I2CC_DMA_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR); 884 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, 885 TX_BUF_LEN) + 1; 886 break; 887 case A_I2CM_DMA_RX_ADDR: 888 bus->regs[R_I2CM_DMA_RX_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR, 889 ADDR); 890 bus->regs[R_I2CC_DMA_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR); 891 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, 892 RX_BUF_LEN) + 1; 893 break; 894 case A_I2CM_DMA_LEN: 895 w1t = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T) || 896 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T); 897 /* If none of the w1t bits are set, just write to the reg as normal. */ 898 if (!w1t) { 899 bus->regs[R_I2CM_DMA_LEN] = value; 900 break; 901 } 902 if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) { 903 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN, 904 FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN)); 905 } 906 if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) { 907 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN, 908 FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN)); 909 } 910 break; 911 case A_I2CM_DMA_LEN_STS: 912 /* Writes clear to 0 */ 913 bus->regs[R_I2CM_DMA_LEN_STS] = 0; 914 break; 915 case A_I2CC_DMA_ADDR: 916 case A_I2CC_DMA_LEN: 917 /* RO */ 918 break; 919 case A_I2CS_DMA_LEN_STS: 920 case A_I2CS_DMA_TX_ADDR: 921 case A_I2CS_DMA_RX_ADDR: 922 case A_I2CS_DEV_ADDR: 923 case A_I2CS_INTR_CTRL: 924 case A_I2CS_INTR_STS: 925 case A_I2CS_CMD: 926 case A_I2CS_DMA_LEN: 927 qemu_log_mask(LOG_UNIMP, "%s: Slave mode is not implemented\n", 928 __func__); 929 break; 930 default: 931 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 932 __func__, offset); 933 } 934 } 935 936 static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset, 937 uint64_t value, unsigned size) 938 { 939 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 940 bool handle_rx; 941 942 trace_aspeed_i2c_bus_write(bus->id, offset, size, value); 943 944 switch (offset) { 945 case A_I2CD_FUN_CTRL: 946 if (SHARED_FIELD_EX32(value, SLAVE_EN)) { 947 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 948 __func__); 949 break; 950 } 951 bus->regs[R_I2CD_FUN_CTRL] = value & 0x0071C3FF; 952 break; 953 case A_I2CD_AC_TIMING1: 954 bus->regs[R_I2CD_AC_TIMING1] = value & 0xFFFFF0F; 955 break; 956 case A_I2CD_AC_TIMING2: 957 bus->regs[R_I2CD_AC_TIMING2] = value & 0x7; 958 break; 959 case A_I2CD_INTR_CTRL: 960 bus->regs[R_I2CD_INTR_CTRL] = value & 0x7FFF; 961 break; 962 case A_I2CD_INTR_STS: 963 handle_rx = SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_INTR_STS, RX_DONE) 964 && SHARED_FIELD_EX32(value, RX_DONE); 965 bus->regs[R_I2CD_INTR_STS] &= ~(value & 0x7FFF); 966 if (!bus->regs[R_I2CD_INTR_STS]) { 967 bus->controller->intr_status &= ~(1 << bus->id); 968 qemu_irq_lower(aic->bus_get_irq(bus)); 969 } 970 if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, 971 M_RX_CMD) || 972 SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, 973 M_S_RX_CMD_LAST))) { 974 aspeed_i2c_handle_rx_cmd(bus); 975 aspeed_i2c_bus_raise_interrupt(bus); 976 } 977 break; 978 case A_I2CD_DEV_ADDR: 979 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 980 __func__); 981 break; 982 case A_I2CD_POOL_CTRL: 983 bus->regs[R_I2CD_POOL_CTRL] &= ~0xffffff; 984 bus->regs[R_I2CD_POOL_CTRL] |= (value & 0xffffff); 985 break; 986 987 case A_I2CD_BYTE_BUF: 988 SHARED_ARRAY_FIELD_DP32(bus->regs, R_I2CD_BYTE_BUF, TX_BUF, value); 989 break; 990 case A_I2CD_CMD: 991 if (!aspeed_i2c_bus_is_enabled(bus)) { 992 break; 993 } 994 995 if (!aspeed_i2c_bus_is_master(bus)) { 996 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 997 __func__); 998 break; 999 } 1000 1001 if (!aic->has_dma && 1002 (SHARED_FIELD_EX32(value, RX_DMA_EN) || 1003 SHARED_FIELD_EX32(value, TX_DMA_EN))) { 1004 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 1005 break; 1006 } 1007 1008 bus->regs[R_I2CD_CMD] &= ~0xFFFF; 1009 bus->regs[R_I2CD_CMD] |= value & 0xFFFF; 1010 1011 aspeed_i2c_bus_handle_cmd(bus, value); 1012 aspeed_i2c_bus_raise_interrupt(bus); 1013 break; 1014 case A_I2CD_DMA_ADDR: 1015 if (!aic->has_dma) { 1016 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 1017 break; 1018 } 1019 1020 bus->regs[R_I2CD_DMA_ADDR] = value & 0x3ffffffc; 1021 break; 1022 1023 case A_I2CD_DMA_LEN: 1024 if (!aic->has_dma) { 1025 qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); 1026 break; 1027 } 1028 1029 bus->regs[R_I2CD_DMA_LEN] = value & 0xfff; 1030 if (!bus->regs[R_I2CD_DMA_LEN]) { 1031 qemu_log_mask(LOG_UNIMP, "%s: invalid DMA length\n", __func__); 1032 } 1033 break; 1034 1035 default: 1036 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 1037 __func__, offset); 1038 } 1039 } 1040 1041 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, 1042 uint64_t value, unsigned size) 1043 { 1044 AspeedI2CBus *bus = opaque; 1045 if (aspeed_i2c_is_new_mode(bus->controller)) { 1046 aspeed_i2c_bus_new_write(bus, offset, value, size); 1047 } else { 1048 aspeed_i2c_bus_old_write(bus, offset, value, size); 1049 } 1050 } 1051 1052 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, 1053 unsigned size) 1054 { 1055 AspeedI2CState *s = opaque; 1056 1057 switch (offset) { 1058 case A_I2C_CTRL_STATUS: 1059 return s->intr_status; 1060 case A_I2C_CTRL_GLOBAL: 1061 return s->ctrl_global; 1062 case A_I2C_CTRL_NEW_CLK_DIVIDER: 1063 if (aspeed_i2c_is_new_mode(s)) { 1064 return s->new_clk_divider; 1065 } 1066 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 1067 __func__, offset); 1068 break; 1069 default: 1070 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 1071 __func__, offset); 1072 break; 1073 } 1074 1075 return -1; 1076 } 1077 1078 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, 1079 uint64_t value, unsigned size) 1080 { 1081 AspeedI2CState *s = opaque; 1082 1083 switch (offset) { 1084 case A_I2C_CTRL_GLOBAL: 1085 s->ctrl_global = value; 1086 break; 1087 case A_I2C_CTRL_NEW_CLK_DIVIDER: 1088 if (aspeed_i2c_is_new_mode(s)) { 1089 s->new_clk_divider = value; 1090 } else { 1091 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx 1092 "\n", __func__, offset); 1093 } 1094 break; 1095 case A_I2C_CTRL_STATUS: 1096 default: 1097 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 1098 __func__, offset); 1099 break; 1100 } 1101 } 1102 1103 static const MemoryRegionOps aspeed_i2c_bus_ops = { 1104 .read = aspeed_i2c_bus_read, 1105 .write = aspeed_i2c_bus_write, 1106 .endianness = DEVICE_LITTLE_ENDIAN, 1107 }; 1108 1109 static const MemoryRegionOps aspeed_i2c_ctrl_ops = { 1110 .read = aspeed_i2c_ctrl_read, 1111 .write = aspeed_i2c_ctrl_write, 1112 .endianness = DEVICE_LITTLE_ENDIAN, 1113 }; 1114 1115 static uint64_t aspeed_i2c_pool_read(void *opaque, hwaddr offset, 1116 unsigned size) 1117 { 1118 AspeedI2CState *s = opaque; 1119 uint64_t ret = 0; 1120 int i; 1121 1122 for (i = 0; i < size; i++) { 1123 ret |= (uint64_t) s->pool[offset + i] << (8 * i); 1124 } 1125 1126 return ret; 1127 } 1128 1129 static void aspeed_i2c_pool_write(void *opaque, hwaddr offset, 1130 uint64_t value, unsigned size) 1131 { 1132 AspeedI2CState *s = opaque; 1133 int i; 1134 1135 for (i = 0; i < size; i++) { 1136 s->pool[offset + i] = (value >> (8 * i)) & 0xFF; 1137 } 1138 } 1139 1140 static const MemoryRegionOps aspeed_i2c_pool_ops = { 1141 .read = aspeed_i2c_pool_read, 1142 .write = aspeed_i2c_pool_write, 1143 .endianness = DEVICE_LITTLE_ENDIAN, 1144 .valid = { 1145 .min_access_size = 1, 1146 .max_access_size = 4, 1147 }, 1148 }; 1149 1150 static const VMStateDescription aspeed_i2c_bus_vmstate = { 1151 .name = TYPE_ASPEED_I2C, 1152 .version_id = 5, 1153 .minimum_version_id = 5, 1154 .fields = (VMStateField[]) { 1155 VMSTATE_UINT32_ARRAY(regs, AspeedI2CBus, ASPEED_I2C_NEW_NUM_REG), 1156 VMSTATE_END_OF_LIST() 1157 } 1158 }; 1159 1160 static const VMStateDescription aspeed_i2c_vmstate = { 1161 .name = TYPE_ASPEED_I2C, 1162 .version_id = 2, 1163 .minimum_version_id = 2, 1164 .fields = (VMStateField[]) { 1165 VMSTATE_UINT32(intr_status, AspeedI2CState), 1166 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, 1167 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, 1168 AspeedI2CBus), 1169 VMSTATE_UINT8_ARRAY(pool, AspeedI2CState, ASPEED_I2C_MAX_POOL_SIZE), 1170 VMSTATE_END_OF_LIST() 1171 } 1172 }; 1173 1174 static void aspeed_i2c_reset(DeviceState *dev) 1175 { 1176 AspeedI2CState *s = ASPEED_I2C(dev); 1177 1178 s->intr_status = 0; 1179 } 1180 1181 static void aspeed_i2c_instance_init(Object *obj) 1182 { 1183 AspeedI2CState *s = ASPEED_I2C(obj); 1184 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 1185 int i; 1186 1187 for (i = 0; i < aic->num_busses; i++) { 1188 object_initialize_child(obj, "bus[*]", &s->busses[i], 1189 TYPE_ASPEED_I2C_BUS); 1190 } 1191 } 1192 1193 /* 1194 * Address Definitions (AST2400 and AST2500) 1195 * 1196 * 0x000 ... 0x03F: Global Register 1197 * 0x040 ... 0x07F: Device 1 1198 * 0x080 ... 0x0BF: Device 2 1199 * 0x0C0 ... 0x0FF: Device 3 1200 * 0x100 ... 0x13F: Device 4 1201 * 0x140 ... 0x17F: Device 5 1202 * 0x180 ... 0x1BF: Device 6 1203 * 0x1C0 ... 0x1FF: Device 7 1204 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver) 1205 * 0x300 ... 0x33F: Device 8 1206 * 0x340 ... 0x37F: Device 9 1207 * 0x380 ... 0x3BF: Device 10 1208 * 0x3C0 ... 0x3FF: Device 11 1209 * 0x400 ... 0x43F: Device 12 1210 * 0x440 ... 0x47F: Device 13 1211 * 0x480 ... 0x4BF: Device 14 1212 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver) 1213 */ 1214 static void aspeed_i2c_realize(DeviceState *dev, Error **errp) 1215 { 1216 int i; 1217 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1218 AspeedI2CState *s = ASPEED_I2C(dev); 1219 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 1220 1221 sysbus_init_irq(sbd, &s->irq); 1222 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, 1223 "aspeed.i2c", 0x1000); 1224 sysbus_init_mmio(sbd, &s->iomem); 1225 1226 for (i = 0; i < aic->num_busses; i++) { 1227 Object *bus = OBJECT(&s->busses[i]); 1228 int offset = i < aic->gap ? 1 : 5; 1229 1230 if (!object_property_set_link(bus, "controller", OBJECT(s), errp)) { 1231 return; 1232 } 1233 1234 if (!object_property_set_uint(bus, "bus-id", i, errp)) { 1235 return; 1236 } 1237 1238 if (!sysbus_realize(SYS_BUS_DEVICE(bus), errp)) { 1239 return; 1240 } 1241 1242 memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), 1243 &s->busses[i].mr); 1244 } 1245 1246 memory_region_init_io(&s->pool_iomem, OBJECT(s), &aspeed_i2c_pool_ops, s, 1247 "aspeed.i2c-pool", aic->pool_size); 1248 memory_region_add_subregion(&s->iomem, aic->pool_base, &s->pool_iomem); 1249 1250 if (aic->has_dma) { 1251 if (!s->dram_mr) { 1252 error_setg(errp, TYPE_ASPEED_I2C ": 'dram' link not set"); 1253 return; 1254 } 1255 1256 address_space_init(&s->dram_as, s->dram_mr, 1257 TYPE_ASPEED_I2C "-dma-dram"); 1258 } 1259 } 1260 1261 static Property aspeed_i2c_properties[] = { 1262 DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, 1263 TYPE_MEMORY_REGION, MemoryRegion *), 1264 DEFINE_PROP_END_OF_LIST(), 1265 }; 1266 1267 static void aspeed_i2c_class_init(ObjectClass *klass, void *data) 1268 { 1269 DeviceClass *dc = DEVICE_CLASS(klass); 1270 1271 dc->vmsd = &aspeed_i2c_vmstate; 1272 dc->reset = aspeed_i2c_reset; 1273 device_class_set_props(dc, aspeed_i2c_properties); 1274 dc->realize = aspeed_i2c_realize; 1275 dc->desc = "Aspeed I2C Controller"; 1276 } 1277 1278 static const TypeInfo aspeed_i2c_info = { 1279 .name = TYPE_ASPEED_I2C, 1280 .parent = TYPE_SYS_BUS_DEVICE, 1281 .instance_init = aspeed_i2c_instance_init, 1282 .instance_size = sizeof(AspeedI2CState), 1283 .class_init = aspeed_i2c_class_init, 1284 .class_size = sizeof(AspeedI2CClass), 1285 .abstract = true, 1286 }; 1287 1288 static void aspeed_i2c_bus_reset(DeviceState *dev) 1289 { 1290 AspeedI2CBus *s = ASPEED_I2C_BUS(dev); 1291 1292 memset(s->regs, 0, sizeof(s->regs)); 1293 i2c_end_transfer(s->bus); 1294 } 1295 1296 static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp) 1297 { 1298 AspeedI2CBus *s = ASPEED_I2C_BUS(dev); 1299 AspeedI2CClass *aic; 1300 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id); 1301 1302 if (!s->controller) { 1303 error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set"); 1304 return; 1305 } 1306 1307 aic = ASPEED_I2C_GET_CLASS(s->controller); 1308 1309 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 1310 1311 s->bus = i2c_init_bus(dev, name); 1312 1313 memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops, 1314 s, name, aic->reg_size); 1315 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); 1316 } 1317 1318 static Property aspeed_i2c_bus_properties[] = { 1319 DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0), 1320 DEFINE_PROP_LINK("controller", AspeedI2CBus, controller, TYPE_ASPEED_I2C, 1321 AspeedI2CState *), 1322 DEFINE_PROP_END_OF_LIST(), 1323 }; 1324 1325 static void aspeed_i2c_bus_class_init(ObjectClass *klass, void *data) 1326 { 1327 DeviceClass *dc = DEVICE_CLASS(klass); 1328 1329 dc->desc = "Aspeed I2C Bus"; 1330 dc->realize = aspeed_i2c_bus_realize; 1331 dc->reset = aspeed_i2c_bus_reset; 1332 device_class_set_props(dc, aspeed_i2c_bus_properties); 1333 } 1334 1335 static const TypeInfo aspeed_i2c_bus_info = { 1336 .name = TYPE_ASPEED_I2C_BUS, 1337 .parent = TYPE_SYS_BUS_DEVICE, 1338 .instance_size = sizeof(AspeedI2CBus), 1339 .class_init = aspeed_i2c_bus_class_init, 1340 }; 1341 1342 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) 1343 { 1344 return bus->controller->irq; 1345 } 1346 1347 static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) 1348 { 1349 uint8_t *pool_page = 1350 &bus->controller->pool[ARRAY_FIELD_EX32(bus->regs, I2CD_FUN_CTRL, 1351 POOL_PAGE_SEL) * 0x100]; 1352 1353 return &pool_page[ARRAY_FIELD_EX32(bus->regs, I2CD_POOL_CTRL, OFFSET)]; 1354 } 1355 1356 static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) 1357 { 1358 DeviceClass *dc = DEVICE_CLASS(klass); 1359 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1360 1361 dc->desc = "ASPEED 2400 I2C Controller"; 1362 1363 aic->num_busses = 14; 1364 aic->reg_size = 0x40; 1365 aic->gap = 7; 1366 aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; 1367 aic->pool_size = 0x800; 1368 aic->pool_base = 0x800; 1369 aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; 1370 } 1371 1372 static const TypeInfo aspeed_2400_i2c_info = { 1373 .name = TYPE_ASPEED_2400_I2C, 1374 .parent = TYPE_ASPEED_I2C, 1375 .class_init = aspeed_2400_i2c_class_init, 1376 }; 1377 1378 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) 1379 { 1380 return bus->controller->irq; 1381 } 1382 1383 static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) 1384 { 1385 return &bus->controller->pool[bus->id * 0x10]; 1386 } 1387 1388 static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) 1389 { 1390 DeviceClass *dc = DEVICE_CLASS(klass); 1391 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1392 1393 dc->desc = "ASPEED 2500 I2C Controller"; 1394 1395 aic->num_busses = 14; 1396 aic->reg_size = 0x40; 1397 aic->gap = 7; 1398 aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; 1399 aic->pool_size = 0x100; 1400 aic->pool_base = 0x200; 1401 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 1402 aic->check_sram = true; 1403 aic->has_dma = true; 1404 } 1405 1406 static const TypeInfo aspeed_2500_i2c_info = { 1407 .name = TYPE_ASPEED_2500_I2C, 1408 .parent = TYPE_ASPEED_I2C, 1409 .class_init = aspeed_2500_i2c_class_init, 1410 }; 1411 1412 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) 1413 { 1414 return bus->irq; 1415 } 1416 1417 static uint8_t *aspeed_2600_i2c_bus_pool_base(AspeedI2CBus *bus) 1418 { 1419 return &bus->controller->pool[bus->id * 0x20]; 1420 } 1421 1422 static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) 1423 { 1424 DeviceClass *dc = DEVICE_CLASS(klass); 1425 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 1426 1427 dc->desc = "ASPEED 2600 I2C Controller"; 1428 1429 aic->num_busses = 16; 1430 aic->reg_size = 0x80; 1431 aic->gap = -1; /* no gap */ 1432 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 1433 aic->pool_size = 0x200; 1434 aic->pool_base = 0xC00; 1435 aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; 1436 aic->has_dma = true; 1437 } 1438 1439 static const TypeInfo aspeed_2600_i2c_info = { 1440 .name = TYPE_ASPEED_2600_I2C, 1441 .parent = TYPE_ASPEED_I2C, 1442 .class_init = aspeed_2600_i2c_class_init, 1443 }; 1444 1445 static void aspeed_i2c_register_types(void) 1446 { 1447 type_register_static(&aspeed_i2c_bus_info); 1448 type_register_static(&aspeed_i2c_info); 1449 type_register_static(&aspeed_2400_i2c_info); 1450 type_register_static(&aspeed_2500_i2c_info); 1451 type_register_static(&aspeed_2600_i2c_info); 1452 } 1453 1454 type_init(aspeed_i2c_register_types) 1455 1456 1457 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr) 1458 { 1459 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 1460 I2CBus *bus = NULL; 1461 1462 if (busnr >= 0 && busnr < aic->num_busses) { 1463 bus = s->busses[busnr].bus; 1464 } 1465 1466 return bus; 1467 } 1468