1a72bd606SHelge Deller /* HPPA cores and system support chips. */ 2a72bd606SHelge Deller 3f91005e1SMarkus Armbruster #ifndef HW_HPPA_HPPA_HARDWARE_H 4f91005e1SMarkus Armbruster #define HW_HPPA_HPPA_HARDWARE_H 5f91005e1SMarkus Armbruster 6a72bd606SHelge Deller #define FIRMWARE_START 0xf0000000 7a72bd606SHelge Deller #define FIRMWARE_END 0xf0800000 8a72bd606SHelge Deller 9a72bd606SHelge Deller #define DEVICE_HPA_LEN 0x00100000 10a72bd606SHelge Deller 11a72bd606SHelge Deller #define GSC_HPA 0xffc00000 12a72bd606SHelge Deller #define DINO_HPA 0xfff80000 13a72bd606SHelge Deller #define DINO_UART_HPA 0xfff83000 14a72bd606SHelge Deller #define DINO_UART_BASE 0xfff83800 15a72bd606SHelge Deller #define DINO_SCSI_HPA 0xfff8c000 16a72bd606SHelge Deller #define LASI_HPA 0xffd00000 17a72bd606SHelge Deller #define LASI_UART_HPA 0xffd05000 18a72bd606SHelge Deller #define LASI_SCSI_HPA 0xffd06000 19a72bd606SHelge Deller #define LASI_LAN_HPA 0xffd07000 20e3a99a8aSHelge Deller #define LASI_RTC_HPA 0xffd09000 21a72bd606SHelge Deller #define LASI_LPT_HPA 0xffd02000 22a72bd606SHelge Deller #define LASI_AUDIO_HPA 0xffd04000 23a72bd606SHelge Deller #define LASI_PS2KBD_HPA 0xffd08000 24a72bd606SHelge Deller #define LASI_PS2MOU_HPA 0xffd08100 25a72bd606SHelge Deller #define LASI_GFX_HPA 0xf8000000 264765384cSSven Schnelle #define ARTIST_FB_ADDR 0xf9000000 272b42f31eSHelge Deller #define CPU_HPA 0xfffb0000 28a72bd606SHelge Deller #define MEMORY_HPA 0xfffbf000 29a72bd606SHelge Deller 30a72bd606SHelge Deller #define PCI_HPA DINO_HPA /* PCI bus */ 31a72bd606SHelge Deller #define IDE_HPA 0xf9000000 /* Boot disc controller */ 32a72bd606SHelge Deller 33a72bd606SHelge Deller /* offsets to DINO HPA: */ 34a72bd606SHelge Deller #define DINO_PCI_ADDR 0x064 35a72bd606SHelge Deller #define DINO_CONFIG_DATA 0x068 36a72bd606SHelge Deller #define DINO_IO_DATA 0x06c 37a72bd606SHelge Deller 38a72bd606SHelge Deller #define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR) 39a72bd606SHelge Deller #define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA) 40a72bd606SHelge Deller 41*24576007SHelge Deller #define FW_CFG_IO_BASE 0xfffa0000 42e3a99a8aSHelge Deller 43a72bd606SHelge Deller #define PORT_SERIAL1 (DINO_UART_HPA + 0x800) 44a72bd606SHelge Deller #define PORT_SERIAL2 (LASI_UART_HPA + 0x800) 45a72bd606SHelge Deller 462b42f31eSHelge Deller #define HPPA_MAX_CPUS 8 /* max. number of SMP CPUs */ 47a72bd606SHelge Deller #define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ 48f91005e1SMarkus Armbruster 49e3a99a8aSHelge Deller #define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */ 50e3a99a8aSHelge Deller 51f91005e1SMarkus Armbruster #endif 52