1 /* 2 * Copyright (c) 2006-2008 Openedhand Ltd. 3 * Written by Andrzej Zaborowski <balrog@zabor.org> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 or 8 * (at your option) version 3 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/irq.h" 21 #include "hw/arm/sharpsl.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "qemu/module.h" 25 #include "qemu/log.h" 26 #include "qom/object.h" 27 28 /* SCOOP devices */ 29 30 #define TYPE_SCOOP "scoop" 31 typedef struct ScoopInfo ScoopInfo; 32 DECLARE_INSTANCE_CHECKER(ScoopInfo, SCOOP, 33 TYPE_SCOOP) 34 35 struct ScoopInfo { 36 SysBusDevice parent_obj; 37 38 qemu_irq handler[16]; 39 MemoryRegion iomem; 40 uint16_t status; 41 uint16_t power; 42 uint32_t gpio_level; 43 uint32_t gpio_dir; 44 uint32_t prev_level; 45 46 uint16_t mcr; 47 uint16_t cdr; 48 uint16_t ccr; 49 uint16_t irr; 50 uint16_t imr; 51 uint16_t isr; 52 }; 53 54 #define SCOOP_MCR 0x00 55 #define SCOOP_CDR 0x04 56 #define SCOOP_CSR 0x08 57 #define SCOOP_CPR 0x0c 58 #define SCOOP_CCR 0x10 59 #define SCOOP_IRR_IRM 0x14 60 #define SCOOP_IMR 0x18 61 #define SCOOP_ISR 0x1c 62 #define SCOOP_GPCR 0x20 63 #define SCOOP_GPWR 0x24 64 #define SCOOP_GPRR 0x28 65 66 static inline void scoop_gpio_handler_update(ScoopInfo *s) { 67 uint32_t level, diff; 68 int bit; 69 level = s->gpio_level & s->gpio_dir; 70 71 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 72 bit = ctz32(diff); 73 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 74 } 75 76 s->prev_level = level; 77 } 78 79 static uint64_t scoop_read(void *opaque, hwaddr addr, 80 unsigned size) 81 { 82 ScoopInfo *s = (ScoopInfo *) opaque; 83 84 switch (addr & 0x3f) { 85 case SCOOP_MCR: 86 return s->mcr; 87 case SCOOP_CDR: 88 return s->cdr; 89 case SCOOP_CSR: 90 return s->status; 91 case SCOOP_CPR: 92 return s->power; 93 case SCOOP_CCR: 94 return s->ccr; 95 case SCOOP_IRR_IRM: 96 return s->irr; 97 case SCOOP_IMR: 98 return s->imr; 99 case SCOOP_ISR: 100 return s->isr; 101 case SCOOP_GPCR: 102 return s->gpio_dir; 103 case SCOOP_GPWR: 104 case SCOOP_GPRR: 105 return s->gpio_level; 106 default: 107 qemu_log_mask(LOG_GUEST_ERROR, 108 "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n", 109 addr); 110 } 111 112 return 0; 113 } 114 115 static void scoop_write(void *opaque, hwaddr addr, 116 uint64_t value, unsigned size) 117 { 118 ScoopInfo *s = (ScoopInfo *) opaque; 119 value &= 0xffff; 120 121 switch (addr & 0x3f) { 122 case SCOOP_MCR: 123 s->mcr = value; 124 break; 125 case SCOOP_CDR: 126 s->cdr = value; 127 break; 128 case SCOOP_CPR: 129 s->power = value; 130 if (value & 0x80) 131 s->power |= 0x8040; 132 break; 133 case SCOOP_CCR: 134 s->ccr = value; 135 break; 136 case SCOOP_IRR_IRM: 137 s->irr = value; 138 break; 139 case SCOOP_IMR: 140 s->imr = value; 141 break; 142 case SCOOP_ISR: 143 s->isr = value; 144 break; 145 case SCOOP_GPCR: 146 s->gpio_dir = value; 147 scoop_gpio_handler_update(s); 148 break; 149 case SCOOP_GPWR: 150 case SCOOP_GPRR: /* GPRR is probably R/O in real HW */ 151 s->gpio_level = value & s->gpio_dir; 152 scoop_gpio_handler_update(s); 153 break; 154 default: 155 qemu_log_mask(LOG_GUEST_ERROR, 156 "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n", 157 addr); 158 } 159 } 160 161 static const MemoryRegionOps scoop_ops = { 162 .read = scoop_read, 163 .write = scoop_write, 164 .endianness = DEVICE_NATIVE_ENDIAN, 165 }; 166 167 static void scoop_gpio_set(void *opaque, int line, int level) 168 { 169 ScoopInfo *s = (ScoopInfo *) opaque; 170 171 if (level) 172 s->gpio_level |= (1 << line); 173 else 174 s->gpio_level &= ~(1 << line); 175 } 176 177 static void scoop_init(Object *obj) 178 { 179 DeviceState *dev = DEVICE(obj); 180 ScoopInfo *s = SCOOP(obj); 181 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 182 183 s->status = 0x02; 184 qdev_init_gpio_out(dev, s->handler, 16); 185 qdev_init_gpio_in(dev, scoop_gpio_set, 16); 186 memory_region_init_io(&s->iomem, obj, &scoop_ops, s, "scoop", 0x1000); 187 188 sysbus_init_mmio(sbd, &s->iomem); 189 } 190 191 static int scoop_post_load(void *opaque, int version_id) 192 { 193 ScoopInfo *s = (ScoopInfo *) opaque; 194 int i; 195 uint32_t level; 196 197 level = s->gpio_level & s->gpio_dir; 198 199 for (i = 0; i < 16; i++) { 200 qemu_set_irq(s->handler[i], (level >> i) & 1); 201 } 202 203 s->prev_level = level; 204 205 return 0; 206 } 207 208 static bool is_version_0 (void *opaque, int version_id) 209 { 210 return version_id == 0; 211 } 212 213 static bool vmstate_scoop_validate(void *opaque, int version_id) 214 { 215 ScoopInfo *s = opaque; 216 217 return !(s->prev_level & 0xffff0000) && 218 !(s->gpio_level & 0xffff0000) && 219 !(s->gpio_dir & 0xffff0000); 220 } 221 222 static const VMStateDescription vmstate_scoop_regs = { 223 .name = "scoop", 224 .version_id = 1, 225 .minimum_version_id = 0, 226 .post_load = scoop_post_load, 227 .fields = (VMStateField[]) { 228 VMSTATE_UINT16(status, ScoopInfo), 229 VMSTATE_UINT16(power, ScoopInfo), 230 VMSTATE_UINT32(gpio_level, ScoopInfo), 231 VMSTATE_UINT32(gpio_dir, ScoopInfo), 232 VMSTATE_UINT32(prev_level, ScoopInfo), 233 VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate), 234 VMSTATE_UINT16(mcr, ScoopInfo), 235 VMSTATE_UINT16(cdr, ScoopInfo), 236 VMSTATE_UINT16(ccr, ScoopInfo), 237 VMSTATE_UINT16(irr, ScoopInfo), 238 VMSTATE_UINT16(imr, ScoopInfo), 239 VMSTATE_UINT16(isr, ScoopInfo), 240 VMSTATE_UNUSED_TEST(is_version_0, 2), 241 VMSTATE_END_OF_LIST(), 242 }, 243 }; 244 245 static void scoop_sysbus_class_init(ObjectClass *klass, void *data) 246 { 247 DeviceClass *dc = DEVICE_CLASS(klass); 248 249 dc->desc = "Scoop2 Sharp custom ASIC"; 250 dc->vmsd = &vmstate_scoop_regs; 251 } 252 253 static const TypeInfo scoop_sysbus_info = { 254 .name = TYPE_SCOOP, 255 .parent = TYPE_SYS_BUS_DEVICE, 256 .instance_size = sizeof(ScoopInfo), 257 .instance_init = scoop_init, 258 .class_init = scoop_sysbus_class_init, 259 }; 260 261 static void scoop_register_types(void) 262 { 263 type_register_static(&scoop_sysbus_info); 264 } 265 266 type_init(scoop_register_types) 267 268 /* Write the bootloader parameters memory area. */ 269 270 #define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a) 271 272 static struct QEMU_PACKED sl_param_info { 273 uint32_t comadj_keyword; 274 int32_t comadj; 275 276 uint32_t uuid_keyword; 277 char uuid[16]; 278 279 uint32_t touch_keyword; 280 int32_t touch_xp; 281 int32_t touch_yp; 282 int32_t touch_xd; 283 int32_t touch_yd; 284 285 uint32_t adadj_keyword; 286 int32_t adadj; 287 288 uint32_t phad_keyword; 289 int32_t phadadj; 290 } zaurus_bootparam = { 291 .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'), 292 .comadj = 125, 293 .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'), 294 .uuid = { -1 }, 295 .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'), 296 .touch_xp = -1, 297 .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'), 298 .adadj = -1, 299 .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'), 300 .phadadj = 0x01, 301 }; 302 303 void sl_bootparam_write(hwaddr ptr) 304 { 305 cpu_physical_memory_write(ptr, &zaurus_bootparam, 306 sizeof(struct sl_param_info)); 307 } 308