1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "hw/sysbus.h" 12 13 //#define DEBUG_PL061 1 14 15 #ifdef DEBUG_PL061 16 #define DPRINTF(fmt, ...) \ 17 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) 18 #define BADF(fmt, ...) \ 19 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 20 #else 21 #define DPRINTF(fmt, ...) do {} while(0) 22 #define BADF(fmt, ...) \ 23 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) 24 #endif 25 26 static const uint8_t pl061_id[12] = 27 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 28 static const uint8_t pl061_id_luminary[12] = 29 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 30 31 typedef struct PL061State { 32 SysBusDevice busdev; 33 MemoryRegion iomem; 34 uint32_t locked; 35 uint32_t data; 36 uint32_t old_data; 37 uint32_t dir; 38 uint32_t isense; 39 uint32_t ibe; 40 uint32_t iev; 41 uint32_t im; 42 uint32_t istate; 43 uint32_t afsel; 44 uint32_t dr2r; 45 uint32_t dr4r; 46 uint32_t dr8r; 47 uint32_t odr; 48 uint32_t pur; 49 uint32_t pdr; 50 uint32_t slr; 51 uint32_t den; 52 uint32_t cr; 53 uint32_t float_high; 54 uint32_t amsel; 55 qemu_irq irq; 56 qemu_irq out[8]; 57 const unsigned char *id; 58 } PL061State; 59 60 static const VMStateDescription vmstate_pl061 = { 61 .name = "pl061", 62 .version_id = 2, 63 .minimum_version_id = 1, 64 .fields = (VMStateField[]) { 65 VMSTATE_UINT32(locked, PL061State), 66 VMSTATE_UINT32(data, PL061State), 67 VMSTATE_UINT32(old_data, PL061State), 68 VMSTATE_UINT32(dir, PL061State), 69 VMSTATE_UINT32(isense, PL061State), 70 VMSTATE_UINT32(ibe, PL061State), 71 VMSTATE_UINT32(iev, PL061State), 72 VMSTATE_UINT32(im, PL061State), 73 VMSTATE_UINT32(istate, PL061State), 74 VMSTATE_UINT32(afsel, PL061State), 75 VMSTATE_UINT32(dr2r, PL061State), 76 VMSTATE_UINT32(dr4r, PL061State), 77 VMSTATE_UINT32(dr8r, PL061State), 78 VMSTATE_UINT32(odr, PL061State), 79 VMSTATE_UINT32(pur, PL061State), 80 VMSTATE_UINT32(pdr, PL061State), 81 VMSTATE_UINT32(slr, PL061State), 82 VMSTATE_UINT32(den, PL061State), 83 VMSTATE_UINT32(cr, PL061State), 84 VMSTATE_UINT32(float_high, PL061State), 85 VMSTATE_UINT32_V(amsel, PL061State, 2), 86 VMSTATE_END_OF_LIST() 87 } 88 }; 89 90 static void pl061_update(PL061State *s) 91 { 92 uint8_t changed; 93 uint8_t mask; 94 uint8_t out; 95 int i; 96 97 /* Outputs float high. */ 98 /* FIXME: This is board dependent. */ 99 out = (s->data & s->dir) | ~s->dir; 100 changed = s->old_data ^ out; 101 if (!changed) 102 return; 103 104 s->old_data = out; 105 for (i = 0; i < 8; i++) { 106 mask = 1 << i; 107 if (changed & mask) { 108 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); 109 qemu_set_irq(s->out[i], (out & mask) != 0); 110 } 111 } 112 113 /* FIXME: Implement input interrupts. */ 114 } 115 116 static uint64_t pl061_read(void *opaque, hwaddr offset, 117 unsigned size) 118 { 119 PL061State *s = (PL061State *)opaque; 120 121 if (offset >= 0xfd0 && offset < 0x1000) { 122 return s->id[(offset - 0xfd0) >> 2]; 123 } 124 if (offset < 0x400) { 125 return s->data & (offset >> 2); 126 } 127 switch (offset) { 128 case 0x400: /* Direction */ 129 return s->dir; 130 case 0x404: /* Interrupt sense */ 131 return s->isense; 132 case 0x408: /* Interrupt both edges */ 133 return s->ibe; 134 case 0x40c: /* Interrupt event */ 135 return s->iev; 136 case 0x410: /* Interrupt mask */ 137 return s->im; 138 case 0x414: /* Raw interrupt status */ 139 return s->istate; 140 case 0x418: /* Masked interrupt status */ 141 return s->istate | s->im; 142 case 0x420: /* Alternate function select */ 143 return s->afsel; 144 case 0x500: /* 2mA drive */ 145 return s->dr2r; 146 case 0x504: /* 4mA drive */ 147 return s->dr4r; 148 case 0x508: /* 8mA drive */ 149 return s->dr8r; 150 case 0x50c: /* Open drain */ 151 return s->odr; 152 case 0x510: /* Pull-up */ 153 return s->pur; 154 case 0x514: /* Pull-down */ 155 return s->pdr; 156 case 0x518: /* Slew rate control */ 157 return s->slr; 158 case 0x51c: /* Digital enable */ 159 return s->den; 160 case 0x520: /* Lock */ 161 return s->locked; 162 case 0x524: /* Commit */ 163 return s->cr; 164 case 0x528: /* Analog mode select */ 165 return s->amsel; 166 default: 167 qemu_log_mask(LOG_GUEST_ERROR, 168 "pl061_read: Bad offset %x\n", (int)offset); 169 return 0; 170 } 171 } 172 173 static void pl061_write(void *opaque, hwaddr offset, 174 uint64_t value, unsigned size) 175 { 176 PL061State *s = (PL061State *)opaque; 177 uint8_t mask; 178 179 if (offset < 0x400) { 180 mask = (offset >> 2) & s->dir; 181 s->data = (s->data & ~mask) | (value & mask); 182 pl061_update(s); 183 return; 184 } 185 switch (offset) { 186 case 0x400: /* Direction */ 187 s->dir = value & 0xff; 188 break; 189 case 0x404: /* Interrupt sense */ 190 s->isense = value & 0xff; 191 break; 192 case 0x408: /* Interrupt both edges */ 193 s->ibe = value & 0xff; 194 break; 195 case 0x40c: /* Interrupt event */ 196 s->iev = value & 0xff; 197 break; 198 case 0x410: /* Interrupt mask */ 199 s->im = value & 0xff; 200 break; 201 case 0x41c: /* Interrupt clear */ 202 s->istate &= ~value; 203 break; 204 case 0x420: /* Alternate function select */ 205 mask = s->cr; 206 s->afsel = (s->afsel & ~mask) | (value & mask); 207 break; 208 case 0x500: /* 2mA drive */ 209 s->dr2r = value & 0xff; 210 break; 211 case 0x504: /* 4mA drive */ 212 s->dr4r = value & 0xff; 213 break; 214 case 0x508: /* 8mA drive */ 215 s->dr8r = value & 0xff; 216 break; 217 case 0x50c: /* Open drain */ 218 s->odr = value & 0xff; 219 break; 220 case 0x510: /* Pull-up */ 221 s->pur = value & 0xff; 222 break; 223 case 0x514: /* Pull-down */ 224 s->pdr = value & 0xff; 225 break; 226 case 0x518: /* Slew rate control */ 227 s->slr = value & 0xff; 228 break; 229 case 0x51c: /* Digital enable */ 230 s->den = value & 0xff; 231 break; 232 case 0x520: /* Lock */ 233 s->locked = (value != 0xacce551); 234 break; 235 case 0x524: /* Commit */ 236 if (!s->locked) 237 s->cr = value & 0xff; 238 break; 239 case 0x528: 240 s->amsel = value & 0xff; 241 break; 242 default: 243 qemu_log_mask(LOG_GUEST_ERROR, 244 "pl061_write: Bad offset %x\n", (int)offset); 245 } 246 pl061_update(s); 247 } 248 249 static void pl061_reset(PL061State *s) 250 { 251 s->locked = 1; 252 s->cr = 0xff; 253 } 254 255 static void pl061_set_irq(void * opaque, int irq, int level) 256 { 257 PL061State *s = (PL061State *)opaque; 258 uint8_t mask; 259 260 mask = 1 << irq; 261 if ((s->dir & mask) == 0) { 262 s->data &= ~mask; 263 if (level) 264 s->data |= mask; 265 pl061_update(s); 266 } 267 } 268 269 static const MemoryRegionOps pl061_ops = { 270 .read = pl061_read, 271 .write = pl061_write, 272 .endianness = DEVICE_NATIVE_ENDIAN, 273 }; 274 275 static int pl061_init(SysBusDevice *dev, const unsigned char *id) 276 { 277 PL061State *s = FROM_SYSBUS(PL061State, dev); 278 s->id = id; 279 memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000); 280 sysbus_init_mmio(dev, &s->iomem); 281 sysbus_init_irq(dev, &s->irq); 282 qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8); 283 qdev_init_gpio_out(&dev->qdev, s->out, 8); 284 pl061_reset(s); 285 return 0; 286 } 287 288 static int pl061_init_luminary(SysBusDevice *dev) 289 { 290 return pl061_init(dev, pl061_id_luminary); 291 } 292 293 static int pl061_init_arm(SysBusDevice *dev) 294 { 295 return pl061_init(dev, pl061_id); 296 } 297 298 static void pl061_class_init(ObjectClass *klass, void *data) 299 { 300 DeviceClass *dc = DEVICE_CLASS(klass); 301 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 302 303 k->init = pl061_init_arm; 304 dc->vmsd = &vmstate_pl061; 305 } 306 307 static const TypeInfo pl061_info = { 308 .name = "pl061", 309 .parent = TYPE_SYS_BUS_DEVICE, 310 .instance_size = sizeof(PL061State), 311 .class_init = pl061_class_init, 312 }; 313 314 static void pl061_luminary_class_init(ObjectClass *klass, void *data) 315 { 316 DeviceClass *dc = DEVICE_CLASS(klass); 317 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 318 319 k->init = pl061_init_luminary; 320 dc->vmsd = &vmstate_pl061; 321 } 322 323 static const TypeInfo pl061_luminary_info = { 324 .name = "pl061_luminary", 325 .parent = TYPE_SYS_BUS_DEVICE, 326 .instance_size = sizeof(PL061State), 327 .class_init = pl061_luminary_class_init, 328 }; 329 330 static void pl061_register_types(void) 331 { 332 type_register_static(&pl061_info); 333 type_register_static(&pl061_luminary_info); 334 } 335 336 type_init(pl061_register_types) 337