1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/sysbus.h" 13 14 //#define DEBUG_PL061 1 15 16 #ifdef DEBUG_PL061 17 #define DPRINTF(fmt, ...) \ 18 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) 19 #define BADF(fmt, ...) \ 20 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 21 #else 22 #define DPRINTF(fmt, ...) do {} while(0) 23 #define BADF(fmt, ...) \ 24 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) 25 #endif 26 27 static const uint8_t pl061_id[12] = 28 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 29 static const uint8_t pl061_id_luminary[12] = 30 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 31 32 #define TYPE_PL061 "pl061" 33 #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061) 34 35 typedef struct PL061State { 36 SysBusDevice parent_obj; 37 38 MemoryRegion iomem; 39 uint32_t locked; 40 uint32_t data; 41 uint32_t old_out_data; 42 uint32_t old_in_data; 43 uint32_t dir; 44 uint32_t isense; 45 uint32_t ibe; 46 uint32_t iev; 47 uint32_t im; 48 uint32_t istate; 49 uint32_t afsel; 50 uint32_t dr2r; 51 uint32_t dr4r; 52 uint32_t dr8r; 53 uint32_t odr; 54 uint32_t pur; 55 uint32_t pdr; 56 uint32_t slr; 57 uint32_t den; 58 uint32_t cr; 59 uint32_t amsel; 60 qemu_irq irq; 61 qemu_irq out[8]; 62 const unsigned char *id; 63 uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ 64 } PL061State; 65 66 static const VMStateDescription vmstate_pl061 = { 67 .name = "pl061", 68 .version_id = 4, 69 .minimum_version_id = 4, 70 .fields = (VMStateField[]) { 71 VMSTATE_UINT32(locked, PL061State), 72 VMSTATE_UINT32(data, PL061State), 73 VMSTATE_UINT32(old_out_data, PL061State), 74 VMSTATE_UINT32(old_in_data, PL061State), 75 VMSTATE_UINT32(dir, PL061State), 76 VMSTATE_UINT32(isense, PL061State), 77 VMSTATE_UINT32(ibe, PL061State), 78 VMSTATE_UINT32(iev, PL061State), 79 VMSTATE_UINT32(im, PL061State), 80 VMSTATE_UINT32(istate, PL061State), 81 VMSTATE_UINT32(afsel, PL061State), 82 VMSTATE_UINT32(dr2r, PL061State), 83 VMSTATE_UINT32(dr4r, PL061State), 84 VMSTATE_UINT32(dr8r, PL061State), 85 VMSTATE_UINT32(odr, PL061State), 86 VMSTATE_UINT32(pur, PL061State), 87 VMSTATE_UINT32(pdr, PL061State), 88 VMSTATE_UINT32(slr, PL061State), 89 VMSTATE_UINT32(den, PL061State), 90 VMSTATE_UINT32(cr, PL061State), 91 VMSTATE_UINT32_V(amsel, PL061State, 2), 92 VMSTATE_END_OF_LIST() 93 } 94 }; 95 96 static void pl061_update(PL061State *s) 97 { 98 uint8_t changed; 99 uint8_t mask; 100 uint8_t out; 101 int i; 102 103 DPRINTF("dir = %d, data = %d\n", s->dir, s->data); 104 105 /* Outputs float high. */ 106 /* FIXME: This is board dependent. */ 107 out = (s->data & s->dir) | ~s->dir; 108 changed = s->old_out_data ^ out; 109 if (changed) { 110 s->old_out_data = out; 111 for (i = 0; i < 8; i++) { 112 mask = 1 << i; 113 if (changed & mask) { 114 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); 115 qemu_set_irq(s->out[i], (out & mask) != 0); 116 } 117 } 118 } 119 120 /* Inputs */ 121 changed = (s->old_in_data ^ s->data) & ~s->dir; 122 if (changed) { 123 s->old_in_data = s->data; 124 for (i = 0; i < 8; i++) { 125 mask = 1 << i; 126 if (changed & mask) { 127 DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); 128 129 if (!(s->isense & mask)) { 130 /* Edge interrupt */ 131 if (s->ibe & mask) { 132 /* Any edge triggers the interrupt */ 133 s->istate |= mask; 134 } else { 135 /* Edge is selected by IEV */ 136 s->istate |= ~(s->data ^ s->iev) & mask; 137 } 138 } 139 } 140 } 141 } 142 143 /* Level interrupt */ 144 s->istate |= ~(s->data ^ s->iev) & s->isense; 145 146 DPRINTF("istate = %02X\n", s->istate); 147 148 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 149 } 150 151 static uint64_t pl061_read(void *opaque, hwaddr offset, 152 unsigned size) 153 { 154 PL061State *s = (PL061State *)opaque; 155 156 if (offset < 0x400) { 157 return s->data & (offset >> 2); 158 } 159 if (offset >= s->rsvd_start && offset <= 0xfcc) { 160 goto err_out; 161 } 162 if (offset >= 0xfd0 && offset < 0x1000) { 163 return s->id[(offset - 0xfd0) >> 2]; 164 } 165 switch (offset) { 166 case 0x400: /* Direction */ 167 return s->dir; 168 case 0x404: /* Interrupt sense */ 169 return s->isense; 170 case 0x408: /* Interrupt both edges */ 171 return s->ibe; 172 case 0x40c: /* Interrupt event */ 173 return s->iev; 174 case 0x410: /* Interrupt mask */ 175 return s->im; 176 case 0x414: /* Raw interrupt status */ 177 return s->istate; 178 case 0x418: /* Masked interrupt status */ 179 return s->istate & s->im; 180 case 0x420: /* Alternate function select */ 181 return s->afsel; 182 case 0x500: /* 2mA drive */ 183 return s->dr2r; 184 case 0x504: /* 4mA drive */ 185 return s->dr4r; 186 case 0x508: /* 8mA drive */ 187 return s->dr8r; 188 case 0x50c: /* Open drain */ 189 return s->odr; 190 case 0x510: /* Pull-up */ 191 return s->pur; 192 case 0x514: /* Pull-down */ 193 return s->pdr; 194 case 0x518: /* Slew rate control */ 195 return s->slr; 196 case 0x51c: /* Digital enable */ 197 return s->den; 198 case 0x520: /* Lock */ 199 return s->locked; 200 case 0x524: /* Commit */ 201 return s->cr; 202 case 0x528: /* Analog mode select */ 203 return s->amsel; 204 default: 205 break; 206 } 207 err_out: 208 qemu_log_mask(LOG_GUEST_ERROR, 209 "pl061_read: Bad offset %x\n", (int)offset); 210 return 0; 211 } 212 213 static void pl061_write(void *opaque, hwaddr offset, 214 uint64_t value, unsigned size) 215 { 216 PL061State *s = (PL061State *)opaque; 217 uint8_t mask; 218 219 if (offset < 0x400) { 220 mask = (offset >> 2) & s->dir; 221 s->data = (s->data & ~mask) | (value & mask); 222 pl061_update(s); 223 return; 224 } 225 if (offset >= s->rsvd_start) { 226 goto err_out; 227 } 228 switch (offset) { 229 case 0x400: /* Direction */ 230 s->dir = value & 0xff; 231 break; 232 case 0x404: /* Interrupt sense */ 233 s->isense = value & 0xff; 234 break; 235 case 0x408: /* Interrupt both edges */ 236 s->ibe = value & 0xff; 237 break; 238 case 0x40c: /* Interrupt event */ 239 s->iev = value & 0xff; 240 break; 241 case 0x410: /* Interrupt mask */ 242 s->im = value & 0xff; 243 break; 244 case 0x41c: /* Interrupt clear */ 245 s->istate &= ~value; 246 break; 247 case 0x420: /* Alternate function select */ 248 mask = s->cr; 249 s->afsel = (s->afsel & ~mask) | (value & mask); 250 break; 251 case 0x500: /* 2mA drive */ 252 s->dr2r = value & 0xff; 253 break; 254 case 0x504: /* 4mA drive */ 255 s->dr4r = value & 0xff; 256 break; 257 case 0x508: /* 8mA drive */ 258 s->dr8r = value & 0xff; 259 break; 260 case 0x50c: /* Open drain */ 261 s->odr = value & 0xff; 262 break; 263 case 0x510: /* Pull-up */ 264 s->pur = value & 0xff; 265 break; 266 case 0x514: /* Pull-down */ 267 s->pdr = value & 0xff; 268 break; 269 case 0x518: /* Slew rate control */ 270 s->slr = value & 0xff; 271 break; 272 case 0x51c: /* Digital enable */ 273 s->den = value & 0xff; 274 break; 275 case 0x520: /* Lock */ 276 s->locked = (value != 0xacce551); 277 break; 278 case 0x524: /* Commit */ 279 if (!s->locked) 280 s->cr = value & 0xff; 281 break; 282 case 0x528: 283 s->amsel = value & 0xff; 284 break; 285 default: 286 goto err_out; 287 } 288 pl061_update(s); 289 return; 290 err_out: 291 qemu_log_mask(LOG_GUEST_ERROR, 292 "pl061_write: Bad offset %x\n", (int)offset); 293 } 294 295 static void pl061_reset(DeviceState *dev) 296 { 297 PL061State *s = PL061(dev); 298 299 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 300 s->data = 0; 301 s->old_out_data = 0; 302 s->old_in_data = 0; 303 s->dir = 0; 304 s->isense = 0; 305 s->ibe = 0; 306 s->iev = 0; 307 s->im = 0; 308 s->istate = 0; 309 s->afsel = 0; 310 s->dr2r = 0xff; 311 s->dr4r = 0; 312 s->dr8r = 0; 313 s->odr = 0; 314 s->pur = 0; 315 s->pdr = 0; 316 s->slr = 0; 317 s->den = 0; 318 s->locked = 1; 319 s->cr = 0xff; 320 s->amsel = 0; 321 } 322 323 static void pl061_set_irq(void * opaque, int irq, int level) 324 { 325 PL061State *s = (PL061State *)opaque; 326 uint8_t mask; 327 328 mask = 1 << irq; 329 if ((s->dir & mask) == 0) { 330 s->data &= ~mask; 331 if (level) 332 s->data |= mask; 333 pl061_update(s); 334 } 335 } 336 337 static const MemoryRegionOps pl061_ops = { 338 .read = pl061_read, 339 .write = pl061_write, 340 .endianness = DEVICE_NATIVE_ENDIAN, 341 }; 342 343 static int pl061_initfn(SysBusDevice *sbd) 344 { 345 DeviceState *dev = DEVICE(sbd); 346 PL061State *s = PL061(dev); 347 348 memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000); 349 sysbus_init_mmio(sbd, &s->iomem); 350 sysbus_init_irq(sbd, &s->irq); 351 qdev_init_gpio_in(dev, pl061_set_irq, 8); 352 qdev_init_gpio_out(dev, s->out, 8); 353 354 return 0; 355 } 356 357 static void pl061_luminary_init(Object *obj) 358 { 359 PL061State *s = PL061(obj); 360 361 s->id = pl061_id_luminary; 362 s->rsvd_start = 0x52c; 363 } 364 365 static void pl061_init(Object *obj) 366 { 367 PL061State *s = PL061(obj); 368 369 s->id = pl061_id; 370 s->rsvd_start = 0x424; 371 } 372 373 static void pl061_class_init(ObjectClass *klass, void *data) 374 { 375 DeviceClass *dc = DEVICE_CLASS(klass); 376 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 377 378 k->init = pl061_initfn; 379 dc->vmsd = &vmstate_pl061; 380 dc->reset = &pl061_reset; 381 } 382 383 static const TypeInfo pl061_info = { 384 .name = TYPE_PL061, 385 .parent = TYPE_SYS_BUS_DEVICE, 386 .instance_size = sizeof(PL061State), 387 .instance_init = pl061_init, 388 .class_init = pl061_class_init, 389 }; 390 391 static const TypeInfo pl061_luminary_info = { 392 .name = "pl061_luminary", 393 .parent = TYPE_PL061, 394 .instance_init = pl061_luminary_init, 395 }; 396 397 static void pl061_register_types(void) 398 { 399 type_register_static(&pl061_info); 400 type_register_static(&pl061_luminary_info); 401 } 402 403 type_init(pl061_register_types) 404