1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/irq.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 #include "qom/object.h" 18 19 //#define DEBUG_PL061 1 20 21 #ifdef DEBUG_PL061 22 #define DPRINTF(fmt, ...) \ 23 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) 24 #define BADF(fmt, ...) \ 25 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 26 #else 27 #define DPRINTF(fmt, ...) do {} while(0) 28 #define BADF(fmt, ...) \ 29 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) 30 #endif 31 32 static const uint8_t pl061_id[12] = 33 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 34 static const uint8_t pl061_id_luminary[12] = 35 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 36 37 #define TYPE_PL061 "pl061" 38 typedef struct PL061State PL061State; 39 DECLARE_INSTANCE_CHECKER(PL061State, PL061, 40 TYPE_PL061) 41 42 #define N_GPIOS 8 43 44 struct PL061State { 45 SysBusDevice parent_obj; 46 47 MemoryRegion iomem; 48 uint32_t locked; 49 uint32_t data; 50 uint32_t old_out_data; 51 uint32_t old_in_data; 52 uint32_t dir; 53 uint32_t isense; 54 uint32_t ibe; 55 uint32_t iev; 56 uint32_t im; 57 uint32_t istate; 58 uint32_t afsel; 59 uint32_t dr2r; 60 uint32_t dr4r; 61 uint32_t dr8r; 62 uint32_t odr; 63 uint32_t pur; 64 uint32_t pdr; 65 uint32_t slr; 66 uint32_t den; 67 uint32_t cr; 68 uint32_t amsel; 69 qemu_irq irq; 70 qemu_irq out[N_GPIOS]; 71 const unsigned char *id; 72 uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ 73 }; 74 75 static const VMStateDescription vmstate_pl061 = { 76 .name = "pl061", 77 .version_id = 4, 78 .minimum_version_id = 4, 79 .fields = (VMStateField[]) { 80 VMSTATE_UINT32(locked, PL061State), 81 VMSTATE_UINT32(data, PL061State), 82 VMSTATE_UINT32(old_out_data, PL061State), 83 VMSTATE_UINT32(old_in_data, PL061State), 84 VMSTATE_UINT32(dir, PL061State), 85 VMSTATE_UINT32(isense, PL061State), 86 VMSTATE_UINT32(ibe, PL061State), 87 VMSTATE_UINT32(iev, PL061State), 88 VMSTATE_UINT32(im, PL061State), 89 VMSTATE_UINT32(istate, PL061State), 90 VMSTATE_UINT32(afsel, PL061State), 91 VMSTATE_UINT32(dr2r, PL061State), 92 VMSTATE_UINT32(dr4r, PL061State), 93 VMSTATE_UINT32(dr8r, PL061State), 94 VMSTATE_UINT32(odr, PL061State), 95 VMSTATE_UINT32(pur, PL061State), 96 VMSTATE_UINT32(pdr, PL061State), 97 VMSTATE_UINT32(slr, PL061State), 98 VMSTATE_UINT32(den, PL061State), 99 VMSTATE_UINT32(cr, PL061State), 100 VMSTATE_UINT32_V(amsel, PL061State, 2), 101 VMSTATE_END_OF_LIST() 102 } 103 }; 104 105 static void pl061_update(PL061State *s) 106 { 107 uint8_t changed; 108 uint8_t mask; 109 uint8_t out; 110 int i; 111 112 DPRINTF("dir = %d, data = %d\n", s->dir, s->data); 113 114 /* Outputs float high. */ 115 /* FIXME: This is board dependent. */ 116 out = (s->data & s->dir) | ~s->dir; 117 changed = s->old_out_data ^ out; 118 if (changed) { 119 s->old_out_data = out; 120 for (i = 0; i < N_GPIOS; i++) { 121 mask = 1 << i; 122 if (changed & mask) { 123 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); 124 qemu_set_irq(s->out[i], (out & mask) != 0); 125 } 126 } 127 } 128 129 /* Inputs */ 130 changed = (s->old_in_data ^ s->data) & ~s->dir; 131 if (changed) { 132 s->old_in_data = s->data; 133 for (i = 0; i < N_GPIOS; i++) { 134 mask = 1 << i; 135 if (changed & mask) { 136 DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); 137 138 if (!(s->isense & mask)) { 139 /* Edge interrupt */ 140 if (s->ibe & mask) { 141 /* Any edge triggers the interrupt */ 142 s->istate |= mask; 143 } else { 144 /* Edge is selected by IEV */ 145 s->istate |= ~(s->data ^ s->iev) & mask; 146 } 147 } 148 } 149 } 150 } 151 152 /* Level interrupt */ 153 s->istate |= ~(s->data ^ s->iev) & s->isense; 154 155 DPRINTF("istate = %02X\n", s->istate); 156 157 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 158 } 159 160 static uint64_t pl061_read(void *opaque, hwaddr offset, 161 unsigned size) 162 { 163 PL061State *s = (PL061State *)opaque; 164 165 if (offset < 0x400) { 166 return s->data & (offset >> 2); 167 } 168 if (offset >= s->rsvd_start && offset <= 0xfcc) { 169 goto err_out; 170 } 171 if (offset >= 0xfd0 && offset < 0x1000) { 172 return s->id[(offset - 0xfd0) >> 2]; 173 } 174 switch (offset) { 175 case 0x400: /* Direction */ 176 return s->dir; 177 case 0x404: /* Interrupt sense */ 178 return s->isense; 179 case 0x408: /* Interrupt both edges */ 180 return s->ibe; 181 case 0x40c: /* Interrupt event */ 182 return s->iev; 183 case 0x410: /* Interrupt mask */ 184 return s->im; 185 case 0x414: /* Raw interrupt status */ 186 return s->istate; 187 case 0x418: /* Masked interrupt status */ 188 return s->istate & s->im; 189 case 0x420: /* Alternate function select */ 190 return s->afsel; 191 case 0x500: /* 2mA drive */ 192 return s->dr2r; 193 case 0x504: /* 4mA drive */ 194 return s->dr4r; 195 case 0x508: /* 8mA drive */ 196 return s->dr8r; 197 case 0x50c: /* Open drain */ 198 return s->odr; 199 case 0x510: /* Pull-up */ 200 return s->pur; 201 case 0x514: /* Pull-down */ 202 return s->pdr; 203 case 0x518: /* Slew rate control */ 204 return s->slr; 205 case 0x51c: /* Digital enable */ 206 return s->den; 207 case 0x520: /* Lock */ 208 return s->locked; 209 case 0x524: /* Commit */ 210 return s->cr; 211 case 0x528: /* Analog mode select */ 212 return s->amsel; 213 default: 214 break; 215 } 216 err_out: 217 qemu_log_mask(LOG_GUEST_ERROR, 218 "pl061_read: Bad offset %x\n", (int)offset); 219 return 0; 220 } 221 222 static void pl061_write(void *opaque, hwaddr offset, 223 uint64_t value, unsigned size) 224 { 225 PL061State *s = (PL061State *)opaque; 226 uint8_t mask; 227 228 if (offset < 0x400) { 229 mask = (offset >> 2) & s->dir; 230 s->data = (s->data & ~mask) | (value & mask); 231 pl061_update(s); 232 return; 233 } 234 if (offset >= s->rsvd_start) { 235 goto err_out; 236 } 237 switch (offset) { 238 case 0x400: /* Direction */ 239 s->dir = value & 0xff; 240 break; 241 case 0x404: /* Interrupt sense */ 242 s->isense = value & 0xff; 243 break; 244 case 0x408: /* Interrupt both edges */ 245 s->ibe = value & 0xff; 246 break; 247 case 0x40c: /* Interrupt event */ 248 s->iev = value & 0xff; 249 break; 250 case 0x410: /* Interrupt mask */ 251 s->im = value & 0xff; 252 break; 253 case 0x41c: /* Interrupt clear */ 254 s->istate &= ~value; 255 break; 256 case 0x420: /* Alternate function select */ 257 mask = s->cr; 258 s->afsel = (s->afsel & ~mask) | (value & mask); 259 break; 260 case 0x500: /* 2mA drive */ 261 s->dr2r = value & 0xff; 262 break; 263 case 0x504: /* 4mA drive */ 264 s->dr4r = value & 0xff; 265 break; 266 case 0x508: /* 8mA drive */ 267 s->dr8r = value & 0xff; 268 break; 269 case 0x50c: /* Open drain */ 270 s->odr = value & 0xff; 271 break; 272 case 0x510: /* Pull-up */ 273 s->pur = value & 0xff; 274 break; 275 case 0x514: /* Pull-down */ 276 s->pdr = value & 0xff; 277 break; 278 case 0x518: /* Slew rate control */ 279 s->slr = value & 0xff; 280 break; 281 case 0x51c: /* Digital enable */ 282 s->den = value & 0xff; 283 break; 284 case 0x520: /* Lock */ 285 s->locked = (value != 0xacce551); 286 break; 287 case 0x524: /* Commit */ 288 if (!s->locked) 289 s->cr = value & 0xff; 290 break; 291 case 0x528: 292 s->amsel = value & 0xff; 293 break; 294 default: 295 goto err_out; 296 } 297 pl061_update(s); 298 return; 299 err_out: 300 qemu_log_mask(LOG_GUEST_ERROR, 301 "pl061_write: Bad offset %x\n", (int)offset); 302 } 303 304 static void pl061_reset(DeviceState *dev) 305 { 306 PL061State *s = PL061(dev); 307 308 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 309 s->data = 0; 310 s->old_out_data = 0; 311 s->old_in_data = 0; 312 s->dir = 0; 313 s->isense = 0; 314 s->ibe = 0; 315 s->iev = 0; 316 s->im = 0; 317 s->istate = 0; 318 s->afsel = 0; 319 s->dr2r = 0xff; 320 s->dr4r = 0; 321 s->dr8r = 0; 322 s->odr = 0; 323 s->pur = 0; 324 s->pdr = 0; 325 s->slr = 0; 326 s->den = 0; 327 s->locked = 1; 328 s->cr = 0xff; 329 s->amsel = 0; 330 } 331 332 static void pl061_set_irq(void * opaque, int irq, int level) 333 { 334 PL061State *s = (PL061State *)opaque; 335 uint8_t mask; 336 337 mask = 1 << irq; 338 if ((s->dir & mask) == 0) { 339 s->data &= ~mask; 340 if (level) 341 s->data |= mask; 342 pl061_update(s); 343 } 344 } 345 346 static const MemoryRegionOps pl061_ops = { 347 .read = pl061_read, 348 .write = pl061_write, 349 .endianness = DEVICE_NATIVE_ENDIAN, 350 }; 351 352 static void pl061_luminary_init(Object *obj) 353 { 354 PL061State *s = PL061(obj); 355 356 s->id = pl061_id_luminary; 357 s->rsvd_start = 0x52c; 358 } 359 360 static void pl061_init(Object *obj) 361 { 362 PL061State *s = PL061(obj); 363 DeviceState *dev = DEVICE(obj); 364 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 365 366 s->id = pl061_id; 367 s->rsvd_start = 0x424; 368 369 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); 370 sysbus_init_mmio(sbd, &s->iomem); 371 sysbus_init_irq(sbd, &s->irq); 372 qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS); 373 qdev_init_gpio_out(dev, s->out, N_GPIOS); 374 } 375 376 static void pl061_class_init(ObjectClass *klass, void *data) 377 { 378 DeviceClass *dc = DEVICE_CLASS(klass); 379 380 dc->vmsd = &vmstate_pl061; 381 dc->reset = &pl061_reset; 382 } 383 384 static const TypeInfo pl061_info = { 385 .name = TYPE_PL061, 386 .parent = TYPE_SYS_BUS_DEVICE, 387 .instance_size = sizeof(PL061State), 388 .instance_init = pl061_init, 389 .class_init = pl061_class_init, 390 }; 391 392 static const TypeInfo pl061_luminary_info = { 393 .name = "pl061_luminary", 394 .parent = TYPE_PL061, 395 .instance_init = pl061_luminary_init, 396 }; 397 398 static void pl061_register_types(void) 399 { 400 type_register_static(&pl061_info); 401 type_register_static(&pl061_luminary_info); 402 } 403 404 type_init(pl061_register_types) 405