1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/irq.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 18 //#define DEBUG_PL061 1 19 20 #ifdef DEBUG_PL061 21 #define DPRINTF(fmt, ...) \ 22 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) 23 #define BADF(fmt, ...) \ 24 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 25 #else 26 #define DPRINTF(fmt, ...) do {} while(0) 27 #define BADF(fmt, ...) \ 28 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) 29 #endif 30 31 static const uint8_t pl061_id[12] = 32 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 33 static const uint8_t pl061_id_luminary[12] = 34 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 35 36 #define TYPE_PL061 "pl061" 37 #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061) 38 39 typedef struct PL061State { 40 SysBusDevice parent_obj; 41 42 MemoryRegion iomem; 43 uint32_t locked; 44 uint32_t data; 45 uint32_t old_out_data; 46 uint32_t old_in_data; 47 uint32_t dir; 48 uint32_t isense; 49 uint32_t ibe; 50 uint32_t iev; 51 uint32_t im; 52 uint32_t istate; 53 uint32_t afsel; 54 uint32_t dr2r; 55 uint32_t dr4r; 56 uint32_t dr8r; 57 uint32_t odr; 58 uint32_t pur; 59 uint32_t pdr; 60 uint32_t slr; 61 uint32_t den; 62 uint32_t cr; 63 uint32_t amsel; 64 qemu_irq irq; 65 qemu_irq out[8]; 66 const unsigned char *id; 67 uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ 68 } PL061State; 69 70 static const VMStateDescription vmstate_pl061 = { 71 .name = "pl061", 72 .version_id = 4, 73 .minimum_version_id = 4, 74 .fields = (VMStateField[]) { 75 VMSTATE_UINT32(locked, PL061State), 76 VMSTATE_UINT32(data, PL061State), 77 VMSTATE_UINT32(old_out_data, PL061State), 78 VMSTATE_UINT32(old_in_data, PL061State), 79 VMSTATE_UINT32(dir, PL061State), 80 VMSTATE_UINT32(isense, PL061State), 81 VMSTATE_UINT32(ibe, PL061State), 82 VMSTATE_UINT32(iev, PL061State), 83 VMSTATE_UINT32(im, PL061State), 84 VMSTATE_UINT32(istate, PL061State), 85 VMSTATE_UINT32(afsel, PL061State), 86 VMSTATE_UINT32(dr2r, PL061State), 87 VMSTATE_UINT32(dr4r, PL061State), 88 VMSTATE_UINT32(dr8r, PL061State), 89 VMSTATE_UINT32(odr, PL061State), 90 VMSTATE_UINT32(pur, PL061State), 91 VMSTATE_UINT32(pdr, PL061State), 92 VMSTATE_UINT32(slr, PL061State), 93 VMSTATE_UINT32(den, PL061State), 94 VMSTATE_UINT32(cr, PL061State), 95 VMSTATE_UINT32_V(amsel, PL061State, 2), 96 VMSTATE_END_OF_LIST() 97 } 98 }; 99 100 static void pl061_update(PL061State *s) 101 { 102 uint8_t changed; 103 uint8_t mask; 104 uint8_t out; 105 int i; 106 107 DPRINTF("dir = %d, data = %d\n", s->dir, s->data); 108 109 /* Outputs float high. */ 110 /* FIXME: This is board dependent. */ 111 out = (s->data & s->dir) | ~s->dir; 112 changed = s->old_out_data ^ out; 113 if (changed) { 114 s->old_out_data = out; 115 for (i = 0; i < 8; i++) { 116 mask = 1 << i; 117 if (changed & mask) { 118 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); 119 qemu_set_irq(s->out[i], (out & mask) != 0); 120 } 121 } 122 } 123 124 /* Inputs */ 125 changed = (s->old_in_data ^ s->data) & ~s->dir; 126 if (changed) { 127 s->old_in_data = s->data; 128 for (i = 0; i < 8; i++) { 129 mask = 1 << i; 130 if (changed & mask) { 131 DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); 132 133 if (!(s->isense & mask)) { 134 /* Edge interrupt */ 135 if (s->ibe & mask) { 136 /* Any edge triggers the interrupt */ 137 s->istate |= mask; 138 } else { 139 /* Edge is selected by IEV */ 140 s->istate |= ~(s->data ^ s->iev) & mask; 141 } 142 } 143 } 144 } 145 } 146 147 /* Level interrupt */ 148 s->istate |= ~(s->data ^ s->iev) & s->isense; 149 150 DPRINTF("istate = %02X\n", s->istate); 151 152 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 153 } 154 155 static uint64_t pl061_read(void *opaque, hwaddr offset, 156 unsigned size) 157 { 158 PL061State *s = (PL061State *)opaque; 159 160 if (offset < 0x400) { 161 return s->data & (offset >> 2); 162 } 163 if (offset >= s->rsvd_start && offset <= 0xfcc) { 164 goto err_out; 165 } 166 if (offset >= 0xfd0 && offset < 0x1000) { 167 return s->id[(offset - 0xfd0) >> 2]; 168 } 169 switch (offset) { 170 case 0x400: /* Direction */ 171 return s->dir; 172 case 0x404: /* Interrupt sense */ 173 return s->isense; 174 case 0x408: /* Interrupt both edges */ 175 return s->ibe; 176 case 0x40c: /* Interrupt event */ 177 return s->iev; 178 case 0x410: /* Interrupt mask */ 179 return s->im; 180 case 0x414: /* Raw interrupt status */ 181 return s->istate; 182 case 0x418: /* Masked interrupt status */ 183 return s->istate & s->im; 184 case 0x420: /* Alternate function select */ 185 return s->afsel; 186 case 0x500: /* 2mA drive */ 187 return s->dr2r; 188 case 0x504: /* 4mA drive */ 189 return s->dr4r; 190 case 0x508: /* 8mA drive */ 191 return s->dr8r; 192 case 0x50c: /* Open drain */ 193 return s->odr; 194 case 0x510: /* Pull-up */ 195 return s->pur; 196 case 0x514: /* Pull-down */ 197 return s->pdr; 198 case 0x518: /* Slew rate control */ 199 return s->slr; 200 case 0x51c: /* Digital enable */ 201 return s->den; 202 case 0x520: /* Lock */ 203 return s->locked; 204 case 0x524: /* Commit */ 205 return s->cr; 206 case 0x528: /* Analog mode select */ 207 return s->amsel; 208 default: 209 break; 210 } 211 err_out: 212 qemu_log_mask(LOG_GUEST_ERROR, 213 "pl061_read: Bad offset %x\n", (int)offset); 214 return 0; 215 } 216 217 static void pl061_write(void *opaque, hwaddr offset, 218 uint64_t value, unsigned size) 219 { 220 PL061State *s = (PL061State *)opaque; 221 uint8_t mask; 222 223 if (offset < 0x400) { 224 mask = (offset >> 2) & s->dir; 225 s->data = (s->data & ~mask) | (value & mask); 226 pl061_update(s); 227 return; 228 } 229 if (offset >= s->rsvd_start) { 230 goto err_out; 231 } 232 switch (offset) { 233 case 0x400: /* Direction */ 234 s->dir = value & 0xff; 235 break; 236 case 0x404: /* Interrupt sense */ 237 s->isense = value & 0xff; 238 break; 239 case 0x408: /* Interrupt both edges */ 240 s->ibe = value & 0xff; 241 break; 242 case 0x40c: /* Interrupt event */ 243 s->iev = value & 0xff; 244 break; 245 case 0x410: /* Interrupt mask */ 246 s->im = value & 0xff; 247 break; 248 case 0x41c: /* Interrupt clear */ 249 s->istate &= ~value; 250 break; 251 case 0x420: /* Alternate function select */ 252 mask = s->cr; 253 s->afsel = (s->afsel & ~mask) | (value & mask); 254 break; 255 case 0x500: /* 2mA drive */ 256 s->dr2r = value & 0xff; 257 break; 258 case 0x504: /* 4mA drive */ 259 s->dr4r = value & 0xff; 260 break; 261 case 0x508: /* 8mA drive */ 262 s->dr8r = value & 0xff; 263 break; 264 case 0x50c: /* Open drain */ 265 s->odr = value & 0xff; 266 break; 267 case 0x510: /* Pull-up */ 268 s->pur = value & 0xff; 269 break; 270 case 0x514: /* Pull-down */ 271 s->pdr = value & 0xff; 272 break; 273 case 0x518: /* Slew rate control */ 274 s->slr = value & 0xff; 275 break; 276 case 0x51c: /* Digital enable */ 277 s->den = value & 0xff; 278 break; 279 case 0x520: /* Lock */ 280 s->locked = (value != 0xacce551); 281 break; 282 case 0x524: /* Commit */ 283 if (!s->locked) 284 s->cr = value & 0xff; 285 break; 286 case 0x528: 287 s->amsel = value & 0xff; 288 break; 289 default: 290 goto err_out; 291 } 292 pl061_update(s); 293 return; 294 err_out: 295 qemu_log_mask(LOG_GUEST_ERROR, 296 "pl061_write: Bad offset %x\n", (int)offset); 297 } 298 299 static void pl061_reset(DeviceState *dev) 300 { 301 PL061State *s = PL061(dev); 302 303 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 304 s->data = 0; 305 s->old_out_data = 0; 306 s->old_in_data = 0; 307 s->dir = 0; 308 s->isense = 0; 309 s->ibe = 0; 310 s->iev = 0; 311 s->im = 0; 312 s->istate = 0; 313 s->afsel = 0; 314 s->dr2r = 0xff; 315 s->dr4r = 0; 316 s->dr8r = 0; 317 s->odr = 0; 318 s->pur = 0; 319 s->pdr = 0; 320 s->slr = 0; 321 s->den = 0; 322 s->locked = 1; 323 s->cr = 0xff; 324 s->amsel = 0; 325 } 326 327 static void pl061_set_irq(void * opaque, int irq, int level) 328 { 329 PL061State *s = (PL061State *)opaque; 330 uint8_t mask; 331 332 mask = 1 << irq; 333 if ((s->dir & mask) == 0) { 334 s->data &= ~mask; 335 if (level) 336 s->data |= mask; 337 pl061_update(s); 338 } 339 } 340 341 static const MemoryRegionOps pl061_ops = { 342 .read = pl061_read, 343 .write = pl061_write, 344 .endianness = DEVICE_NATIVE_ENDIAN, 345 }; 346 347 static void pl061_luminary_init(Object *obj) 348 { 349 PL061State *s = PL061(obj); 350 351 s->id = pl061_id_luminary; 352 s->rsvd_start = 0x52c; 353 } 354 355 static void pl061_init(Object *obj) 356 { 357 PL061State *s = PL061(obj); 358 DeviceState *dev = DEVICE(obj); 359 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 360 361 s->id = pl061_id; 362 s->rsvd_start = 0x424; 363 364 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); 365 sysbus_init_mmio(sbd, &s->iomem); 366 sysbus_init_irq(sbd, &s->irq); 367 qdev_init_gpio_in(dev, pl061_set_irq, 8); 368 qdev_init_gpio_out(dev, s->out, 8); 369 } 370 371 static void pl061_class_init(ObjectClass *klass, void *data) 372 { 373 DeviceClass *dc = DEVICE_CLASS(klass); 374 375 dc->vmsd = &vmstate_pl061; 376 dc->reset = &pl061_reset; 377 } 378 379 static const TypeInfo pl061_info = { 380 .name = TYPE_PL061, 381 .parent = TYPE_SYS_BUS_DEVICE, 382 .instance_size = sizeof(PL061State), 383 .instance_init = pl061_init, 384 .class_init = pl061_class_init, 385 }; 386 387 static const TypeInfo pl061_luminary_info = { 388 .name = "pl061_luminary", 389 .parent = TYPE_PL061, 390 .instance_init = pl061_luminary_init, 391 }; 392 393 static void pl061_register_types(void) 394 { 395 type_register_static(&pl061_info); 396 type_register_static(&pl061_luminary_info); 397 } 398 399 type_init(pl061_register_types) 400