1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/irq.h" 13 #include "hw/sysbus.h" 14 #include "qemu/log.h" 15 #include "qemu/module.h" 16 17 //#define DEBUG_PL061 1 18 19 #ifdef DEBUG_PL061 20 #define DPRINTF(fmt, ...) \ 21 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) 22 #define BADF(fmt, ...) \ 23 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 24 #else 25 #define DPRINTF(fmt, ...) do {} while(0) 26 #define BADF(fmt, ...) \ 27 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) 28 #endif 29 30 static const uint8_t pl061_id[12] = 31 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 32 static const uint8_t pl061_id_luminary[12] = 33 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 34 35 #define TYPE_PL061 "pl061" 36 #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061) 37 38 typedef struct PL061State { 39 SysBusDevice parent_obj; 40 41 MemoryRegion iomem; 42 uint32_t locked; 43 uint32_t data; 44 uint32_t old_out_data; 45 uint32_t old_in_data; 46 uint32_t dir; 47 uint32_t isense; 48 uint32_t ibe; 49 uint32_t iev; 50 uint32_t im; 51 uint32_t istate; 52 uint32_t afsel; 53 uint32_t dr2r; 54 uint32_t dr4r; 55 uint32_t dr8r; 56 uint32_t odr; 57 uint32_t pur; 58 uint32_t pdr; 59 uint32_t slr; 60 uint32_t den; 61 uint32_t cr; 62 uint32_t amsel; 63 qemu_irq irq; 64 qemu_irq out[8]; 65 const unsigned char *id; 66 uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ 67 } PL061State; 68 69 static const VMStateDescription vmstate_pl061 = { 70 .name = "pl061", 71 .version_id = 4, 72 .minimum_version_id = 4, 73 .fields = (VMStateField[]) { 74 VMSTATE_UINT32(locked, PL061State), 75 VMSTATE_UINT32(data, PL061State), 76 VMSTATE_UINT32(old_out_data, PL061State), 77 VMSTATE_UINT32(old_in_data, PL061State), 78 VMSTATE_UINT32(dir, PL061State), 79 VMSTATE_UINT32(isense, PL061State), 80 VMSTATE_UINT32(ibe, PL061State), 81 VMSTATE_UINT32(iev, PL061State), 82 VMSTATE_UINT32(im, PL061State), 83 VMSTATE_UINT32(istate, PL061State), 84 VMSTATE_UINT32(afsel, PL061State), 85 VMSTATE_UINT32(dr2r, PL061State), 86 VMSTATE_UINT32(dr4r, PL061State), 87 VMSTATE_UINT32(dr8r, PL061State), 88 VMSTATE_UINT32(odr, PL061State), 89 VMSTATE_UINT32(pur, PL061State), 90 VMSTATE_UINT32(pdr, PL061State), 91 VMSTATE_UINT32(slr, PL061State), 92 VMSTATE_UINT32(den, PL061State), 93 VMSTATE_UINT32(cr, PL061State), 94 VMSTATE_UINT32_V(amsel, PL061State, 2), 95 VMSTATE_END_OF_LIST() 96 } 97 }; 98 99 static void pl061_update(PL061State *s) 100 { 101 uint8_t changed; 102 uint8_t mask; 103 uint8_t out; 104 int i; 105 106 DPRINTF("dir = %d, data = %d\n", s->dir, s->data); 107 108 /* Outputs float high. */ 109 /* FIXME: This is board dependent. */ 110 out = (s->data & s->dir) | ~s->dir; 111 changed = s->old_out_data ^ out; 112 if (changed) { 113 s->old_out_data = out; 114 for (i = 0; i < 8; i++) { 115 mask = 1 << i; 116 if (changed & mask) { 117 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); 118 qemu_set_irq(s->out[i], (out & mask) != 0); 119 } 120 } 121 } 122 123 /* Inputs */ 124 changed = (s->old_in_data ^ s->data) & ~s->dir; 125 if (changed) { 126 s->old_in_data = s->data; 127 for (i = 0; i < 8; i++) { 128 mask = 1 << i; 129 if (changed & mask) { 130 DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); 131 132 if (!(s->isense & mask)) { 133 /* Edge interrupt */ 134 if (s->ibe & mask) { 135 /* Any edge triggers the interrupt */ 136 s->istate |= mask; 137 } else { 138 /* Edge is selected by IEV */ 139 s->istate |= ~(s->data ^ s->iev) & mask; 140 } 141 } 142 } 143 } 144 } 145 146 /* Level interrupt */ 147 s->istate |= ~(s->data ^ s->iev) & s->isense; 148 149 DPRINTF("istate = %02X\n", s->istate); 150 151 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 152 } 153 154 static uint64_t pl061_read(void *opaque, hwaddr offset, 155 unsigned size) 156 { 157 PL061State *s = (PL061State *)opaque; 158 159 if (offset < 0x400) { 160 return s->data & (offset >> 2); 161 } 162 if (offset >= s->rsvd_start && offset <= 0xfcc) { 163 goto err_out; 164 } 165 if (offset >= 0xfd0 && offset < 0x1000) { 166 return s->id[(offset - 0xfd0) >> 2]; 167 } 168 switch (offset) { 169 case 0x400: /* Direction */ 170 return s->dir; 171 case 0x404: /* Interrupt sense */ 172 return s->isense; 173 case 0x408: /* Interrupt both edges */ 174 return s->ibe; 175 case 0x40c: /* Interrupt event */ 176 return s->iev; 177 case 0x410: /* Interrupt mask */ 178 return s->im; 179 case 0x414: /* Raw interrupt status */ 180 return s->istate; 181 case 0x418: /* Masked interrupt status */ 182 return s->istate & s->im; 183 case 0x420: /* Alternate function select */ 184 return s->afsel; 185 case 0x500: /* 2mA drive */ 186 return s->dr2r; 187 case 0x504: /* 4mA drive */ 188 return s->dr4r; 189 case 0x508: /* 8mA drive */ 190 return s->dr8r; 191 case 0x50c: /* Open drain */ 192 return s->odr; 193 case 0x510: /* Pull-up */ 194 return s->pur; 195 case 0x514: /* Pull-down */ 196 return s->pdr; 197 case 0x518: /* Slew rate control */ 198 return s->slr; 199 case 0x51c: /* Digital enable */ 200 return s->den; 201 case 0x520: /* Lock */ 202 return s->locked; 203 case 0x524: /* Commit */ 204 return s->cr; 205 case 0x528: /* Analog mode select */ 206 return s->amsel; 207 default: 208 break; 209 } 210 err_out: 211 qemu_log_mask(LOG_GUEST_ERROR, 212 "pl061_read: Bad offset %x\n", (int)offset); 213 return 0; 214 } 215 216 static void pl061_write(void *opaque, hwaddr offset, 217 uint64_t value, unsigned size) 218 { 219 PL061State *s = (PL061State *)opaque; 220 uint8_t mask; 221 222 if (offset < 0x400) { 223 mask = (offset >> 2) & s->dir; 224 s->data = (s->data & ~mask) | (value & mask); 225 pl061_update(s); 226 return; 227 } 228 if (offset >= s->rsvd_start) { 229 goto err_out; 230 } 231 switch (offset) { 232 case 0x400: /* Direction */ 233 s->dir = value & 0xff; 234 break; 235 case 0x404: /* Interrupt sense */ 236 s->isense = value & 0xff; 237 break; 238 case 0x408: /* Interrupt both edges */ 239 s->ibe = value & 0xff; 240 break; 241 case 0x40c: /* Interrupt event */ 242 s->iev = value & 0xff; 243 break; 244 case 0x410: /* Interrupt mask */ 245 s->im = value & 0xff; 246 break; 247 case 0x41c: /* Interrupt clear */ 248 s->istate &= ~value; 249 break; 250 case 0x420: /* Alternate function select */ 251 mask = s->cr; 252 s->afsel = (s->afsel & ~mask) | (value & mask); 253 break; 254 case 0x500: /* 2mA drive */ 255 s->dr2r = value & 0xff; 256 break; 257 case 0x504: /* 4mA drive */ 258 s->dr4r = value & 0xff; 259 break; 260 case 0x508: /* 8mA drive */ 261 s->dr8r = value & 0xff; 262 break; 263 case 0x50c: /* Open drain */ 264 s->odr = value & 0xff; 265 break; 266 case 0x510: /* Pull-up */ 267 s->pur = value & 0xff; 268 break; 269 case 0x514: /* Pull-down */ 270 s->pdr = value & 0xff; 271 break; 272 case 0x518: /* Slew rate control */ 273 s->slr = value & 0xff; 274 break; 275 case 0x51c: /* Digital enable */ 276 s->den = value & 0xff; 277 break; 278 case 0x520: /* Lock */ 279 s->locked = (value != 0xacce551); 280 break; 281 case 0x524: /* Commit */ 282 if (!s->locked) 283 s->cr = value & 0xff; 284 break; 285 case 0x528: 286 s->amsel = value & 0xff; 287 break; 288 default: 289 goto err_out; 290 } 291 pl061_update(s); 292 return; 293 err_out: 294 qemu_log_mask(LOG_GUEST_ERROR, 295 "pl061_write: Bad offset %x\n", (int)offset); 296 } 297 298 static void pl061_reset(DeviceState *dev) 299 { 300 PL061State *s = PL061(dev); 301 302 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 303 s->data = 0; 304 s->old_out_data = 0; 305 s->old_in_data = 0; 306 s->dir = 0; 307 s->isense = 0; 308 s->ibe = 0; 309 s->iev = 0; 310 s->im = 0; 311 s->istate = 0; 312 s->afsel = 0; 313 s->dr2r = 0xff; 314 s->dr4r = 0; 315 s->dr8r = 0; 316 s->odr = 0; 317 s->pur = 0; 318 s->pdr = 0; 319 s->slr = 0; 320 s->den = 0; 321 s->locked = 1; 322 s->cr = 0xff; 323 s->amsel = 0; 324 } 325 326 static void pl061_set_irq(void * opaque, int irq, int level) 327 { 328 PL061State *s = (PL061State *)opaque; 329 uint8_t mask; 330 331 mask = 1 << irq; 332 if ((s->dir & mask) == 0) { 333 s->data &= ~mask; 334 if (level) 335 s->data |= mask; 336 pl061_update(s); 337 } 338 } 339 340 static const MemoryRegionOps pl061_ops = { 341 .read = pl061_read, 342 .write = pl061_write, 343 .endianness = DEVICE_NATIVE_ENDIAN, 344 }; 345 346 static void pl061_luminary_init(Object *obj) 347 { 348 PL061State *s = PL061(obj); 349 350 s->id = pl061_id_luminary; 351 s->rsvd_start = 0x52c; 352 } 353 354 static void pl061_init(Object *obj) 355 { 356 PL061State *s = PL061(obj); 357 DeviceState *dev = DEVICE(obj); 358 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 359 360 s->id = pl061_id; 361 s->rsvd_start = 0x424; 362 363 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); 364 sysbus_init_mmio(sbd, &s->iomem); 365 sysbus_init_irq(sbd, &s->irq); 366 qdev_init_gpio_in(dev, pl061_set_irq, 8); 367 qdev_init_gpio_out(dev, s->out, 8); 368 } 369 370 static void pl061_class_init(ObjectClass *klass, void *data) 371 { 372 DeviceClass *dc = DEVICE_CLASS(klass); 373 374 dc->vmsd = &vmstate_pl061; 375 dc->reset = &pl061_reset; 376 } 377 378 static const TypeInfo pl061_info = { 379 .name = TYPE_PL061, 380 .parent = TYPE_SYS_BUS_DEVICE, 381 .instance_size = sizeof(PL061State), 382 .instance_init = pl061_init, 383 .class_init = pl061_class_init, 384 }; 385 386 static const TypeInfo pl061_luminary_info = { 387 .name = "pl061_luminary", 388 .parent = TYPE_PL061, 389 .instance_init = pl061_luminary_init, 390 }; 391 392 static void pl061_register_types(void) 393 { 394 type_register_static(&pl061_info); 395 type_register_static(&pl061_luminary_info); 396 } 397 398 type_init(pl061_register_types) 399