1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/sysbus.h" 13 14 //#define DEBUG_PL061 1 15 16 #ifdef DEBUG_PL061 17 #define DPRINTF(fmt, ...) \ 18 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) 19 #define BADF(fmt, ...) \ 20 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 21 #else 22 #define DPRINTF(fmt, ...) do {} while(0) 23 #define BADF(fmt, ...) \ 24 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) 25 #endif 26 27 static const uint8_t pl061_id[12] = 28 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 29 static const uint8_t pl061_id_luminary[12] = 30 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 31 32 #define TYPE_PL061 "pl061" 33 #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061) 34 35 typedef struct PL061State { 36 SysBusDevice parent_obj; 37 38 MemoryRegion iomem; 39 uint32_t locked; 40 uint32_t data; 41 uint32_t old_out_data; 42 uint32_t old_in_data; 43 uint32_t dir; 44 uint32_t isense; 45 uint32_t ibe; 46 uint32_t iev; 47 uint32_t im; 48 uint32_t istate; 49 uint32_t afsel; 50 uint32_t dr2r; 51 uint32_t dr4r; 52 uint32_t dr8r; 53 uint32_t odr; 54 uint32_t pur; 55 uint32_t pdr; 56 uint32_t slr; 57 uint32_t den; 58 uint32_t cr; 59 uint32_t amsel; 60 qemu_irq irq; 61 qemu_irq out[8]; 62 const unsigned char *id; 63 } PL061State; 64 65 static const VMStateDescription vmstate_pl061 = { 66 .name = "pl061", 67 .version_id = 4, 68 .minimum_version_id = 4, 69 .fields = (VMStateField[]) { 70 VMSTATE_UINT32(locked, PL061State), 71 VMSTATE_UINT32(data, PL061State), 72 VMSTATE_UINT32(old_out_data, PL061State), 73 VMSTATE_UINT32(old_in_data, PL061State), 74 VMSTATE_UINT32(dir, PL061State), 75 VMSTATE_UINT32(isense, PL061State), 76 VMSTATE_UINT32(ibe, PL061State), 77 VMSTATE_UINT32(iev, PL061State), 78 VMSTATE_UINT32(im, PL061State), 79 VMSTATE_UINT32(istate, PL061State), 80 VMSTATE_UINT32(afsel, PL061State), 81 VMSTATE_UINT32(dr2r, PL061State), 82 VMSTATE_UINT32(dr4r, PL061State), 83 VMSTATE_UINT32(dr8r, PL061State), 84 VMSTATE_UINT32(odr, PL061State), 85 VMSTATE_UINT32(pur, PL061State), 86 VMSTATE_UINT32(pdr, PL061State), 87 VMSTATE_UINT32(slr, PL061State), 88 VMSTATE_UINT32(den, PL061State), 89 VMSTATE_UINT32(cr, PL061State), 90 VMSTATE_UINT32_V(amsel, PL061State, 2), 91 VMSTATE_END_OF_LIST() 92 } 93 }; 94 95 static void pl061_update(PL061State *s) 96 { 97 uint8_t changed; 98 uint8_t mask; 99 uint8_t out; 100 int i; 101 102 DPRINTF("dir = %d, data = %d\n", s->dir, s->data); 103 104 /* Outputs float high. */ 105 /* FIXME: This is board dependent. */ 106 out = (s->data & s->dir) | ~s->dir; 107 changed = s->old_out_data ^ out; 108 if (changed) { 109 s->old_out_data = out; 110 for (i = 0; i < 8; i++) { 111 mask = 1 << i; 112 if (changed & mask) { 113 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); 114 qemu_set_irq(s->out[i], (out & mask) != 0); 115 } 116 } 117 } 118 119 /* Inputs */ 120 changed = (s->old_in_data ^ s->data) & ~s->dir; 121 if (changed) { 122 s->old_in_data = s->data; 123 for (i = 0; i < 8; i++) { 124 mask = 1 << i; 125 if (changed & mask) { 126 DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); 127 128 if (!(s->isense & mask)) { 129 /* Edge interrupt */ 130 if (s->ibe & mask) { 131 /* Any edge triggers the interrupt */ 132 s->istate |= mask; 133 } else { 134 /* Edge is selected by IEV */ 135 s->istate |= ~(s->data ^ s->iev) & mask; 136 } 137 } 138 } 139 } 140 } 141 142 /* Level interrupt */ 143 s->istate |= ~(s->data ^ s->iev) & s->isense; 144 145 DPRINTF("istate = %02X\n", s->istate); 146 147 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 148 } 149 150 static uint64_t pl061_read(void *opaque, hwaddr offset, 151 unsigned size) 152 { 153 PL061State *s = (PL061State *)opaque; 154 155 if (offset >= 0xfd0 && offset < 0x1000) { 156 return s->id[(offset - 0xfd0) >> 2]; 157 } 158 if (offset < 0x400) { 159 return s->data & (offset >> 2); 160 } 161 switch (offset) { 162 case 0x400: /* Direction */ 163 return s->dir; 164 case 0x404: /* Interrupt sense */ 165 return s->isense; 166 case 0x408: /* Interrupt both edges */ 167 return s->ibe; 168 case 0x40c: /* Interrupt event */ 169 return s->iev; 170 case 0x410: /* Interrupt mask */ 171 return s->im; 172 case 0x414: /* Raw interrupt status */ 173 return s->istate; 174 case 0x418: /* Masked interrupt status */ 175 return s->istate & s->im; 176 case 0x420: /* Alternate function select */ 177 return s->afsel; 178 case 0x500: /* 2mA drive */ 179 return s->dr2r; 180 case 0x504: /* 4mA drive */ 181 return s->dr4r; 182 case 0x508: /* 8mA drive */ 183 return s->dr8r; 184 case 0x50c: /* Open drain */ 185 return s->odr; 186 case 0x510: /* Pull-up */ 187 return s->pur; 188 case 0x514: /* Pull-down */ 189 return s->pdr; 190 case 0x518: /* Slew rate control */ 191 return s->slr; 192 case 0x51c: /* Digital enable */ 193 return s->den; 194 case 0x520: /* Lock */ 195 return s->locked; 196 case 0x524: /* Commit */ 197 return s->cr; 198 case 0x528: /* Analog mode select */ 199 return s->amsel; 200 default: 201 qemu_log_mask(LOG_GUEST_ERROR, 202 "pl061_read: Bad offset %x\n", (int)offset); 203 return 0; 204 } 205 } 206 207 static void pl061_write(void *opaque, hwaddr offset, 208 uint64_t value, unsigned size) 209 { 210 PL061State *s = (PL061State *)opaque; 211 uint8_t mask; 212 213 if (offset < 0x400) { 214 mask = (offset >> 2) & s->dir; 215 s->data = (s->data & ~mask) | (value & mask); 216 pl061_update(s); 217 return; 218 } 219 switch (offset) { 220 case 0x400: /* Direction */ 221 s->dir = value & 0xff; 222 break; 223 case 0x404: /* Interrupt sense */ 224 s->isense = value & 0xff; 225 break; 226 case 0x408: /* Interrupt both edges */ 227 s->ibe = value & 0xff; 228 break; 229 case 0x40c: /* Interrupt event */ 230 s->iev = value & 0xff; 231 break; 232 case 0x410: /* Interrupt mask */ 233 s->im = value & 0xff; 234 break; 235 case 0x41c: /* Interrupt clear */ 236 s->istate &= ~value; 237 break; 238 case 0x420: /* Alternate function select */ 239 mask = s->cr; 240 s->afsel = (s->afsel & ~mask) | (value & mask); 241 break; 242 case 0x500: /* 2mA drive */ 243 s->dr2r = value & 0xff; 244 break; 245 case 0x504: /* 4mA drive */ 246 s->dr4r = value & 0xff; 247 break; 248 case 0x508: /* 8mA drive */ 249 s->dr8r = value & 0xff; 250 break; 251 case 0x50c: /* Open drain */ 252 s->odr = value & 0xff; 253 break; 254 case 0x510: /* Pull-up */ 255 s->pur = value & 0xff; 256 break; 257 case 0x514: /* Pull-down */ 258 s->pdr = value & 0xff; 259 break; 260 case 0x518: /* Slew rate control */ 261 s->slr = value & 0xff; 262 break; 263 case 0x51c: /* Digital enable */ 264 s->den = value & 0xff; 265 break; 266 case 0x520: /* Lock */ 267 s->locked = (value != 0xacce551); 268 break; 269 case 0x524: /* Commit */ 270 if (!s->locked) 271 s->cr = value & 0xff; 272 break; 273 case 0x528: 274 s->amsel = value & 0xff; 275 break; 276 default: 277 qemu_log_mask(LOG_GUEST_ERROR, 278 "pl061_write: Bad offset %x\n", (int)offset); 279 } 280 pl061_update(s); 281 } 282 283 static void pl061_reset(DeviceState *dev) 284 { 285 PL061State *s = PL061(dev); 286 287 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 288 s->data = 0; 289 s->old_out_data = 0; 290 s->old_in_data = 0; 291 s->dir = 0; 292 s->isense = 0; 293 s->ibe = 0; 294 s->iev = 0; 295 s->im = 0; 296 s->istate = 0; 297 s->afsel = 0; 298 s->dr2r = 0xff; 299 s->dr4r = 0; 300 s->dr8r = 0; 301 s->odr = 0; 302 s->pur = 0; 303 s->pdr = 0; 304 s->slr = 0; 305 s->den = 0; 306 s->locked = 1; 307 s->cr = 0xff; 308 s->amsel = 0; 309 } 310 311 static void pl061_set_irq(void * opaque, int irq, int level) 312 { 313 PL061State *s = (PL061State *)opaque; 314 uint8_t mask; 315 316 mask = 1 << irq; 317 if ((s->dir & mask) == 0) { 318 s->data &= ~mask; 319 if (level) 320 s->data |= mask; 321 pl061_update(s); 322 } 323 } 324 325 static const MemoryRegionOps pl061_ops = { 326 .read = pl061_read, 327 .write = pl061_write, 328 .endianness = DEVICE_NATIVE_ENDIAN, 329 }; 330 331 static int pl061_initfn(SysBusDevice *sbd) 332 { 333 DeviceState *dev = DEVICE(sbd); 334 PL061State *s = PL061(dev); 335 336 memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000); 337 sysbus_init_mmio(sbd, &s->iomem); 338 sysbus_init_irq(sbd, &s->irq); 339 qdev_init_gpio_in(dev, pl061_set_irq, 8); 340 qdev_init_gpio_out(dev, s->out, 8); 341 342 return 0; 343 } 344 345 static void pl061_luminary_init(Object *obj) 346 { 347 PL061State *s = PL061(obj); 348 349 s->id = pl061_id_luminary; 350 } 351 352 static void pl061_init(Object *obj) 353 { 354 PL061State *s = PL061(obj); 355 356 s->id = pl061_id; 357 } 358 359 static void pl061_class_init(ObjectClass *klass, void *data) 360 { 361 DeviceClass *dc = DEVICE_CLASS(klass); 362 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 363 364 k->init = pl061_initfn; 365 dc->vmsd = &vmstate_pl061; 366 dc->reset = &pl061_reset; 367 } 368 369 static const TypeInfo pl061_info = { 370 .name = TYPE_PL061, 371 .parent = TYPE_SYS_BUS_DEVICE, 372 .instance_size = sizeof(PL061State), 373 .instance_init = pl061_init, 374 .class_init = pl061_class_init, 375 }; 376 377 static const TypeInfo pl061_luminary_info = { 378 .name = "pl061_luminary", 379 .parent = TYPE_PL061, 380 .instance_init = pl061_luminary_init, 381 }; 382 383 static void pl061_register_types(void) 384 { 385 type_register_static(&pl061_info); 386 type_register_static(&pl061_luminary_info); 387 } 388 389 type_init(pl061_register_types) 390