1 /* 2 * TI OMAP processors GPIO emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * Copyright (C) 2007-2009 Nokia Corporation 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "hw/hw.h" 22 #include "hw/arm/omap.h" 23 #include "hw/sysbus.h" 24 25 struct omap_gpio_s { 26 qemu_irq irq; 27 qemu_irq handler[16]; 28 29 uint16_t inputs; 30 uint16_t outputs; 31 uint16_t dir; 32 uint16_t edge; 33 uint16_t mask; 34 uint16_t ints; 35 uint16_t pins; 36 }; 37 38 #define TYPE_OMAP1_GPIO "omap-gpio" 39 #define OMAP1_GPIO(obj) \ 40 OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO) 41 42 struct omap_gpif_s { 43 SysBusDevice parent_obj; 44 45 MemoryRegion iomem; 46 int mpu_model; 47 void *clk; 48 struct omap_gpio_s omap1; 49 }; 50 51 /* General-Purpose I/O of OMAP1 */ 52 static void omap_gpio_set(void *opaque, int line, int level) 53 { 54 struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1; 55 uint16_t prev = s->inputs; 56 57 if (level) 58 s->inputs |= 1 << line; 59 else 60 s->inputs &= ~(1 << line); 61 62 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & 63 (1 << line) & s->dir & ~s->mask) { 64 s->ints |= 1 << line; 65 qemu_irq_raise(s->irq); 66 } 67 } 68 69 static uint64_t omap_gpio_read(void *opaque, hwaddr addr, 70 unsigned size) 71 { 72 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; 73 int offset = addr & OMAP_MPUI_REG_MASK; 74 75 if (size != 2) { 76 return omap_badwidth_read16(opaque, addr); 77 } 78 79 switch (offset) { 80 case 0x00: /* DATA_INPUT */ 81 return s->inputs & s->pins; 82 83 case 0x04: /* DATA_OUTPUT */ 84 return s->outputs; 85 86 case 0x08: /* DIRECTION_CONTROL */ 87 return s->dir; 88 89 case 0x0c: /* INTERRUPT_CONTROL */ 90 return s->edge; 91 92 case 0x10: /* INTERRUPT_MASK */ 93 return s->mask; 94 95 case 0x14: /* INTERRUPT_STATUS */ 96 return s->ints; 97 98 case 0x18: /* PIN_CONTROL (not in OMAP310) */ 99 OMAP_BAD_REG(addr); 100 return s->pins; 101 } 102 103 OMAP_BAD_REG(addr); 104 return 0; 105 } 106 107 static void omap_gpio_write(void *opaque, hwaddr addr, 108 uint64_t value, unsigned size) 109 { 110 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; 111 int offset = addr & OMAP_MPUI_REG_MASK; 112 uint16_t diff; 113 int ln; 114 115 if (size != 2) { 116 omap_badwidth_write16(opaque, addr, value); 117 return; 118 } 119 120 switch (offset) { 121 case 0x00: /* DATA_INPUT */ 122 OMAP_RO_REG(addr); 123 return; 124 125 case 0x04: /* DATA_OUTPUT */ 126 diff = (s->outputs ^ value) & ~s->dir; 127 s->outputs = value; 128 while ((ln = ffs(diff))) { 129 ln --; 130 if (s->handler[ln]) 131 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 132 diff &= ~(1 << ln); 133 } 134 break; 135 136 case 0x08: /* DIRECTION_CONTROL */ 137 diff = s->outputs & (s->dir ^ value); 138 s->dir = value; 139 140 value = s->outputs & ~s->dir; 141 while ((ln = ffs(diff))) { 142 ln --; 143 if (s->handler[ln]) 144 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 145 diff &= ~(1 << ln); 146 } 147 break; 148 149 case 0x0c: /* INTERRUPT_CONTROL */ 150 s->edge = value; 151 break; 152 153 case 0x10: /* INTERRUPT_MASK */ 154 s->mask = value; 155 break; 156 157 case 0x14: /* INTERRUPT_STATUS */ 158 s->ints &= ~value; 159 if (!s->ints) 160 qemu_irq_lower(s->irq); 161 break; 162 163 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ 164 OMAP_BAD_REG(addr); 165 s->pins = value; 166 break; 167 168 default: 169 OMAP_BAD_REG(addr); 170 return; 171 } 172 } 173 174 /* *Some* sources say the memory region is 32-bit. */ 175 static const MemoryRegionOps omap_gpio_ops = { 176 .read = omap_gpio_read, 177 .write = omap_gpio_write, 178 .endianness = DEVICE_NATIVE_ENDIAN, 179 }; 180 181 static void omap_gpio_reset(struct omap_gpio_s *s) 182 { 183 s->inputs = 0; 184 s->outputs = ~0; 185 s->dir = ~0; 186 s->edge = ~0; 187 s->mask = ~0; 188 s->ints = 0; 189 s->pins = ~0; 190 } 191 192 struct omap2_gpio_s { 193 qemu_irq irq[2]; 194 qemu_irq wkup; 195 qemu_irq *handler; 196 MemoryRegion iomem; 197 198 uint8_t revision; 199 uint8_t config[2]; 200 uint32_t inputs; 201 uint32_t outputs; 202 uint32_t dir; 203 uint32_t level[2]; 204 uint32_t edge[2]; 205 uint32_t mask[2]; 206 uint32_t wumask; 207 uint32_t ints[2]; 208 uint32_t debounce; 209 uint8_t delay; 210 }; 211 212 #define TYPE_OMAP2_GPIO "omap2-gpio" 213 #define OMAP2_GPIO(obj) \ 214 OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO) 215 216 struct omap2_gpif_s { 217 SysBusDevice parent_obj; 218 219 MemoryRegion iomem; 220 int mpu_model; 221 void *iclk; 222 void *fclk[6]; 223 int modulecount; 224 struct omap2_gpio_s *modules; 225 qemu_irq *handler; 226 int autoidle; 227 int gpo; 228 }; 229 230 /* General-Purpose Interface of OMAP2/3 */ 231 static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s, 232 int line) 233 { 234 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); 235 } 236 237 static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line) 238 { 239 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ 240 return; 241 if (!(s->config[0] & (3 << 3))) /* Force Idle */ 242 return; 243 if (!(s->wumask & (1 << line))) 244 return; 245 246 qemu_irq_raise(s->wkup); 247 } 248 249 static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s, 250 uint32_t diff) 251 { 252 int ln; 253 254 s->outputs ^= diff; 255 diff &= ~s->dir; 256 while ((ln = ffs(diff))) { 257 ln --; 258 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1); 259 diff &= ~(1 << ln); 260 } 261 } 262 263 static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line) 264 { 265 s->ints[line] |= s->dir & 266 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); 267 omap2_gpio_module_int_update(s, line); 268 } 269 270 static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line) 271 { 272 s->ints[0] |= 1 << line; 273 omap2_gpio_module_int_update(s, 0); 274 s->ints[1] |= 1 << line; 275 omap2_gpio_module_int_update(s, 1); 276 omap2_gpio_module_wake(s, line); 277 } 278 279 static void omap2_gpio_set(void *opaque, int line, int level) 280 { 281 struct omap2_gpif_s *p = opaque; 282 struct omap2_gpio_s *s = &p->modules[line >> 5]; 283 284 line &= 31; 285 if (level) { 286 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) 287 omap2_gpio_module_int(s, line); 288 s->inputs |= 1 << line; 289 } else { 290 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) 291 omap2_gpio_module_int(s, line); 292 s->inputs &= ~(1 << line); 293 } 294 } 295 296 static void omap2_gpio_module_reset(struct omap2_gpio_s *s) 297 { 298 s->config[0] = 0; 299 s->config[1] = 2; 300 s->ints[0] = 0; 301 s->ints[1] = 0; 302 s->mask[0] = 0; 303 s->mask[1] = 0; 304 s->wumask = 0; 305 s->dir = ~0; 306 s->level[0] = 0; 307 s->level[1] = 0; 308 s->edge[0] = 0; 309 s->edge[1] = 0; 310 s->debounce = 0; 311 s->delay = 0; 312 } 313 314 static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr) 315 { 316 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; 317 318 switch (addr) { 319 case 0x00: /* GPIO_REVISION */ 320 return s->revision; 321 322 case 0x10: /* GPIO_SYSCONFIG */ 323 return s->config[0]; 324 325 case 0x14: /* GPIO_SYSSTATUS */ 326 return 0x01; 327 328 case 0x18: /* GPIO_IRQSTATUS1 */ 329 return s->ints[0]; 330 331 case 0x1c: /* GPIO_IRQENABLE1 */ 332 case 0x60: /* GPIO_CLEARIRQENABLE1 */ 333 case 0x64: /* GPIO_SETIRQENABLE1 */ 334 return s->mask[0]; 335 336 case 0x20: /* GPIO_WAKEUPENABLE */ 337 case 0x80: /* GPIO_CLEARWKUENA */ 338 case 0x84: /* GPIO_SETWKUENA */ 339 return s->wumask; 340 341 case 0x28: /* GPIO_IRQSTATUS2 */ 342 return s->ints[1]; 343 344 case 0x2c: /* GPIO_IRQENABLE2 */ 345 case 0x70: /* GPIO_CLEARIRQENABLE2 */ 346 case 0x74: /* GPIO_SETIREQNEABLE2 */ 347 return s->mask[1]; 348 349 case 0x30: /* GPIO_CTRL */ 350 return s->config[1]; 351 352 case 0x34: /* GPIO_OE */ 353 return s->dir; 354 355 case 0x38: /* GPIO_DATAIN */ 356 return s->inputs; 357 358 case 0x3c: /* GPIO_DATAOUT */ 359 case 0x90: /* GPIO_CLEARDATAOUT */ 360 case 0x94: /* GPIO_SETDATAOUT */ 361 return s->outputs; 362 363 case 0x40: /* GPIO_LEVELDETECT0 */ 364 return s->level[0]; 365 366 case 0x44: /* GPIO_LEVELDETECT1 */ 367 return s->level[1]; 368 369 case 0x48: /* GPIO_RISINGDETECT */ 370 return s->edge[0]; 371 372 case 0x4c: /* GPIO_FALLINGDETECT */ 373 return s->edge[1]; 374 375 case 0x50: /* GPIO_DEBOUNCENABLE */ 376 return s->debounce; 377 378 case 0x54: /* GPIO_DEBOUNCINGTIME */ 379 return s->delay; 380 } 381 382 OMAP_BAD_REG(addr); 383 return 0; 384 } 385 386 static void omap2_gpio_module_write(void *opaque, hwaddr addr, 387 uint32_t value) 388 { 389 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; 390 uint32_t diff; 391 int ln; 392 393 switch (addr) { 394 case 0x00: /* GPIO_REVISION */ 395 case 0x14: /* GPIO_SYSSTATUS */ 396 case 0x38: /* GPIO_DATAIN */ 397 OMAP_RO_REG(addr); 398 break; 399 400 case 0x10: /* GPIO_SYSCONFIG */ 401 if (((value >> 3) & 3) == 3) 402 fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__); 403 if (value & 2) 404 omap2_gpio_module_reset(s); 405 s->config[0] = value & 0x1d; 406 break; 407 408 case 0x18: /* GPIO_IRQSTATUS1 */ 409 if (s->ints[0] & value) { 410 s->ints[0] &= ~value; 411 omap2_gpio_module_level_update(s, 0); 412 } 413 break; 414 415 case 0x1c: /* GPIO_IRQENABLE1 */ 416 s->mask[0] = value; 417 omap2_gpio_module_int_update(s, 0); 418 break; 419 420 case 0x20: /* GPIO_WAKEUPENABLE */ 421 s->wumask = value; 422 break; 423 424 case 0x28: /* GPIO_IRQSTATUS2 */ 425 if (s->ints[1] & value) { 426 s->ints[1] &= ~value; 427 omap2_gpio_module_level_update(s, 1); 428 } 429 break; 430 431 case 0x2c: /* GPIO_IRQENABLE2 */ 432 s->mask[1] = value; 433 omap2_gpio_module_int_update(s, 1); 434 break; 435 436 case 0x30: /* GPIO_CTRL */ 437 s->config[1] = value & 7; 438 break; 439 440 case 0x34: /* GPIO_OE */ 441 diff = s->outputs & (s->dir ^ value); 442 s->dir = value; 443 444 value = s->outputs & ~s->dir; 445 while ((ln = ffs(diff))) { 446 diff &= ~(1 <<-- ln); 447 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 448 } 449 450 omap2_gpio_module_level_update(s, 0); 451 omap2_gpio_module_level_update(s, 1); 452 break; 453 454 case 0x3c: /* GPIO_DATAOUT */ 455 omap2_gpio_module_out_update(s, s->outputs ^ value); 456 break; 457 458 case 0x40: /* GPIO_LEVELDETECT0 */ 459 s->level[0] = value; 460 omap2_gpio_module_level_update(s, 0); 461 omap2_gpio_module_level_update(s, 1); 462 break; 463 464 case 0x44: /* GPIO_LEVELDETECT1 */ 465 s->level[1] = value; 466 omap2_gpio_module_level_update(s, 0); 467 omap2_gpio_module_level_update(s, 1); 468 break; 469 470 case 0x48: /* GPIO_RISINGDETECT */ 471 s->edge[0] = value; 472 break; 473 474 case 0x4c: /* GPIO_FALLINGDETECT */ 475 s->edge[1] = value; 476 break; 477 478 case 0x50: /* GPIO_DEBOUNCENABLE */ 479 s->debounce = value; 480 break; 481 482 case 0x54: /* GPIO_DEBOUNCINGTIME */ 483 s->delay = value; 484 break; 485 486 case 0x60: /* GPIO_CLEARIRQENABLE1 */ 487 s->mask[0] &= ~value; 488 omap2_gpio_module_int_update(s, 0); 489 break; 490 491 case 0x64: /* GPIO_SETIRQENABLE1 */ 492 s->mask[0] |= value; 493 omap2_gpio_module_int_update(s, 0); 494 break; 495 496 case 0x70: /* GPIO_CLEARIRQENABLE2 */ 497 s->mask[1] &= ~value; 498 omap2_gpio_module_int_update(s, 1); 499 break; 500 501 case 0x74: /* GPIO_SETIREQNEABLE2 */ 502 s->mask[1] |= value; 503 omap2_gpio_module_int_update(s, 1); 504 break; 505 506 case 0x80: /* GPIO_CLEARWKUENA */ 507 s->wumask &= ~value; 508 break; 509 510 case 0x84: /* GPIO_SETWKUENA */ 511 s->wumask |= value; 512 break; 513 514 case 0x90: /* GPIO_CLEARDATAOUT */ 515 omap2_gpio_module_out_update(s, s->outputs & value); 516 break; 517 518 case 0x94: /* GPIO_SETDATAOUT */ 519 omap2_gpio_module_out_update(s, ~s->outputs & value); 520 break; 521 522 default: 523 OMAP_BAD_REG(addr); 524 return; 525 } 526 } 527 528 static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr) 529 { 530 return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3); 531 } 532 533 static void omap2_gpio_module_writep(void *opaque, hwaddr addr, 534 uint32_t value) 535 { 536 uint32_t cur = 0; 537 uint32_t mask = 0xffff; 538 539 switch (addr & ~3) { 540 case 0x00: /* GPIO_REVISION */ 541 case 0x14: /* GPIO_SYSSTATUS */ 542 case 0x38: /* GPIO_DATAIN */ 543 OMAP_RO_REG(addr); 544 break; 545 546 case 0x10: /* GPIO_SYSCONFIG */ 547 case 0x1c: /* GPIO_IRQENABLE1 */ 548 case 0x20: /* GPIO_WAKEUPENABLE */ 549 case 0x2c: /* GPIO_IRQENABLE2 */ 550 case 0x30: /* GPIO_CTRL */ 551 case 0x34: /* GPIO_OE */ 552 case 0x3c: /* GPIO_DATAOUT */ 553 case 0x40: /* GPIO_LEVELDETECT0 */ 554 case 0x44: /* GPIO_LEVELDETECT1 */ 555 case 0x48: /* GPIO_RISINGDETECT */ 556 case 0x4c: /* GPIO_FALLINGDETECT */ 557 case 0x50: /* GPIO_DEBOUNCENABLE */ 558 case 0x54: /* GPIO_DEBOUNCINGTIME */ 559 cur = omap2_gpio_module_read(opaque, addr & ~3) & 560 ~(mask << ((addr & 3) << 3)); 561 562 /* Fall through. */ 563 case 0x18: /* GPIO_IRQSTATUS1 */ 564 case 0x28: /* GPIO_IRQSTATUS2 */ 565 case 0x60: /* GPIO_CLEARIRQENABLE1 */ 566 case 0x64: /* GPIO_SETIRQENABLE1 */ 567 case 0x70: /* GPIO_CLEARIRQENABLE2 */ 568 case 0x74: /* GPIO_SETIREQNEABLE2 */ 569 case 0x80: /* GPIO_CLEARWKUENA */ 570 case 0x84: /* GPIO_SETWKUENA */ 571 case 0x90: /* GPIO_CLEARDATAOUT */ 572 case 0x94: /* GPIO_SETDATAOUT */ 573 value <<= (addr & 3) << 3; 574 omap2_gpio_module_write(opaque, addr, cur | value); 575 break; 576 577 default: 578 OMAP_BAD_REG(addr); 579 return; 580 } 581 } 582 583 static const MemoryRegionOps omap2_gpio_module_ops = { 584 .old_mmio = { 585 .read = { 586 omap2_gpio_module_readp, 587 omap2_gpio_module_readp, 588 omap2_gpio_module_read, 589 }, 590 .write = { 591 omap2_gpio_module_writep, 592 omap2_gpio_module_writep, 593 omap2_gpio_module_write, 594 }, 595 }, 596 .endianness = DEVICE_NATIVE_ENDIAN, 597 }; 598 599 static void omap_gpif_reset(DeviceState *dev) 600 { 601 struct omap_gpif_s *s = OMAP1_GPIO(dev); 602 603 omap_gpio_reset(&s->omap1); 604 } 605 606 static void omap2_gpif_reset(DeviceState *dev) 607 { 608 struct omap2_gpif_s *s = OMAP2_GPIO(dev); 609 int i; 610 611 for (i = 0; i < s->modulecount; i++) { 612 omap2_gpio_module_reset(&s->modules[i]); 613 } 614 s->autoidle = 0; 615 s->gpo = 0; 616 } 617 618 static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, 619 unsigned size) 620 { 621 struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; 622 623 switch (addr) { 624 case 0x00: /* IPGENERICOCPSPL_REVISION */ 625 return 0x18; 626 627 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ 628 return s->autoidle; 629 630 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ 631 return 0x01; 632 633 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ 634 return 0x00; 635 636 case 0x40: /* IPGENERICOCPSPL_GPO */ 637 return s->gpo; 638 639 case 0x50: /* IPGENERICOCPSPL_GPI */ 640 return 0x00; 641 } 642 643 OMAP_BAD_REG(addr); 644 return 0; 645 } 646 647 static void omap2_gpif_top_write(void *opaque, hwaddr addr, 648 uint64_t value, unsigned size) 649 { 650 struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; 651 652 switch (addr) { 653 case 0x00: /* IPGENERICOCPSPL_REVISION */ 654 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ 655 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ 656 case 0x50: /* IPGENERICOCPSPL_GPI */ 657 OMAP_RO_REG(addr); 658 break; 659 660 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ 661 if (value & (1 << 1)) /* SOFTRESET */ 662 omap2_gpif_reset(DEVICE(s)); 663 s->autoidle = value & 1; 664 break; 665 666 case 0x40: /* IPGENERICOCPSPL_GPO */ 667 s->gpo = value & 1; 668 break; 669 670 default: 671 OMAP_BAD_REG(addr); 672 return; 673 } 674 } 675 676 static const MemoryRegionOps omap2_gpif_top_ops = { 677 .read = omap2_gpif_top_read, 678 .write = omap2_gpif_top_write, 679 .endianness = DEVICE_NATIVE_ENDIAN, 680 }; 681 682 static int omap_gpio_init(SysBusDevice *sbd) 683 { 684 DeviceState *dev = DEVICE(sbd); 685 struct omap_gpif_s *s = OMAP1_GPIO(dev); 686 687 if (!s->clk) { 688 hw_error("omap-gpio: clk not connected\n"); 689 } 690 qdev_init_gpio_in(dev, omap_gpio_set, 16); 691 qdev_init_gpio_out(dev, s->omap1.handler, 16); 692 sysbus_init_irq(sbd, &s->omap1.irq); 693 memory_region_init_io(&s->iomem, OBJECT(s), &omap_gpio_ops, &s->omap1, 694 "omap.gpio", 0x1000); 695 sysbus_init_mmio(sbd, &s->iomem); 696 return 0; 697 } 698 699 static int omap2_gpio_init(SysBusDevice *sbd) 700 { 701 DeviceState *dev = DEVICE(sbd); 702 struct omap2_gpif_s *s = OMAP2_GPIO(dev); 703 int i; 704 705 if (!s->iclk) { 706 hw_error("omap2-gpio: iclk not connected\n"); 707 } 708 if (s->mpu_model < omap3430) { 709 s->modulecount = (s->mpu_model < omap2430) ? 4 : 5; 710 memory_region_init_io(&s->iomem, OBJECT(s), &omap2_gpif_top_ops, s, 711 "omap2.gpio", 0x1000); 712 sysbus_init_mmio(sbd, &s->iomem); 713 } else { 714 s->modulecount = 6; 715 } 716 s->modules = g_malloc0(s->modulecount * sizeof(struct omap2_gpio_s)); 717 s->handler = g_malloc0(s->modulecount * 32 * sizeof(qemu_irq)); 718 qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32); 719 qdev_init_gpio_out(dev, s->handler, s->modulecount * 32); 720 for (i = 0; i < s->modulecount; i++) { 721 struct omap2_gpio_s *m = &s->modules[i]; 722 if (!s->fclk[i]) { 723 hw_error("omap2-gpio: fclk%d not connected\n", i); 724 } 725 m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25; 726 m->handler = &s->handler[i * 32]; 727 sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */ 728 sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */ 729 sysbus_init_irq(sbd, &m->wkup); 730 memory_region_init_io(&m->iomem, OBJECT(s), &omap2_gpio_module_ops, m, 731 "omap.gpio-module", 0x1000); 732 sysbus_init_mmio(sbd, &m->iomem); 733 } 734 return 0; 735 } 736 737 /* Using qdev pointer properties for the clocks is not ideal. 738 * qdev should support a generic means of defining a 'port' with 739 * an arbitrary interface for connecting two devices. Then we 740 * could reframe the omap clock API in terms of clock ports, 741 * and get some type safety. For now the best qdev provides is 742 * passing an arbitrary pointer. 743 * (It's not possible to pass in the string which is the clock 744 * name, because this device does not have the necessary information 745 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer 746 * translation.) 747 */ 748 749 static Property omap_gpio_properties[] = { 750 DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0), 751 DEFINE_PROP_PTR("clk", struct omap_gpif_s, clk), 752 DEFINE_PROP_END_OF_LIST(), 753 }; 754 755 static void omap_gpio_class_init(ObjectClass *klass, void *data) 756 { 757 DeviceClass *dc = DEVICE_CLASS(klass); 758 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 759 760 k->init = omap_gpio_init; 761 dc->reset = omap_gpif_reset; 762 dc->props = omap_gpio_properties; 763 /* Reason: pointer property "clk" */ 764 dc->cannot_instantiate_with_device_add_yet = true; 765 } 766 767 static const TypeInfo omap_gpio_info = { 768 .name = TYPE_OMAP1_GPIO, 769 .parent = TYPE_SYS_BUS_DEVICE, 770 .instance_size = sizeof(struct omap_gpif_s), 771 .class_init = omap_gpio_class_init, 772 }; 773 774 static Property omap2_gpio_properties[] = { 775 DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0), 776 DEFINE_PROP_PTR("iclk", struct omap2_gpif_s, iclk), 777 DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s, fclk[0]), 778 DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s, fclk[1]), 779 DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s, fclk[2]), 780 DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s, fclk[3]), 781 DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s, fclk[4]), 782 DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s, fclk[5]), 783 DEFINE_PROP_END_OF_LIST(), 784 }; 785 786 static void omap2_gpio_class_init(ObjectClass *klass, void *data) 787 { 788 DeviceClass *dc = DEVICE_CLASS(klass); 789 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 790 791 k->init = omap2_gpio_init; 792 dc->reset = omap2_gpif_reset; 793 dc->props = omap2_gpio_properties; 794 /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */ 795 dc->cannot_instantiate_with_device_add_yet = true; 796 } 797 798 static const TypeInfo omap2_gpio_info = { 799 .name = TYPE_OMAP2_GPIO, 800 .parent = TYPE_SYS_BUS_DEVICE, 801 .instance_size = sizeof(struct omap2_gpif_s), 802 .class_init = omap2_gpio_class_init, 803 }; 804 805 static void omap_gpio_register_types(void) 806 { 807 type_register_static(&omap_gpio_info); 808 type_register_static(&omap2_gpio_info); 809 } 810 811 type_init(omap_gpio_register_types) 812