1 /* 2 * TI OMAP processors GPIO emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * Copyright (C) 2007-2009 Nokia Corporation 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/log.h" 23 #include "hw/irq.h" 24 #include "hw/qdev-properties.h" 25 #include "hw/arm/omap.h" 26 #include "hw/sysbus.h" 27 #include "qemu/error-report.h" 28 #include "qemu/module.h" 29 #include "qapi/error.h" 30 31 struct omap_gpio_s { 32 qemu_irq irq; 33 qemu_irq handler[16]; 34 35 uint16_t inputs; 36 uint16_t outputs; 37 uint16_t dir; 38 uint16_t edge; 39 uint16_t mask; 40 uint16_t ints; 41 uint16_t pins; 42 }; 43 44 struct Omap1GpioState { 45 SysBusDevice parent_obj; 46 47 MemoryRegion iomem; 48 int mpu_model; 49 void *clk; 50 struct omap_gpio_s omap1; 51 }; 52 53 /* General-Purpose I/O of OMAP1 */ 54 static void omap_gpio_set(void *opaque, int line, int level) 55 { 56 Omap1GpioState *p = opaque; 57 struct omap_gpio_s *s = &p->omap1; 58 uint16_t prev = s->inputs; 59 60 if (level) 61 s->inputs |= 1 << line; 62 else 63 s->inputs &= ~(1 << line); 64 65 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & 66 (1 << line) & s->dir & ~s->mask) { 67 s->ints |= 1 << line; 68 qemu_irq_raise(s->irq); 69 } 70 } 71 72 static uint64_t omap_gpio_read(void *opaque, hwaddr addr, 73 unsigned size) 74 { 75 struct omap_gpio_s *s = opaque; 76 int offset = addr & OMAP_MPUI_REG_MASK; 77 78 if (size != 2) { 79 return omap_badwidth_read16(opaque, addr); 80 } 81 82 switch (offset) { 83 case 0x00: /* DATA_INPUT */ 84 return s->inputs & s->pins; 85 86 case 0x04: /* DATA_OUTPUT */ 87 return s->outputs; 88 89 case 0x08: /* DIRECTION_CONTROL */ 90 return s->dir; 91 92 case 0x0c: /* INTERRUPT_CONTROL */ 93 return s->edge; 94 95 case 0x10: /* INTERRUPT_MASK */ 96 return s->mask; 97 98 case 0x14: /* INTERRUPT_STATUS */ 99 return s->ints; 100 101 case 0x18: /* PIN_CONTROL (not in OMAP310) */ 102 OMAP_BAD_REG(addr); 103 return s->pins; 104 } 105 106 OMAP_BAD_REG(addr); 107 return 0; 108 } 109 110 static void omap_gpio_write(void *opaque, hwaddr addr, 111 uint64_t value, unsigned size) 112 { 113 struct omap_gpio_s *s = opaque; 114 int offset = addr & OMAP_MPUI_REG_MASK; 115 uint16_t diff; 116 int ln; 117 118 if (size != 2) { 119 omap_badwidth_write16(opaque, addr, value); 120 return; 121 } 122 123 switch (offset) { 124 case 0x00: /* DATA_INPUT */ 125 OMAP_RO_REG(addr); 126 return; 127 128 case 0x04: /* DATA_OUTPUT */ 129 diff = (s->outputs ^ value) & ~s->dir; 130 s->outputs = value; 131 while ((ln = ctz32(diff)) != 32) { 132 if (s->handler[ln]) 133 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 134 diff &= ~(1 << ln); 135 } 136 break; 137 138 case 0x08: /* DIRECTION_CONTROL */ 139 diff = s->outputs & (s->dir ^ value); 140 s->dir = value; 141 142 value = s->outputs & ~s->dir; 143 while ((ln = ctz32(diff)) != 32) { 144 if (s->handler[ln]) 145 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 146 diff &= ~(1 << ln); 147 } 148 break; 149 150 case 0x0c: /* INTERRUPT_CONTROL */ 151 s->edge = value; 152 break; 153 154 case 0x10: /* INTERRUPT_MASK */ 155 s->mask = value; 156 break; 157 158 case 0x14: /* INTERRUPT_STATUS */ 159 s->ints &= ~value; 160 if (!s->ints) 161 qemu_irq_lower(s->irq); 162 break; 163 164 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ 165 OMAP_BAD_REG(addr); 166 s->pins = value; 167 break; 168 169 default: 170 OMAP_BAD_REG(addr); 171 return; 172 } 173 } 174 175 /* *Some* sources say the memory region is 32-bit. */ 176 static const MemoryRegionOps omap_gpio_ops = { 177 .read = omap_gpio_read, 178 .write = omap_gpio_write, 179 .endianness = DEVICE_NATIVE_ENDIAN, 180 }; 181 182 static void omap_gpio_reset(struct omap_gpio_s *s) 183 { 184 s->inputs = 0; 185 s->outputs = ~0; 186 s->dir = ~0; 187 s->edge = ~0; 188 s->mask = ~0; 189 s->ints = 0; 190 s->pins = ~0; 191 } 192 193 struct omap2_gpio_s { 194 qemu_irq irq[2]; 195 qemu_irq wkup; 196 qemu_irq *handler; 197 MemoryRegion iomem; 198 199 uint8_t revision; 200 uint8_t config[2]; 201 uint32_t inputs; 202 uint32_t outputs; 203 uint32_t dir; 204 uint32_t level[2]; 205 uint32_t edge[2]; 206 uint32_t mask[2]; 207 uint32_t wumask; 208 uint32_t ints[2]; 209 uint32_t debounce; 210 uint8_t delay; 211 }; 212 213 struct Omap2GpioState { 214 SysBusDevice parent_obj; 215 216 MemoryRegion iomem; 217 int mpu_model; 218 void *iclk; 219 void *fclk[6]; 220 int modulecount; 221 struct omap2_gpio_s *modules; 222 qemu_irq *handler; 223 int autoidle; 224 int gpo; 225 }; 226 227 /* General-Purpose Interface of OMAP2/3 */ 228 static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s, 229 int line) 230 { 231 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); 232 } 233 234 static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line) 235 { 236 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ 237 return; 238 if (!(s->config[0] & (3 << 3))) /* Force Idle */ 239 return; 240 if (!(s->wumask & (1 << line))) 241 return; 242 243 qemu_irq_raise(s->wkup); 244 } 245 246 static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s, 247 uint32_t diff) 248 { 249 int ln; 250 251 s->outputs ^= diff; 252 diff &= ~s->dir; 253 while ((ln = ctz32(diff)) != 32) { 254 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1); 255 diff &= ~(1 << ln); 256 } 257 } 258 259 static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line) 260 { 261 s->ints[line] |= s->dir & 262 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); 263 omap2_gpio_module_int_update(s, line); 264 } 265 266 static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line) 267 { 268 s->ints[0] |= 1 << line; 269 omap2_gpio_module_int_update(s, 0); 270 s->ints[1] |= 1 << line; 271 omap2_gpio_module_int_update(s, 1); 272 omap2_gpio_module_wake(s, line); 273 } 274 275 static void omap2_gpio_set(void *opaque, int line, int level) 276 { 277 Omap2GpioState *p = opaque; 278 struct omap2_gpio_s *s = &p->modules[line >> 5]; 279 280 line &= 31; 281 if (level) { 282 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) 283 omap2_gpio_module_int(s, line); 284 s->inputs |= 1 << line; 285 } else { 286 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) 287 omap2_gpio_module_int(s, line); 288 s->inputs &= ~(1 << line); 289 } 290 } 291 292 static void omap2_gpio_module_reset(struct omap2_gpio_s *s) 293 { 294 s->config[0] = 0; 295 s->config[1] = 2; 296 s->ints[0] = 0; 297 s->ints[1] = 0; 298 s->mask[0] = 0; 299 s->mask[1] = 0; 300 s->wumask = 0; 301 s->dir = ~0; 302 s->level[0] = 0; 303 s->level[1] = 0; 304 s->edge[0] = 0; 305 s->edge[1] = 0; 306 s->debounce = 0; 307 s->delay = 0; 308 } 309 310 static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr) 311 { 312 struct omap2_gpio_s *s = opaque; 313 314 switch (addr) { 315 case 0x00: /* GPIO_REVISION */ 316 return s->revision; 317 318 case 0x10: /* GPIO_SYSCONFIG */ 319 return s->config[0]; 320 321 case 0x14: /* GPIO_SYSSTATUS */ 322 return 0x01; 323 324 case 0x18: /* GPIO_IRQSTATUS1 */ 325 return s->ints[0]; 326 327 case 0x1c: /* GPIO_IRQENABLE1 */ 328 case 0x60: /* GPIO_CLEARIRQENABLE1 */ 329 case 0x64: /* GPIO_SETIRQENABLE1 */ 330 return s->mask[0]; 331 332 case 0x20: /* GPIO_WAKEUPENABLE */ 333 case 0x80: /* GPIO_CLEARWKUENA */ 334 case 0x84: /* GPIO_SETWKUENA */ 335 return s->wumask; 336 337 case 0x28: /* GPIO_IRQSTATUS2 */ 338 return s->ints[1]; 339 340 case 0x2c: /* GPIO_IRQENABLE2 */ 341 case 0x70: /* GPIO_CLEARIRQENABLE2 */ 342 case 0x74: /* GPIO_SETIREQNEABLE2 */ 343 return s->mask[1]; 344 345 case 0x30: /* GPIO_CTRL */ 346 return s->config[1]; 347 348 case 0x34: /* GPIO_OE */ 349 return s->dir; 350 351 case 0x38: /* GPIO_DATAIN */ 352 return s->inputs; 353 354 case 0x3c: /* GPIO_DATAOUT */ 355 case 0x90: /* GPIO_CLEARDATAOUT */ 356 case 0x94: /* GPIO_SETDATAOUT */ 357 return s->outputs; 358 359 case 0x40: /* GPIO_LEVELDETECT0 */ 360 return s->level[0]; 361 362 case 0x44: /* GPIO_LEVELDETECT1 */ 363 return s->level[1]; 364 365 case 0x48: /* GPIO_RISINGDETECT */ 366 return s->edge[0]; 367 368 case 0x4c: /* GPIO_FALLINGDETECT */ 369 return s->edge[1]; 370 371 case 0x50: /* GPIO_DEBOUNCENABLE */ 372 return s->debounce; 373 374 case 0x54: /* GPIO_DEBOUNCINGTIME */ 375 return s->delay; 376 } 377 378 OMAP_BAD_REG(addr); 379 return 0; 380 } 381 382 static void omap2_gpio_module_write(void *opaque, hwaddr addr, 383 uint32_t value) 384 { 385 struct omap2_gpio_s *s = opaque; 386 uint32_t diff; 387 int ln; 388 389 switch (addr) { 390 case 0x00: /* GPIO_REVISION */ 391 case 0x14: /* GPIO_SYSSTATUS */ 392 case 0x38: /* GPIO_DATAIN */ 393 OMAP_RO_REG(addr); 394 break; 395 396 case 0x10: /* GPIO_SYSCONFIG */ 397 if (((value >> 3) & 3) == 3) { 398 qemu_log_mask(LOG_GUEST_ERROR, 399 "%s: Illegal IDLEMODE value: 3\n", __func__); 400 } 401 if (value & 2) 402 omap2_gpio_module_reset(s); 403 s->config[0] = value & 0x1d; 404 break; 405 406 case 0x18: /* GPIO_IRQSTATUS1 */ 407 if (s->ints[0] & value) { 408 s->ints[0] &= ~value; 409 omap2_gpio_module_level_update(s, 0); 410 } 411 break; 412 413 case 0x1c: /* GPIO_IRQENABLE1 */ 414 s->mask[0] = value; 415 omap2_gpio_module_int_update(s, 0); 416 break; 417 418 case 0x20: /* GPIO_WAKEUPENABLE */ 419 s->wumask = value; 420 break; 421 422 case 0x28: /* GPIO_IRQSTATUS2 */ 423 if (s->ints[1] & value) { 424 s->ints[1] &= ~value; 425 omap2_gpio_module_level_update(s, 1); 426 } 427 break; 428 429 case 0x2c: /* GPIO_IRQENABLE2 */ 430 s->mask[1] = value; 431 omap2_gpio_module_int_update(s, 1); 432 break; 433 434 case 0x30: /* GPIO_CTRL */ 435 s->config[1] = value & 7; 436 break; 437 438 case 0x34: /* GPIO_OE */ 439 diff = s->outputs & (s->dir ^ value); 440 s->dir = value; 441 442 value = s->outputs & ~s->dir; 443 while ((ln = ctz32(diff)) != 32) { 444 diff &= ~(1 << ln); 445 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 446 } 447 448 omap2_gpio_module_level_update(s, 0); 449 omap2_gpio_module_level_update(s, 1); 450 break; 451 452 case 0x3c: /* GPIO_DATAOUT */ 453 omap2_gpio_module_out_update(s, s->outputs ^ value); 454 break; 455 456 case 0x40: /* GPIO_LEVELDETECT0 */ 457 s->level[0] = value; 458 omap2_gpio_module_level_update(s, 0); 459 omap2_gpio_module_level_update(s, 1); 460 break; 461 462 case 0x44: /* GPIO_LEVELDETECT1 */ 463 s->level[1] = value; 464 omap2_gpio_module_level_update(s, 0); 465 omap2_gpio_module_level_update(s, 1); 466 break; 467 468 case 0x48: /* GPIO_RISINGDETECT */ 469 s->edge[0] = value; 470 break; 471 472 case 0x4c: /* GPIO_FALLINGDETECT */ 473 s->edge[1] = value; 474 break; 475 476 case 0x50: /* GPIO_DEBOUNCENABLE */ 477 s->debounce = value; 478 break; 479 480 case 0x54: /* GPIO_DEBOUNCINGTIME */ 481 s->delay = value; 482 break; 483 484 case 0x60: /* GPIO_CLEARIRQENABLE1 */ 485 s->mask[0] &= ~value; 486 omap2_gpio_module_int_update(s, 0); 487 break; 488 489 case 0x64: /* GPIO_SETIRQENABLE1 */ 490 s->mask[0] |= value; 491 omap2_gpio_module_int_update(s, 0); 492 break; 493 494 case 0x70: /* GPIO_CLEARIRQENABLE2 */ 495 s->mask[1] &= ~value; 496 omap2_gpio_module_int_update(s, 1); 497 break; 498 499 case 0x74: /* GPIO_SETIREQNEABLE2 */ 500 s->mask[1] |= value; 501 omap2_gpio_module_int_update(s, 1); 502 break; 503 504 case 0x80: /* GPIO_CLEARWKUENA */ 505 s->wumask &= ~value; 506 break; 507 508 case 0x84: /* GPIO_SETWKUENA */ 509 s->wumask |= value; 510 break; 511 512 case 0x90: /* GPIO_CLEARDATAOUT */ 513 omap2_gpio_module_out_update(s, s->outputs & value); 514 break; 515 516 case 0x94: /* GPIO_SETDATAOUT */ 517 omap2_gpio_module_out_update(s, ~s->outputs & value); 518 break; 519 520 default: 521 OMAP_BAD_REG(addr); 522 return; 523 } 524 } 525 526 static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr, 527 unsigned size) 528 { 529 return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3); 530 } 531 532 static void omap2_gpio_module_writep(void *opaque, hwaddr addr, 533 uint64_t value, unsigned size) 534 { 535 uint32_t cur = 0; 536 uint32_t mask = 0xffff; 537 538 if (size == 4) { 539 omap2_gpio_module_write(opaque, addr, value); 540 return; 541 } 542 543 switch (addr & ~3) { 544 case 0x00: /* GPIO_REVISION */ 545 case 0x14: /* GPIO_SYSSTATUS */ 546 case 0x38: /* GPIO_DATAIN */ 547 OMAP_RO_REG(addr); 548 break; 549 550 case 0x10: /* GPIO_SYSCONFIG */ 551 case 0x1c: /* GPIO_IRQENABLE1 */ 552 case 0x20: /* GPIO_WAKEUPENABLE */ 553 case 0x2c: /* GPIO_IRQENABLE2 */ 554 case 0x30: /* GPIO_CTRL */ 555 case 0x34: /* GPIO_OE */ 556 case 0x3c: /* GPIO_DATAOUT */ 557 case 0x40: /* GPIO_LEVELDETECT0 */ 558 case 0x44: /* GPIO_LEVELDETECT1 */ 559 case 0x48: /* GPIO_RISINGDETECT */ 560 case 0x4c: /* GPIO_FALLINGDETECT */ 561 case 0x50: /* GPIO_DEBOUNCENABLE */ 562 case 0x54: /* GPIO_DEBOUNCINGTIME */ 563 cur = omap2_gpio_module_read(opaque, addr & ~3) & 564 ~(mask << ((addr & 3) << 3)); 565 566 /* Fall through. */ 567 case 0x18: /* GPIO_IRQSTATUS1 */ 568 case 0x28: /* GPIO_IRQSTATUS2 */ 569 case 0x60: /* GPIO_CLEARIRQENABLE1 */ 570 case 0x64: /* GPIO_SETIRQENABLE1 */ 571 case 0x70: /* GPIO_CLEARIRQENABLE2 */ 572 case 0x74: /* GPIO_SETIREQNEABLE2 */ 573 case 0x80: /* GPIO_CLEARWKUENA */ 574 case 0x84: /* GPIO_SETWKUENA */ 575 case 0x90: /* GPIO_CLEARDATAOUT */ 576 case 0x94: /* GPIO_SETDATAOUT */ 577 value <<= (addr & 3) << 3; 578 omap2_gpio_module_write(opaque, addr, cur | value); 579 break; 580 581 default: 582 OMAP_BAD_REG(addr); 583 return; 584 } 585 } 586 587 static const MemoryRegionOps omap2_gpio_module_ops = { 588 .read = omap2_gpio_module_readp, 589 .write = omap2_gpio_module_writep, 590 .valid.min_access_size = 1, 591 .valid.max_access_size = 4, 592 .endianness = DEVICE_NATIVE_ENDIAN, 593 }; 594 595 static void omap_gpif_reset(DeviceState *dev) 596 { 597 Omap1GpioState *s = OMAP1_GPIO(dev); 598 599 omap_gpio_reset(&s->omap1); 600 } 601 602 static void omap2_gpif_reset(DeviceState *dev) 603 { 604 Omap2GpioState *s = OMAP2_GPIO(dev); 605 int i; 606 607 for (i = 0; i < s->modulecount; i++) { 608 omap2_gpio_module_reset(&s->modules[i]); 609 } 610 s->autoidle = 0; 611 s->gpo = 0; 612 } 613 614 static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size) 615 { 616 Omap2GpioState *s = opaque; 617 618 switch (addr) { 619 case 0x00: /* IPGENERICOCPSPL_REVISION */ 620 return 0x18; 621 622 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ 623 return s->autoidle; 624 625 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ 626 return 0x01; 627 628 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ 629 return 0x00; 630 631 case 0x40: /* IPGENERICOCPSPL_GPO */ 632 return s->gpo; 633 634 case 0x50: /* IPGENERICOCPSPL_GPI */ 635 return 0x00; 636 } 637 638 OMAP_BAD_REG(addr); 639 return 0; 640 } 641 642 static void omap2_gpif_top_write(void *opaque, hwaddr addr, 643 uint64_t value, unsigned size) 644 { 645 Omap2GpioState *s = opaque; 646 647 switch (addr) { 648 case 0x00: /* IPGENERICOCPSPL_REVISION */ 649 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ 650 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ 651 case 0x50: /* IPGENERICOCPSPL_GPI */ 652 OMAP_RO_REG(addr); 653 break; 654 655 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ 656 if (value & (1 << 1)) /* SOFTRESET */ 657 omap2_gpif_reset(DEVICE(s)); 658 s->autoidle = value & 1; 659 break; 660 661 case 0x40: /* IPGENERICOCPSPL_GPO */ 662 s->gpo = value & 1; 663 break; 664 665 default: 666 OMAP_BAD_REG(addr); 667 return; 668 } 669 } 670 671 static const MemoryRegionOps omap2_gpif_top_ops = { 672 .read = omap2_gpif_top_read, 673 .write = omap2_gpif_top_write, 674 .endianness = DEVICE_NATIVE_ENDIAN, 675 }; 676 677 static void omap_gpio_init(Object *obj) 678 { 679 DeviceState *dev = DEVICE(obj); 680 Omap1GpioState *s = OMAP1_GPIO(obj); 681 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 682 683 qdev_init_gpio_in(dev, omap_gpio_set, 16); 684 qdev_init_gpio_out(dev, s->omap1.handler, 16); 685 sysbus_init_irq(sbd, &s->omap1.irq); 686 memory_region_init_io(&s->iomem, obj, &omap_gpio_ops, &s->omap1, 687 "omap.gpio", 0x1000); 688 sysbus_init_mmio(sbd, &s->iomem); 689 } 690 691 static void omap_gpio_realize(DeviceState *dev, Error **errp) 692 { 693 Omap1GpioState *s = OMAP1_GPIO(dev); 694 695 if (!s->clk) { 696 error_setg(errp, "omap-gpio: clk not connected"); 697 } 698 } 699 700 static void omap2_gpio_realize(DeviceState *dev, Error **errp) 701 { 702 Omap2GpioState *s = OMAP2_GPIO(dev); 703 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 704 int i; 705 706 if (!s->iclk) { 707 error_setg(errp, "omap2-gpio: iclk not connected"); 708 return; 709 } 710 711 s->modulecount = s->mpu_model < omap2430 ? 4 712 : s->mpu_model < omap3430 ? 5 713 : 6; 714 715 if (s->mpu_model < omap3430) { 716 memory_region_init_io(&s->iomem, OBJECT(dev), &omap2_gpif_top_ops, s, 717 "omap2.gpio", 0x1000); 718 sysbus_init_mmio(sbd, &s->iomem); 719 } 720 721 s->modules = g_new0(struct omap2_gpio_s, s->modulecount); 722 s->handler = g_new0(qemu_irq, s->modulecount * 32); 723 qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32); 724 qdev_init_gpio_out(dev, s->handler, s->modulecount * 32); 725 726 for (i = 0; i < s->modulecount; i++) { 727 struct omap2_gpio_s *m = &s->modules[i]; 728 729 if (!s->fclk[i]) { 730 error_setg(errp, "omap2-gpio: fclk%d not connected", i); 731 return; 732 } 733 734 m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25; 735 m->handler = &s->handler[i * 32]; 736 sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */ 737 sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */ 738 sysbus_init_irq(sbd, &m->wkup); 739 memory_region_init_io(&m->iomem, OBJECT(dev), &omap2_gpio_module_ops, m, 740 "omap.gpio-module", 0x1000); 741 sysbus_init_mmio(sbd, &m->iomem); 742 } 743 } 744 745 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk) 746 { 747 gpio->clk = clk; 748 } 749 750 static Property omap_gpio_properties[] = { 751 DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0), 752 DEFINE_PROP_END_OF_LIST(), 753 }; 754 755 static void omap_gpio_class_init(ObjectClass *klass, void *data) 756 { 757 DeviceClass *dc = DEVICE_CLASS(klass); 758 759 dc->realize = omap_gpio_realize; 760 dc->reset = omap_gpif_reset; 761 device_class_set_props(dc, omap_gpio_properties); 762 /* Reason: pointer property "clk" */ 763 dc->user_creatable = false; 764 } 765 766 static const TypeInfo omap_gpio_info = { 767 .name = TYPE_OMAP1_GPIO, 768 .parent = TYPE_SYS_BUS_DEVICE, 769 .instance_size = sizeof(Omap1GpioState), 770 .instance_init = omap_gpio_init, 771 .class_init = omap_gpio_class_init, 772 }; 773 774 void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk) 775 { 776 gpio->iclk = clk; 777 } 778 779 void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk) 780 { 781 assert(i <= 5); 782 gpio->fclk[i] = clk; 783 } 784 785 static Property omap2_gpio_properties[] = { 786 DEFINE_PROP_INT32("mpu_model", Omap2GpioState, mpu_model, 0), 787 DEFINE_PROP_END_OF_LIST(), 788 }; 789 790 static void omap2_gpio_class_init(ObjectClass *klass, void *data) 791 { 792 DeviceClass *dc = DEVICE_CLASS(klass); 793 794 dc->realize = omap2_gpio_realize; 795 dc->reset = omap2_gpif_reset; 796 device_class_set_props(dc, omap2_gpio_properties); 797 /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */ 798 dc->user_creatable = false; 799 } 800 801 static const TypeInfo omap2_gpio_info = { 802 .name = TYPE_OMAP2_GPIO, 803 .parent = TYPE_SYS_BUS_DEVICE, 804 .instance_size = sizeof(Omap2GpioState), 805 .class_init = omap2_gpio_class_init, 806 }; 807 808 static void omap_gpio_register_types(void) 809 { 810 type_register_static(&omap_gpio_info); 811 type_register_static(&omap2_gpio_info); 812 } 813 814 type_init(omap_gpio_register_types) 815