1 /* 2 * nRF51 System-on-Chip general purpose input/output register definition 3 * 4 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf 5 * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf 6 * 7 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/log.h" 15 #include "qemu/module.h" 16 #include "hw/gpio/nrf51_gpio.h" 17 #include "hw/irq.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 21 /* 22 * Check if the output driver is connected to the direction switch 23 * given the current configuration and logic level. 24 * It is not differentiated between standard and "high"(-power) drive modes. 25 */ 26 static bool is_connected(uint32_t config, uint32_t level) 27 { 28 bool state; 29 uint32_t drive_config = extract32(config, 8, 3); 30 31 switch (drive_config) { 32 case 0 ... 3: 33 state = true; 34 break; 35 case 4 ... 5: 36 state = level != 0; 37 break; 38 case 6 ... 7: 39 state = level == 0; 40 break; 41 default: 42 g_assert_not_reached(); 43 break; 44 } 45 46 return state; 47 } 48 49 static int pull_value(uint32_t config) 50 { 51 int pull = extract32(config, 2, 2); 52 if (pull == NRF51_GPIO_PULLDOWN) { 53 return 0; 54 } else if (pull == NRF51_GPIO_PULLUP) { 55 return 1; 56 } 57 return -1; 58 } 59 60 static void update_output_irq(NRF51GPIOState *s, size_t i, 61 bool connected, bool level) 62 { 63 int64_t irq_level = connected ? level : -1; 64 bool old_connected = extract32(s->old_out_connected, i, 1); 65 bool old_level = extract32(s->old_out, i, 1); 66 67 if ((old_connected != connected) || (old_level != level)) { 68 qemu_set_irq(s->output[i], irq_level); 69 trace_nrf51_gpio_update_output_irq(i, irq_level); 70 } 71 72 s->old_out = deposit32(s->old_out, i, 1, level); 73 s->old_out_connected = deposit32(s->old_out_connected, i, 1, connected); 74 } 75 76 static void update_state(NRF51GPIOState *s) 77 { 78 int pull; 79 size_t i; 80 bool connected_out, dir, connected_in, out, in, input; 81 bool assert_detect = false; 82 83 for (i = 0; i < NRF51_GPIO_PINS; i++) { 84 pull = pull_value(s->cnf[i]); 85 dir = extract32(s->cnf[i], 0, 1); 86 connected_in = extract32(s->in_mask, i, 1); 87 out = extract32(s->out, i, 1); 88 in = extract32(s->in, i, 1); 89 input = !extract32(s->cnf[i], 1, 1); 90 connected_out = is_connected(s->cnf[i], out) && dir; 91 92 if (!input) { 93 if (pull >= 0) { 94 /* Input buffer disconnected from external drives */ 95 s->in = deposit32(s->in, i, 1, pull); 96 } 97 } else { 98 if (connected_out && connected_in && out != in) { 99 /* Pin both driven externally and internally */ 100 qemu_log_mask(LOG_GUEST_ERROR, 101 "GPIO pin %zu short circuited\n", i); 102 } 103 if (connected_in) { 104 uint32_t detect_config = extract32(s->cnf[i], 16, 2); 105 if ((detect_config == 2) && (in == 1)) { 106 assert_detect = true; 107 } 108 if ((detect_config == 3) && (in == 0)) { 109 assert_detect = true; 110 } 111 } else { 112 /* 113 * Floating input: the output stimulates IN if connected, 114 * otherwise pull-up/pull-down resistors put a value on both 115 * IN and OUT. 116 */ 117 if (pull >= 0 && !connected_out) { 118 connected_out = true; 119 out = pull; 120 } 121 if (connected_out) { 122 s->in = deposit32(s->in, i, 1, out); 123 } 124 } 125 } 126 update_output_irq(s, i, connected_out, out); 127 } 128 129 qemu_set_irq(s->detect, assert_detect); 130 } 131 132 /* 133 * Direction is exposed in both the DIR register and the DIR bit 134 * of each PINs CNF configuration register. Reflect bits for pins in DIR 135 * to individual pin configuration registers. 136 */ 137 static void reflect_dir_bit_in_cnf(NRF51GPIOState *s) 138 { 139 size_t i; 140 141 uint32_t value = s->dir; 142 143 for (i = 0; i < NRF51_GPIO_PINS; i++) { 144 s->cnf[i] = (s->cnf[i] & ~(1UL)) | ((value >> i) & 0x01); 145 } 146 } 147 148 static uint64_t nrf51_gpio_read(void *opaque, hwaddr offset, unsigned int size) 149 { 150 NRF51GPIOState *s = NRF51_GPIO(opaque); 151 uint64_t r = 0; 152 size_t idx; 153 154 switch (offset) { 155 case NRF51_GPIO_REG_OUT ... NRF51_GPIO_REG_OUTCLR: 156 r = s->out; 157 break; 158 159 case NRF51_GPIO_REG_IN: 160 r = s->in; 161 break; 162 163 case NRF51_GPIO_REG_DIR ... NRF51_GPIO_REG_DIRCLR: 164 r = s->dir; 165 break; 166 167 case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: 168 idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; 169 r = s->cnf[idx]; 170 break; 171 172 default: 173 qemu_log_mask(LOG_GUEST_ERROR, 174 "%s: bad read offset 0x%" HWADDR_PRIx "\n", 175 __func__, offset); 176 } 177 178 trace_nrf51_gpio_read(offset, r); 179 180 return r; 181 } 182 183 static void nrf51_gpio_write(void *opaque, hwaddr offset, 184 uint64_t value, unsigned int size) 185 { 186 NRF51GPIOState *s = NRF51_GPIO(opaque); 187 size_t idx; 188 189 trace_nrf51_gpio_write(offset, value); 190 191 switch (offset) { 192 case NRF51_GPIO_REG_OUT: 193 s->out = value; 194 break; 195 196 case NRF51_GPIO_REG_OUTSET: 197 s->out |= value; 198 break; 199 200 case NRF51_GPIO_REG_OUTCLR: 201 s->out &= ~value; 202 break; 203 204 case NRF51_GPIO_REG_DIR: 205 s->dir = value; 206 reflect_dir_bit_in_cnf(s); 207 break; 208 209 case NRF51_GPIO_REG_DIRSET: 210 s->dir |= value; 211 reflect_dir_bit_in_cnf(s); 212 break; 213 214 case NRF51_GPIO_REG_DIRCLR: 215 s->dir &= ~value; 216 reflect_dir_bit_in_cnf(s); 217 break; 218 219 case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: 220 idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; 221 s->cnf[idx] = value; 222 /* 223 * direction is exposed in both the DIR register and the DIR bit 224 * of each PINs CNF configuration register. 225 */ 226 s->dir = (s->dir & ~(1UL << idx)) | ((value & 0x01) << idx); 227 break; 228 229 default: 230 qemu_log_mask(LOG_GUEST_ERROR, 231 "%s: bad write offset 0x%" HWADDR_PRIx "\n", 232 __func__, offset); 233 } 234 235 update_state(s); 236 } 237 238 static const MemoryRegionOps gpio_ops = { 239 .read = nrf51_gpio_read, 240 .write = nrf51_gpio_write, 241 .endianness = DEVICE_LITTLE_ENDIAN, 242 .impl.min_access_size = 4, 243 .impl.max_access_size = 4, 244 }; 245 246 static void nrf51_gpio_set(void *opaque, int line, int value) 247 { 248 NRF51GPIOState *s = NRF51_GPIO(opaque); 249 250 trace_nrf51_gpio_set(line, value); 251 252 assert(line >= 0 && line < NRF51_GPIO_PINS); 253 254 s->in_mask = deposit32(s->in_mask, line, 1, value >= 0); 255 if (value >= 0) { 256 s->in = deposit32(s->in, line, 1, value != 0); 257 } 258 259 update_state(s); 260 } 261 262 static void nrf51_gpio_reset(DeviceState *dev) 263 { 264 NRF51GPIOState *s = NRF51_GPIO(dev); 265 size_t i; 266 267 s->out = 0; 268 s->old_out = 0; 269 s->old_out_connected = 0; 270 s->in = 0; 271 s->in_mask = 0; 272 s->dir = 0; 273 274 for (i = 0; i < NRF51_GPIO_PINS; i++) { 275 s->cnf[i] = 0x00000002; 276 } 277 } 278 279 static const VMStateDescription vmstate_nrf51_gpio = { 280 .name = TYPE_NRF51_GPIO, 281 .version_id = 1, 282 .minimum_version_id = 1, 283 .fields = (const VMStateField[]) { 284 VMSTATE_UINT32(out, NRF51GPIOState), 285 VMSTATE_UINT32(in, NRF51GPIOState), 286 VMSTATE_UINT32(in_mask, NRF51GPIOState), 287 VMSTATE_UINT32(dir, NRF51GPIOState), 288 VMSTATE_UINT32_ARRAY(cnf, NRF51GPIOState, NRF51_GPIO_PINS), 289 VMSTATE_UINT32(old_out, NRF51GPIOState), 290 VMSTATE_UINT32(old_out_connected, NRF51GPIOState), 291 VMSTATE_END_OF_LIST() 292 } 293 }; 294 295 static void nrf51_gpio_init(Object *obj) 296 { 297 NRF51GPIOState *s = NRF51_GPIO(obj); 298 299 memory_region_init_io(&s->mmio, obj, &gpio_ops, s, 300 TYPE_NRF51_GPIO, NRF51_GPIO_SIZE); 301 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 302 303 qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS); 304 qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS); 305 qdev_init_gpio_out_named(DEVICE(s), &s->detect, "detect", 1); 306 } 307 308 static void nrf51_gpio_class_init(ObjectClass *klass, void *data) 309 { 310 DeviceClass *dc = DEVICE_CLASS(klass); 311 312 dc->vmsd = &vmstate_nrf51_gpio; 313 device_class_set_legacy_reset(dc, nrf51_gpio_reset); 314 dc->desc = "nRF51 GPIO"; 315 } 316 317 static const TypeInfo nrf51_gpio_info = { 318 .name = TYPE_NRF51_GPIO, 319 .parent = TYPE_SYS_BUS_DEVICE, 320 .instance_size = sizeof(NRF51GPIOState), 321 .instance_init = nrf51_gpio_init, 322 .class_init = nrf51_gpio_class_init 323 }; 324 325 static void nrf51_gpio_register_types(void) 326 { 327 type_register_static(&nrf51_gpio_info); 328 } 329 330 type_init(nrf51_gpio_register_types) 331