1 /* 2 * nRF51 System-on-Chip general purpose input/output register definition 3 * 4 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf 5 * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf 6 * 7 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/log.h" 15 #include "qemu/module.h" 16 #include "hw/gpio/nrf51_gpio.h" 17 #include "trace.h" 18 19 /* 20 * Check if the output driver is connected to the direction switch 21 * given the current configuration and logic level. 22 * It is not differentiated between standard and "high"(-power) drive modes. 23 */ 24 static bool is_connected(uint32_t config, uint32_t level) 25 { 26 bool state; 27 uint32_t drive_config = extract32(config, 8, 3); 28 29 switch (drive_config) { 30 case 0 ... 3: 31 state = true; 32 break; 33 case 4 ... 5: 34 state = level != 0; 35 break; 36 case 6 ... 7: 37 state = level == 0; 38 break; 39 default: 40 g_assert_not_reached(); 41 break; 42 } 43 44 return state; 45 } 46 47 static int pull_value(uint32_t config) 48 { 49 int pull = extract32(config, 2, 2); 50 if (pull == NRF51_GPIO_PULLDOWN) { 51 return 0; 52 } else if (pull == NRF51_GPIO_PULLUP) { 53 return 1; 54 } 55 return -1; 56 } 57 58 static void update_output_irq(NRF51GPIOState *s, size_t i, 59 bool connected, bool level) 60 { 61 int64_t irq_level = connected ? level : -1; 62 bool old_connected = extract32(s->old_out_connected, i, 1); 63 bool old_level = extract32(s->old_out, i, 1); 64 65 if ((old_connected != connected) || (old_level != level)) { 66 qemu_set_irq(s->output[i], irq_level); 67 trace_nrf51_gpio_update_output_irq(i, irq_level); 68 } 69 70 s->old_out = deposit32(s->old_out, i, 1, level); 71 s->old_out_connected = deposit32(s->old_out_connected, i, 1, connected); 72 } 73 74 static void update_state(NRF51GPIOState *s) 75 { 76 int pull; 77 size_t i; 78 bool connected_out, dir, connected_in, out, in, input; 79 80 for (i = 0; i < NRF51_GPIO_PINS; i++) { 81 pull = pull_value(s->cnf[i]); 82 dir = extract32(s->cnf[i], 0, 1); 83 connected_in = extract32(s->in_mask, i, 1); 84 out = extract32(s->out, i, 1); 85 in = extract32(s->in, i, 1); 86 input = !extract32(s->cnf[i], 1, 1); 87 connected_out = is_connected(s->cnf[i], out) && dir; 88 89 if (!input) { 90 if (pull >= 0) { 91 /* Input buffer disconnected from external drives */ 92 s->in = deposit32(s->in, i, 1, pull); 93 } 94 } else { 95 if (connected_out && connected_in && out != in) { 96 /* Pin both driven externally and internally */ 97 qemu_log_mask(LOG_GUEST_ERROR, 98 "GPIO pin %zu short circuited\n", i); 99 } 100 if (!connected_in) { 101 /* 102 * Floating input: the output stimulates IN if connected, 103 * otherwise pull-up/pull-down resistors put a value on both 104 * IN and OUT. 105 */ 106 if (pull >= 0 && !connected_out) { 107 connected_out = true; 108 out = pull; 109 } 110 if (connected_out) { 111 s->in = deposit32(s->in, i, 1, out); 112 } 113 } 114 } 115 update_output_irq(s, i, connected_out, out); 116 } 117 } 118 119 /* 120 * Direction is exposed in both the DIR register and the DIR bit 121 * of each PINs CNF configuration register. Reflect bits for pins in DIR 122 * to individual pin configuration registers. 123 */ 124 static void reflect_dir_bit_in_cnf(NRF51GPIOState *s) 125 { 126 size_t i; 127 128 uint32_t value = s->dir; 129 130 for (i = 0; i < NRF51_GPIO_PINS; i++) { 131 s->cnf[i] = (s->cnf[i] & ~(1UL)) | ((value >> i) & 0x01); 132 } 133 } 134 135 static uint64_t nrf51_gpio_read(void *opaque, hwaddr offset, unsigned int size) 136 { 137 NRF51GPIOState *s = NRF51_GPIO(opaque); 138 uint64_t r = 0; 139 size_t idx; 140 141 switch (offset) { 142 case NRF51_GPIO_REG_OUT ... NRF51_GPIO_REG_OUTCLR: 143 r = s->out; 144 break; 145 146 case NRF51_GPIO_REG_IN: 147 r = s->in; 148 break; 149 150 case NRF51_GPIO_REG_DIR ... NRF51_GPIO_REG_DIRCLR: 151 r = s->dir; 152 break; 153 154 case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: 155 idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; 156 r = s->cnf[idx]; 157 break; 158 159 default: 160 qemu_log_mask(LOG_GUEST_ERROR, 161 "%s: bad read offset 0x%" HWADDR_PRIx "\n", 162 __func__, offset); 163 } 164 165 trace_nrf51_gpio_read(offset, r); 166 167 return r; 168 } 169 170 static void nrf51_gpio_write(void *opaque, hwaddr offset, 171 uint64_t value, unsigned int size) 172 { 173 NRF51GPIOState *s = NRF51_GPIO(opaque); 174 size_t idx; 175 176 trace_nrf51_gpio_write(offset, value); 177 178 switch (offset) { 179 case NRF51_GPIO_REG_OUT: 180 s->out = value; 181 break; 182 183 case NRF51_GPIO_REG_OUTSET: 184 s->out |= value; 185 break; 186 187 case NRF51_GPIO_REG_OUTCLR: 188 s->out &= ~value; 189 break; 190 191 case NRF51_GPIO_REG_DIR: 192 s->dir = value; 193 reflect_dir_bit_in_cnf(s); 194 break; 195 196 case NRF51_GPIO_REG_DIRSET: 197 s->dir |= value; 198 reflect_dir_bit_in_cnf(s); 199 break; 200 201 case NRF51_GPIO_REG_DIRCLR: 202 s->dir &= ~value; 203 reflect_dir_bit_in_cnf(s); 204 break; 205 206 case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: 207 idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; 208 s->cnf[idx] = value; 209 /* 210 * direction is exposed in both the DIR register and the DIR bit 211 * of each PINs CNF configuration register. 212 */ 213 s->dir = (s->dir & ~(1UL << idx)) | ((value & 0x01) << idx); 214 break; 215 216 default: 217 qemu_log_mask(LOG_GUEST_ERROR, 218 "%s: bad write offset 0x%" HWADDR_PRIx "\n", 219 __func__, offset); 220 } 221 222 update_state(s); 223 } 224 225 static const MemoryRegionOps gpio_ops = { 226 .read = nrf51_gpio_read, 227 .write = nrf51_gpio_write, 228 .endianness = DEVICE_LITTLE_ENDIAN, 229 .impl.min_access_size = 4, 230 .impl.max_access_size = 4, 231 }; 232 233 static void nrf51_gpio_set(void *opaque, int line, int value) 234 { 235 NRF51GPIOState *s = NRF51_GPIO(opaque); 236 237 trace_nrf51_gpio_set(line, value); 238 239 assert(line >= 0 && line < NRF51_GPIO_PINS); 240 241 s->in_mask = deposit32(s->in_mask, line, 1, value >= 0); 242 if (value >= 0) { 243 s->in = deposit32(s->in, line, 1, value != 0); 244 } 245 246 update_state(s); 247 } 248 249 static void nrf51_gpio_reset(DeviceState *dev) 250 { 251 NRF51GPIOState *s = NRF51_GPIO(dev); 252 size_t i; 253 254 s->out = 0; 255 s->old_out = 0; 256 s->old_out_connected = 0; 257 s->in = 0; 258 s->in_mask = 0; 259 s->dir = 0; 260 261 for (i = 0; i < NRF51_GPIO_PINS; i++) { 262 s->cnf[i] = 0x00000002; 263 } 264 } 265 266 static const VMStateDescription vmstate_nrf51_gpio = { 267 .name = TYPE_NRF51_GPIO, 268 .version_id = 1, 269 .minimum_version_id = 1, 270 .fields = (VMStateField[]) { 271 VMSTATE_UINT32(out, NRF51GPIOState), 272 VMSTATE_UINT32(in, NRF51GPIOState), 273 VMSTATE_UINT32(in_mask, NRF51GPIOState), 274 VMSTATE_UINT32(dir, NRF51GPIOState), 275 VMSTATE_UINT32_ARRAY(cnf, NRF51GPIOState, NRF51_GPIO_PINS), 276 VMSTATE_UINT32(old_out, NRF51GPIOState), 277 VMSTATE_UINT32(old_out_connected, NRF51GPIOState), 278 VMSTATE_END_OF_LIST() 279 } 280 }; 281 282 static void nrf51_gpio_init(Object *obj) 283 { 284 NRF51GPIOState *s = NRF51_GPIO(obj); 285 286 memory_region_init_io(&s->mmio, obj, &gpio_ops, s, 287 TYPE_NRF51_GPIO, NRF51_GPIO_SIZE); 288 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 289 290 qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS); 291 qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS); 292 } 293 294 static void nrf51_gpio_class_init(ObjectClass *klass, void *data) 295 { 296 DeviceClass *dc = DEVICE_CLASS(klass); 297 298 dc->vmsd = &vmstate_nrf51_gpio; 299 dc->reset = nrf51_gpio_reset; 300 dc->desc = "nRF51 GPIO"; 301 } 302 303 static const TypeInfo nrf51_gpio_info = { 304 .name = TYPE_NRF51_GPIO, 305 .parent = TYPE_SYS_BUS_DEVICE, 306 .instance_size = sizeof(NRF51GPIOState), 307 .instance_init = nrf51_gpio_init, 308 .class_init = nrf51_gpio_class_init 309 }; 310 311 static void nrf51_gpio_register_types(void) 312 { 313 type_register_static(&nrf51_gpio_info); 314 } 315 316 type_init(nrf51_gpio_register_types) 317