1 /* 2 * ASPEED GPIO Controller 3 * 4 * Copyright (C) 2017-2019 IBM Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include <assert.h> 10 11 #include "qemu/osdep.h" 12 #include "qemu/host-utils.h" 13 #include "qemu/log.h" 14 #include "hw/gpio/aspeed_gpio.h" 15 #include "include/hw/misc/aspeed_scu.h" 16 #include "qapi/error.h" 17 #include "qapi/visitor.h" 18 #include "hw/irq.h" 19 #include "migration/vmstate.h" 20 21 #define GPIOS_PER_REG 32 22 #define GPIOS_PER_SET GPIOS_PER_REG 23 #define GPIO_PIN_GAP_SIZE 4 24 #define GPIOS_PER_GROUP 8 25 #define GPIO_GROUP_SHIFT 3 26 27 /* GPIO Source Types */ 28 #define ASPEED_CMD_SRC_MASK 0x01010101 29 #define ASPEED_SOURCE_ARM 0 30 #define ASPEED_SOURCE_LPC 1 31 #define ASPEED_SOURCE_COPROCESSOR 2 32 #define ASPEED_SOURCE_RESERVED 3 33 34 /* GPIO Interrupt Triggers */ 35 /* 36 * For each set of gpios there are three sensitivity registers that control 37 * the interrupt trigger mode. 38 * 39 * | 2 | 1 | 0 | trigger mode 40 * ----------------------------- 41 * | 0 | 0 | 0 | falling-edge 42 * | 0 | 0 | 1 | rising-edge 43 * | 0 | 1 | 0 | level-low 44 * | 0 | 1 | 1 | level-high 45 * | 1 | X | X | dual-edge 46 */ 47 #define ASPEED_FALLING_EDGE 0 48 #define ASPEED_RISING_EDGE 1 49 #define ASPEED_LEVEL_LOW 2 50 #define ASPEED_LEVEL_HIGH 3 51 #define ASPEED_DUAL_EDGE 4 52 53 /* GPIO Register Address Offsets */ 54 #define GPIO_ABCD_DATA_VALUE (0x000 >> 2) 55 #define GPIO_ABCD_DIRECTION (0x004 >> 2) 56 #define GPIO_ABCD_INT_ENABLE (0x008 >> 2) 57 #define GPIO_ABCD_INT_SENS_0 (0x00C >> 2) 58 #define GPIO_ABCD_INT_SENS_1 (0x010 >> 2) 59 #define GPIO_ABCD_INT_SENS_2 (0x014 >> 2) 60 #define GPIO_ABCD_INT_STATUS (0x018 >> 2) 61 #define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2) 62 #define GPIO_EFGH_DATA_VALUE (0x020 >> 2) 63 #define GPIO_EFGH_DIRECTION (0x024 >> 2) 64 #define GPIO_EFGH_INT_ENABLE (0x028 >> 2) 65 #define GPIO_EFGH_INT_SENS_0 (0x02C >> 2) 66 #define GPIO_EFGH_INT_SENS_1 (0x030 >> 2) 67 #define GPIO_EFGH_INT_SENS_2 (0x034 >> 2) 68 #define GPIO_EFGH_INT_STATUS (0x038 >> 2) 69 #define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2) 70 #define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2) 71 #define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2) 72 #define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2) 73 #define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2) 74 #define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2) 75 #define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2) 76 #define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2) 77 #define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2) 78 #define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2) 79 #define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2) 80 #define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2) 81 #define GPIO_IJKL_DATA_VALUE (0x070 >> 2) 82 #define GPIO_IJKL_DIRECTION (0x074 >> 2) 83 #define GPIO_MNOP_DATA_VALUE (0x078 >> 2) 84 #define GPIO_MNOP_DIRECTION (0x07C >> 2) 85 #define GPIO_QRST_DATA_VALUE (0x080 >> 2) 86 #define GPIO_QRST_DIRECTION (0x084 >> 2) 87 #define GPIO_UVWX_DATA_VALUE (0x088 >> 2) 88 #define GPIO_UVWX_DIRECTION (0x08C >> 2) 89 #define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2) 90 #define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2) 91 #define GPIO_IJKL_INT_ENABLE (0x098 >> 2) 92 #define GPIO_IJKL_INT_SENS_0 (0x09C >> 2) 93 #define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2) 94 #define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2) 95 #define GPIO_IJKL_INT_STATUS (0x0A8 >> 2) 96 #define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2) 97 #define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2) 98 #define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2) 99 #define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2) 100 #define GPIO_ABCD_DATA_READ (0x0C0 >> 2) 101 #define GPIO_EFGH_DATA_READ (0x0C4 >> 2) 102 #define GPIO_IJKL_DATA_READ (0x0C8 >> 2) 103 #define GPIO_MNOP_DATA_READ (0x0CC >> 2) 104 #define GPIO_QRST_DATA_READ (0x0D0 >> 2) 105 #define GPIO_UVWX_DATA_READ (0x0D4 >> 2) 106 #define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2) 107 #define GPIO_AC_DATA_READ (0x0DC >> 2) 108 #define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2) 109 #define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2) 110 #define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2) 111 #define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2) 112 #define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2) 113 #define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2) 114 #define GPIO_MNOP_INT_STATUS (0x0F8 >> 2) 115 #define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2) 116 #define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2) 117 #define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2) 118 #define GPIO_MNOP_INPUT_MASK (0x108 >> 2) 119 #define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2) 120 #define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2) 121 #define GPIO_QRST_INT_ENABLE (0x118 >> 2) 122 #define GPIO_QRST_INT_SENS_0 (0x11C >> 2) 123 #define GPIO_QRST_INT_SENS_1 (0x120 >> 2) 124 #define GPIO_QRST_INT_SENS_2 (0x124 >> 2) 125 #define GPIO_QRST_INT_STATUS (0x128 >> 2) 126 #define GPIO_QRST_RESET_TOLERANT (0x12C >> 2) 127 #define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2) 128 #define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2) 129 #define GPIO_QRST_INPUT_MASK (0x138 >> 2) 130 #define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2) 131 #define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2) 132 #define GPIO_UVWX_INT_ENABLE (0x148 >> 2) 133 #define GPIO_UVWX_INT_SENS_0 (0x14C >> 2) 134 #define GPIO_UVWX_INT_SENS_1 (0x150 >> 2) 135 #define GPIO_UVWX_INT_SENS_2 (0x154 >> 2) 136 #define GPIO_UVWX_INT_STATUS (0x158 >> 2) 137 #define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2) 138 #define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2) 139 #define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2) 140 #define GPIO_UVWX_INPUT_MASK (0x168 >> 2) 141 #define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2) 142 #define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2) 143 #define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2) 144 #define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2) 145 #define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2) 146 #define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2) 147 #define GPIO_YZAAAB_INT_STATUS (0x188 >> 2) 148 #define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2) 149 #define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2) 150 #define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2) 151 #define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2) 152 #define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2) 153 #define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2) 154 #define GPIO_AC_INT_ENABLE (0x1A8 >> 2) 155 #define GPIO_AC_INT_SENS_0 (0x1AC >> 2) 156 #define GPIO_AC_INT_SENS_1 (0x1B0 >> 2) 157 #define GPIO_AC_INT_SENS_2 (0x1B4 >> 2) 158 #define GPIO_AC_INT_STATUS (0x1B8 >> 2) 159 #define GPIO_AC_RESET_TOLERANT (0x1BC >> 2) 160 #define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2) 161 #define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2) 162 #define GPIO_AC_INPUT_MASK (0x1C8 >> 2) 163 #define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2) 164 #define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2) 165 #define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2) 166 #define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2) 167 #define GPIO_AC_DATA_VALUE (0x1E8 >> 2) 168 #define GPIO_AC_DIRECTION (0x1EC >> 2) 169 #define GPIO_3_6V_MEM_SIZE 0x1F0 170 #define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2) 171 172 /* AST2600 only - 1.8V gpios */ 173 /* 174 * The AST2600 has same 3.6V gpios as the AST2400 (memory offsets 0x0-0x198) 175 * and addtional 1.8V gpios (memory offsets 0x800-0x9D4). 176 */ 177 #define GPIO_1_8V_REG_OFFSET 0x800 178 #define GPIO_1_8V_ABCD_DATA_VALUE ((0x800 - GPIO_1_8V_REG_OFFSET) >> 2) 179 #define GPIO_1_8V_ABCD_DIRECTION ((0x804 - GPIO_1_8V_REG_OFFSET) >> 2) 180 #define GPIO_1_8V_ABCD_INT_ENABLE ((0x808 - GPIO_1_8V_REG_OFFSET) >> 2) 181 #define GPIO_1_8V_ABCD_INT_SENS_0 ((0x80C - GPIO_1_8V_REG_OFFSET) >> 2) 182 #define GPIO_1_8V_ABCD_INT_SENS_1 ((0x810 - GPIO_1_8V_REG_OFFSET) >> 2) 183 #define GPIO_1_8V_ABCD_INT_SENS_2 ((0x814 - GPIO_1_8V_REG_OFFSET) >> 2) 184 #define GPIO_1_8V_ABCD_INT_STATUS ((0x818 - GPIO_1_8V_REG_OFFSET) >> 2) 185 #define GPIO_1_8V_ABCD_RESET_TOLERANT ((0x81C - GPIO_1_8V_REG_OFFSET) >> 2) 186 #define GPIO_1_8V_E_DATA_VALUE ((0x820 - GPIO_1_8V_REG_OFFSET) >> 2) 187 #define GPIO_1_8V_E_DIRECTION ((0x824 - GPIO_1_8V_REG_OFFSET) >> 2) 188 #define GPIO_1_8V_E_INT_ENABLE ((0x828 - GPIO_1_8V_REG_OFFSET) >> 2) 189 #define GPIO_1_8V_E_INT_SENS_0 ((0x82C - GPIO_1_8V_REG_OFFSET) >> 2) 190 #define GPIO_1_8V_E_INT_SENS_1 ((0x830 - GPIO_1_8V_REG_OFFSET) >> 2) 191 #define GPIO_1_8V_E_INT_SENS_2 ((0x834 - GPIO_1_8V_REG_OFFSET) >> 2) 192 #define GPIO_1_8V_E_INT_STATUS ((0x838 - GPIO_1_8V_REG_OFFSET) >> 2) 193 #define GPIO_1_8V_E_RESET_TOLERANT ((0x83C - GPIO_1_8V_REG_OFFSET) >> 2) 194 #define GPIO_1_8V_ABCD_DEBOUNCE_1 ((0x840 - GPIO_1_8V_REG_OFFSET) >> 2) 195 #define GPIO_1_8V_ABCD_DEBOUNCE_2 ((0x844 - GPIO_1_8V_REG_OFFSET) >> 2) 196 #define GPIO_1_8V_E_DEBOUNCE_1 ((0x848 - GPIO_1_8V_REG_OFFSET) >> 2) 197 #define GPIO_1_8V_E_DEBOUNCE_2 ((0x84C - GPIO_1_8V_REG_OFFSET) >> 2) 198 #define GPIO_1_8V_DEBOUNCE_TIME_1 ((0x850 - GPIO_1_8V_REG_OFFSET) >> 2) 199 #define GPIO_1_8V_DEBOUNCE_TIME_2 ((0x854 - GPIO_1_8V_REG_OFFSET) >> 2) 200 #define GPIO_1_8V_DEBOUNCE_TIME_3 ((0x858 - GPIO_1_8V_REG_OFFSET) >> 2) 201 #define GPIO_1_8V_ABCD_COMMAND_SRC_0 ((0x860 - GPIO_1_8V_REG_OFFSET) >> 2) 202 #define GPIO_1_8V_ABCD_COMMAND_SRC_1 ((0x864 - GPIO_1_8V_REG_OFFSET) >> 2) 203 #define GPIO_1_8V_E_COMMAND_SRC_0 ((0x868 - GPIO_1_8V_REG_OFFSET) >> 2) 204 #define GPIO_1_8V_E_COMMAND_SRC_1 ((0x86C - GPIO_1_8V_REG_OFFSET) >> 2) 205 #define GPIO_1_8V_ABCD_DATA_READ ((0x8C0 - GPIO_1_8V_REG_OFFSET) >> 2) 206 #define GPIO_1_8V_E_DATA_READ ((0x8C4 - GPIO_1_8V_REG_OFFSET) >> 2) 207 #define GPIO_1_8V_ABCD_INPUT_MASK ((0x9D0 - GPIO_1_8V_REG_OFFSET) >> 2) 208 #define GPIO_1_8V_E_INPUT_MASK ((0x9D4 - GPIO_1_8V_REG_OFFSET) >> 2) 209 #define GPIO_1_8V_MEM_SIZE 0x9D8 210 #define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \ 211 GPIO_1_8V_REG_OFFSET) >> 2) 212 #define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE) 213 214 static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) 215 { 216 uint32_t falling_edge = 0, rising_edge = 0; 217 uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1) 218 | extract32(regs->int_sens_1, gpio, 1) << 1 219 | extract32(regs->int_sens_2, gpio, 1) << 2; 220 uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1); 221 uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1); 222 223 if (!gpio_int_enabled) { 224 return 0; 225 } 226 227 /* Detect edges */ 228 if (gpio_curr_high && !gpio_prev_high) { 229 rising_edge = 1; 230 } else if (!gpio_curr_high && gpio_prev_high) { 231 falling_edge = 1; 232 } 233 234 if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) || 235 ((int_trigger == ASPEED_RISING_EDGE) && rising_edge) || 236 ((int_trigger == ASPEED_LEVEL_LOW) && !gpio_curr_high) || 237 ((int_trigger == ASPEED_LEVEL_HIGH) && gpio_curr_high) || 238 ((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge))) 239 { 240 regs->int_status = deposit32(regs->int_status, gpio, 1, 1); 241 return 1; 242 } 243 return 0; 244 } 245 246 #define nested_struct_index(ta, pa, m, tb, pb) \ 247 (pb - ((tb *)(((char *)pa) + offsetof(ta, m)))) 248 249 static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s, GPIOSets *regs) 250 { 251 return nested_struct_index(AspeedGPIOState, s, sets, GPIOSets, regs); 252 } 253 254 static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs, 255 uint32_t value) 256 { 257 uint32_t input_mask = regs->input_mask; 258 uint32_t direction = regs->direction; 259 uint32_t old = regs->data_value; 260 uint32_t new = value; 261 uint32_t diff; 262 int gpio; 263 264 diff = old ^ new; 265 if (diff) { 266 for (gpio = 0; gpio < GPIOS_PER_REG; gpio++) { 267 uint32_t mask = 1 << gpio; 268 269 /* If the gpio needs to be updated... */ 270 if (!(diff & mask)) { 271 continue; 272 } 273 274 /* ...and we're output or not input-masked... */ 275 if (!(direction & mask) && (input_mask & mask)) { 276 continue; 277 } 278 279 /* ...then update the state. */ 280 if (mask & new) { 281 regs->data_value |= mask; 282 } else { 283 regs->data_value &= ~mask; 284 } 285 286 /* If the gpio is set to output... */ 287 if (direction & mask) { 288 /* ...trigger the line-state IRQ */ 289 ptrdiff_t set = aspeed_gpio_set_idx(s, regs); 290 size_t offset = set * GPIOS_PER_SET + gpio; 291 qemu_set_irq(s->gpios[offset], !!(new & mask)); 292 } else { 293 /* ...otherwise if we meet the line's current IRQ policy... */ 294 if (aspeed_evaluate_irq(regs, old & mask, gpio)) { 295 /* ...trigger the VIC IRQ */ 296 s->pending++; 297 } 298 } 299 } 300 } 301 qemu_set_irq(s->irq, !!(s->pending)); 302 } 303 304 static uint32_t aspeed_adjust_pin(AspeedGPIOState *s, uint32_t pin) 305 { 306 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 307 /* 308 * The 2500 has a 4 pin gap in group AB and the 2400 has a 4 pin 309 * gap in group Y (and only four pins in AB but this is the last group so 310 * it doesn't matter). 311 */ 312 if (agc->gap && pin >= agc->gap) { 313 pin += GPIO_PIN_GAP_SIZE; 314 } 315 316 return pin; 317 } 318 319 static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx, 320 uint32_t pin) 321 { 322 uint32_t reg_val; 323 uint32_t pin_mask = 1 << pin; 324 325 reg_val = s->sets[set_idx].data_value; 326 327 return !!(reg_val & pin_mask); 328 } 329 330 static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx, 331 uint32_t pin, bool level) 332 { 333 uint32_t value = s->sets[set_idx].data_value; 334 uint32_t pin_mask = 1 << pin; 335 336 if (level) { 337 value |= pin_mask; 338 } else { 339 value &= !pin_mask; 340 } 341 342 aspeed_gpio_update(s, &s->sets[set_idx], value); 343 } 344 345 /* 346 * | src_1 | src_2 | source | 347 * |-----------------------------| 348 * | 0 | 0 | ARM | 349 * | 0 | 1 | LPC | 350 * | 1 | 0 | Coprocessor| 351 * | 1 | 1 | Reserved | 352 * 353 * Once the source of a set is programmed, corresponding bits in the 354 * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and 355 * debounce registers can only be written by the source. 356 * 357 * Source is ARM by default 358 * only bits 24, 16, 8, and 0 can be set 359 * 360 * we don't currently have a model for the LPC or Coprocessor 361 */ 362 static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value, 363 uint32_t value) 364 { 365 int i; 366 int cmd_source; 367 368 /* assume the source is always ARM for now */ 369 int source = ASPEED_SOURCE_ARM; 370 371 uint32_t new_value = 0; 372 373 /* for each group in set */ 374 for (i = 0; i < GPIOS_PER_REG; i += GPIOS_PER_GROUP) { 375 cmd_source = extract32(regs->cmd_source_0, i, 1) 376 | (extract32(regs->cmd_source_1, i, 1) << 1); 377 378 if (source == cmd_source) { 379 new_value |= (0xff << i) & value; 380 } else { 381 new_value |= (0xff << i) & old_value; 382 } 383 } 384 return new_value; 385 } 386 387 static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = { 388 /* Set ABCD */ 389 [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value }, 390 [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction }, 391 [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable }, 392 [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 }, 393 [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 }, 394 [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 }, 395 [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status }, 396 [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant }, 397 [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 }, 398 [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 }, 399 [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 }, 400 [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 }, 401 [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read }, 402 [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask }, 403 /* Set EFGH */ 404 [GPIO_EFGH_DATA_VALUE] = { 1, gpio_reg_data_value }, 405 [GPIO_EFGH_DIRECTION] = { 1, gpio_reg_direction }, 406 [GPIO_EFGH_INT_ENABLE] = { 1, gpio_reg_int_enable }, 407 [GPIO_EFGH_INT_SENS_0] = { 1, gpio_reg_int_sens_0 }, 408 [GPIO_EFGH_INT_SENS_1] = { 1, gpio_reg_int_sens_1 }, 409 [GPIO_EFGH_INT_SENS_2] = { 1, gpio_reg_int_sens_2 }, 410 [GPIO_EFGH_INT_STATUS] = { 1, gpio_reg_int_status }, 411 [GPIO_EFGH_RESET_TOLERANT] = { 1, gpio_reg_reset_tolerant }, 412 [GPIO_EFGH_DEBOUNCE_1] = { 1, gpio_reg_debounce_1 }, 413 [GPIO_EFGH_DEBOUNCE_2] = { 1, gpio_reg_debounce_2 }, 414 [GPIO_EFGH_COMMAND_SRC_0] = { 1, gpio_reg_cmd_source_0 }, 415 [GPIO_EFGH_COMMAND_SRC_1] = { 1, gpio_reg_cmd_source_1 }, 416 [GPIO_EFGH_DATA_READ] = { 1, gpio_reg_data_read }, 417 [GPIO_EFGH_INPUT_MASK] = { 1, gpio_reg_input_mask }, 418 /* Set IJKL */ 419 [GPIO_IJKL_DATA_VALUE] = { 2, gpio_reg_data_value }, 420 [GPIO_IJKL_DIRECTION] = { 2, gpio_reg_direction }, 421 [GPIO_IJKL_INT_ENABLE] = { 2, gpio_reg_int_enable }, 422 [GPIO_IJKL_INT_SENS_0] = { 2, gpio_reg_int_sens_0 }, 423 [GPIO_IJKL_INT_SENS_1] = { 2, gpio_reg_int_sens_1 }, 424 [GPIO_IJKL_INT_SENS_2] = { 2, gpio_reg_int_sens_2 }, 425 [GPIO_IJKL_INT_STATUS] = { 2, gpio_reg_int_status }, 426 [GPIO_IJKL_RESET_TOLERANT] = { 2, gpio_reg_reset_tolerant }, 427 [GPIO_IJKL_DEBOUNCE_1] = { 2, gpio_reg_debounce_1 }, 428 [GPIO_IJKL_DEBOUNCE_2] = { 2, gpio_reg_debounce_2 }, 429 [GPIO_IJKL_COMMAND_SRC_0] = { 2, gpio_reg_cmd_source_0 }, 430 [GPIO_IJKL_COMMAND_SRC_1] = { 2, gpio_reg_cmd_source_1 }, 431 [GPIO_IJKL_DATA_READ] = { 2, gpio_reg_data_read }, 432 [GPIO_IJKL_INPUT_MASK] = { 2, gpio_reg_input_mask }, 433 /* Set MNOP */ 434 [GPIO_MNOP_DATA_VALUE] = { 3, gpio_reg_data_value }, 435 [GPIO_MNOP_DIRECTION] = { 3, gpio_reg_direction }, 436 [GPIO_MNOP_INT_ENABLE] = { 3, gpio_reg_int_enable }, 437 [GPIO_MNOP_INT_SENS_0] = { 3, gpio_reg_int_sens_0 }, 438 [GPIO_MNOP_INT_SENS_1] = { 3, gpio_reg_int_sens_1 }, 439 [GPIO_MNOP_INT_SENS_2] = { 3, gpio_reg_int_sens_2 }, 440 [GPIO_MNOP_INT_STATUS] = { 3, gpio_reg_int_status }, 441 [GPIO_MNOP_RESET_TOLERANT] = { 3, gpio_reg_reset_tolerant }, 442 [GPIO_MNOP_DEBOUNCE_1] = { 3, gpio_reg_debounce_1 }, 443 [GPIO_MNOP_DEBOUNCE_2] = { 3, gpio_reg_debounce_2 }, 444 [GPIO_MNOP_COMMAND_SRC_0] = { 3, gpio_reg_cmd_source_0 }, 445 [GPIO_MNOP_COMMAND_SRC_1] = { 3, gpio_reg_cmd_source_1 }, 446 [GPIO_MNOP_DATA_READ] = { 3, gpio_reg_data_read }, 447 [GPIO_MNOP_INPUT_MASK] = { 3, gpio_reg_input_mask }, 448 /* Set QRST */ 449 [GPIO_QRST_DATA_VALUE] = { 4, gpio_reg_data_value }, 450 [GPIO_QRST_DIRECTION] = { 4, gpio_reg_direction }, 451 [GPIO_QRST_INT_ENABLE] = { 4, gpio_reg_int_enable }, 452 [GPIO_QRST_INT_SENS_0] = { 4, gpio_reg_int_sens_0 }, 453 [GPIO_QRST_INT_SENS_1] = { 4, gpio_reg_int_sens_1 }, 454 [GPIO_QRST_INT_SENS_2] = { 4, gpio_reg_int_sens_2 }, 455 [GPIO_QRST_INT_STATUS] = { 4, gpio_reg_int_status }, 456 [GPIO_QRST_RESET_TOLERANT] = { 4, gpio_reg_reset_tolerant }, 457 [GPIO_QRST_DEBOUNCE_1] = { 4, gpio_reg_debounce_1 }, 458 [GPIO_QRST_DEBOUNCE_2] = { 4, gpio_reg_debounce_2 }, 459 [GPIO_QRST_COMMAND_SRC_0] = { 4, gpio_reg_cmd_source_0 }, 460 [GPIO_QRST_COMMAND_SRC_1] = { 4, gpio_reg_cmd_source_1 }, 461 [GPIO_QRST_DATA_READ] = { 4, gpio_reg_data_read }, 462 [GPIO_QRST_INPUT_MASK] = { 4, gpio_reg_input_mask }, 463 /* Set UVWX */ 464 [GPIO_UVWX_DATA_VALUE] = { 5, gpio_reg_data_value }, 465 [GPIO_UVWX_DIRECTION] = { 5, gpio_reg_direction }, 466 [GPIO_UVWX_INT_ENABLE] = { 5, gpio_reg_int_enable }, 467 [GPIO_UVWX_INT_SENS_0] = { 5, gpio_reg_int_sens_0 }, 468 [GPIO_UVWX_INT_SENS_1] = { 5, gpio_reg_int_sens_1 }, 469 [GPIO_UVWX_INT_SENS_2] = { 5, gpio_reg_int_sens_2 }, 470 [GPIO_UVWX_INT_STATUS] = { 5, gpio_reg_int_status }, 471 [GPIO_UVWX_RESET_TOLERANT] = { 5, gpio_reg_reset_tolerant }, 472 [GPIO_UVWX_DEBOUNCE_1] = { 5, gpio_reg_debounce_1 }, 473 [GPIO_UVWX_DEBOUNCE_2] = { 5, gpio_reg_debounce_2 }, 474 [GPIO_UVWX_COMMAND_SRC_0] = { 5, gpio_reg_cmd_source_0 }, 475 [GPIO_UVWX_COMMAND_SRC_1] = { 5, gpio_reg_cmd_source_1 }, 476 [GPIO_UVWX_DATA_READ] = { 5, gpio_reg_data_read }, 477 [GPIO_UVWX_INPUT_MASK] = { 5, gpio_reg_input_mask }, 478 /* Set YZAAAB */ 479 [GPIO_YZAAAB_DATA_VALUE] = { 6, gpio_reg_data_value }, 480 [GPIO_YZAAAB_DIRECTION] = { 6, gpio_reg_direction }, 481 [GPIO_YZAAAB_INT_ENABLE] = { 6, gpio_reg_int_enable }, 482 [GPIO_YZAAAB_INT_SENS_0] = { 6, gpio_reg_int_sens_0 }, 483 [GPIO_YZAAAB_INT_SENS_1] = { 6, gpio_reg_int_sens_1 }, 484 [GPIO_YZAAAB_INT_SENS_2] = { 6, gpio_reg_int_sens_2 }, 485 [GPIO_YZAAAB_INT_STATUS] = { 6, gpio_reg_int_status }, 486 [GPIO_YZAAAB_RESET_TOLERANT] = { 6, gpio_reg_reset_tolerant }, 487 [GPIO_YZAAAB_DEBOUNCE_1] = { 6, gpio_reg_debounce_1 }, 488 [GPIO_YZAAAB_DEBOUNCE_2] = { 6, gpio_reg_debounce_2 }, 489 [GPIO_YZAAAB_COMMAND_SRC_0] = { 6, gpio_reg_cmd_source_0 }, 490 [GPIO_YZAAAB_COMMAND_SRC_1] = { 6, gpio_reg_cmd_source_1 }, 491 [GPIO_YZAAAB_DATA_READ] = { 6, gpio_reg_data_read }, 492 [GPIO_YZAAAB_INPUT_MASK] = { 6, gpio_reg_input_mask }, 493 /* Set AC (ast2500 only) */ 494 [GPIO_AC_DATA_VALUE] = { 7, gpio_reg_data_value }, 495 [GPIO_AC_DIRECTION] = { 7, gpio_reg_direction }, 496 [GPIO_AC_INT_ENABLE] = { 7, gpio_reg_int_enable }, 497 [GPIO_AC_INT_SENS_0] = { 7, gpio_reg_int_sens_0 }, 498 [GPIO_AC_INT_SENS_1] = { 7, gpio_reg_int_sens_1 }, 499 [GPIO_AC_INT_SENS_2] = { 7, gpio_reg_int_sens_2 }, 500 [GPIO_AC_INT_STATUS] = { 7, gpio_reg_int_status }, 501 [GPIO_AC_RESET_TOLERANT] = { 7, gpio_reg_reset_tolerant }, 502 [GPIO_AC_DEBOUNCE_1] = { 7, gpio_reg_debounce_1 }, 503 [GPIO_AC_DEBOUNCE_2] = { 7, gpio_reg_debounce_2 }, 504 [GPIO_AC_COMMAND_SRC_0] = { 7, gpio_reg_cmd_source_0 }, 505 [GPIO_AC_COMMAND_SRC_1] = { 7, gpio_reg_cmd_source_1 }, 506 [GPIO_AC_DATA_READ] = { 7, gpio_reg_data_read }, 507 [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask }, 508 }; 509 510 static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = { 511 /* 1.8V Set ABCD */ 512 [GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value}, 513 [GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction}, 514 [GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable}, 515 [GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0}, 516 [GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1}, 517 [GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2}, 518 [GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status}, 519 [GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant}, 520 [GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1}, 521 [GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2}, 522 [GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0}, 523 [GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1}, 524 [GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read}, 525 [GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask}, 526 /* 1.8V Set E */ 527 [GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value}, 528 [GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction}, 529 [GPIO_1_8V_E_INT_ENABLE] = {1, gpio_reg_int_enable}, 530 [GPIO_1_8V_E_INT_SENS_0] = {1, gpio_reg_int_sens_0}, 531 [GPIO_1_8V_E_INT_SENS_1] = {1, gpio_reg_int_sens_1}, 532 [GPIO_1_8V_E_INT_SENS_2] = {1, gpio_reg_int_sens_2}, 533 [GPIO_1_8V_E_INT_STATUS] = {1, gpio_reg_int_status}, 534 [GPIO_1_8V_E_RESET_TOLERANT] = {1, gpio_reg_reset_tolerant}, 535 [GPIO_1_8V_E_DEBOUNCE_1] = {1, gpio_reg_debounce_1}, 536 [GPIO_1_8V_E_DEBOUNCE_2] = {1, gpio_reg_debounce_2}, 537 [GPIO_1_8V_E_COMMAND_SRC_0] = {1, gpio_reg_cmd_source_0}, 538 [GPIO_1_8V_E_COMMAND_SRC_1] = {1, gpio_reg_cmd_source_1}, 539 [GPIO_1_8V_E_DATA_READ] = {1, gpio_reg_data_read}, 540 [GPIO_1_8V_E_INPUT_MASK] = {1, gpio_reg_input_mask}, 541 }; 542 543 static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) 544 { 545 AspeedGPIOState *s = ASPEED_GPIO(opaque); 546 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 547 uint64_t idx = -1; 548 const AspeedGPIOReg *reg; 549 GPIOSets *set; 550 551 idx = offset >> 2; 552 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 553 idx -= GPIO_DEBOUNCE_TIME_1; 554 return (uint64_t) s->debounce_regs[idx]; 555 } 556 557 reg = &agc->reg_table[idx]; 558 if (reg->set_idx >= agc->nr_gpio_sets) { 559 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 560 HWADDR_PRIx"\n", __func__, offset); 561 return 0; 562 } 563 564 set = &s->sets[reg->set_idx]; 565 switch (reg->type) { 566 case gpio_reg_data_value: 567 return set->data_value; 568 case gpio_reg_direction: 569 return set->direction; 570 case gpio_reg_int_enable: 571 return set->int_enable; 572 case gpio_reg_int_sens_0: 573 return set->int_sens_0; 574 case gpio_reg_int_sens_1: 575 return set->int_sens_1; 576 case gpio_reg_int_sens_2: 577 return set->int_sens_2; 578 case gpio_reg_int_status: 579 return set->int_status; 580 case gpio_reg_reset_tolerant: 581 return set->reset_tol; 582 case gpio_reg_debounce_1: 583 return set->debounce_1; 584 case gpio_reg_debounce_2: 585 return set->debounce_2; 586 case gpio_reg_cmd_source_0: 587 return set->cmd_source_0; 588 case gpio_reg_cmd_source_1: 589 return set->cmd_source_1; 590 case gpio_reg_data_read: 591 return set->data_read; 592 case gpio_reg_input_mask: 593 return set->input_mask; 594 default: 595 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 596 HWADDR_PRIx"\n", __func__, offset); 597 return 0; 598 }; 599 } 600 601 static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, 602 uint32_t size) 603 { 604 AspeedGPIOState *s = ASPEED_GPIO(opaque); 605 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 606 const GPIOSetProperties *props; 607 uint64_t idx = -1; 608 const AspeedGPIOReg *reg; 609 GPIOSets *set; 610 uint32_t cleared; 611 612 idx = offset >> 2; 613 if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { 614 idx -= GPIO_DEBOUNCE_TIME_1; 615 s->debounce_regs[idx] = (uint32_t) data; 616 return; 617 } 618 619 reg = &agc->reg_table[idx]; 620 if (reg->set_idx >= agc->nr_gpio_sets) { 621 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 622 HWADDR_PRIx"\n", __func__, offset); 623 return; 624 } 625 626 set = &s->sets[reg->set_idx]; 627 props = &agc->props[reg->set_idx]; 628 629 switch (reg->type) { 630 case gpio_reg_data_value: 631 data &= props->output; 632 data = update_value_control_source(set, set->data_value, data); 633 set->data_read = data; 634 aspeed_gpio_update(s, set, data); 635 return; 636 case gpio_reg_direction: 637 /* 638 * where data is the value attempted to be written to the pin: 639 * pin type | input mask | output mask | expected value 640 * ------------------------------------------------------------ 641 * bidirectional | 1 | 1 | data 642 * input only | 1 | 0 | 0 643 * output only | 0 | 1 | 1 644 * no pin / gap | 0 | 0 | 0 645 * 646 * which is captured by: 647 * data = ( data | ~input) & output; 648 */ 649 data = (data | ~props->input) & props->output; 650 set->direction = update_value_control_source(set, set->direction, data); 651 break; 652 case gpio_reg_int_enable: 653 set->int_enable = update_value_control_source(set, set->int_enable, 654 data); 655 break; 656 case gpio_reg_int_sens_0: 657 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, 658 data); 659 break; 660 case gpio_reg_int_sens_1: 661 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, 662 data); 663 break; 664 case gpio_reg_int_sens_2: 665 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, 666 data); 667 break; 668 case gpio_reg_int_status: 669 cleared = ctpop32(data & set->int_status); 670 if (s->pending && cleared) { 671 assert(s->pending >= cleared); 672 s->pending -= cleared; 673 } 674 set->int_status &= ~data; 675 break; 676 case gpio_reg_reset_tolerant: 677 set->reset_tol = update_value_control_source(set, set->reset_tol, 678 data); 679 return; 680 case gpio_reg_debounce_1: 681 set->debounce_1 = update_value_control_source(set, set->debounce_1, 682 data); 683 return; 684 case gpio_reg_debounce_2: 685 set->debounce_2 = update_value_control_source(set, set->debounce_2, 686 data); 687 return; 688 case gpio_reg_cmd_source_0: 689 set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK; 690 return; 691 case gpio_reg_cmd_source_1: 692 set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK; 693 return; 694 case gpio_reg_data_read: 695 /* Read only register */ 696 return; 697 case gpio_reg_input_mask: 698 /* 699 * feeds into interrupt generation 700 * 0: read from data value reg will be updated 701 * 1: read from data value reg will not be updated 702 */ 703 set->input_mask = data & props->input; 704 break; 705 default: 706 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 707 HWADDR_PRIx"\n", __func__, offset); 708 return; 709 } 710 aspeed_gpio_update(s, set, set->data_value); 711 return; 712 } 713 714 static int get_set_idx(AspeedGPIOState *s, const char *group, int *group_idx) 715 { 716 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 717 int set_idx, g_idx = *group_idx; 718 719 for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) { 720 const GPIOSetProperties *set_props = &agc->props[set_idx]; 721 for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) { 722 if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) { 723 *group_idx = g_idx; 724 return set_idx; 725 } 726 } 727 } 728 return -1; 729 } 730 731 static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name, 732 void *opaque, Error **errp) 733 { 734 int pin = 0xfff; 735 bool level = true; 736 char group[4]; 737 AspeedGPIOState *s = ASPEED_GPIO(obj); 738 int set_idx, group_idx = 0; 739 740 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 741 /* 1.8V gpio */ 742 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 743 error_setg(errp, "%s: error reading %s", __func__, name); 744 return; 745 } 746 } 747 set_idx = get_set_idx(s, group, &group_idx); 748 if (set_idx == -1) { 749 error_setg(errp, "%s: invalid group %s", __func__, group); 750 return; 751 } 752 pin = pin + group_idx * GPIOS_PER_GROUP; 753 level = aspeed_gpio_get_pin_level(s, set_idx, pin); 754 visit_type_bool(v, name, &level, errp); 755 } 756 757 static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, 758 void *opaque, Error **errp) 759 { 760 Error *local_err = NULL; 761 bool level; 762 int pin = 0xfff; 763 char group[4]; 764 AspeedGPIOState *s = ASPEED_GPIO(obj); 765 int set_idx, group_idx = 0; 766 767 visit_type_bool(v, name, &level, &local_err); 768 if (local_err) { 769 error_propagate(errp, local_err); 770 return; 771 } 772 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { 773 /* 1.8V gpio */ 774 if (sscanf(name, "gpio%3[18A-E]%1d", group, &pin) != 2) { 775 error_setg(errp, "%s: error reading %s", __func__, name); 776 return; 777 } 778 } 779 set_idx = get_set_idx(s, group, &group_idx); 780 if (set_idx == -1) { 781 error_setg(errp, "%s: invalid group %s", __func__, group); 782 return; 783 } 784 pin = pin + group_idx * GPIOS_PER_GROUP; 785 aspeed_gpio_set_pin_level(s, set_idx, pin, level); 786 } 787 788 /****************** Setup functions ******************/ 789 static const GPIOSetProperties ast2400_set_props[] = { 790 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 791 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 792 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 793 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 794 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 795 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 796 [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, 797 }; 798 799 static const GPIOSetProperties ast2500_set_props[] = { 800 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 801 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 802 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 803 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 804 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 805 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 806 [6] = {0xffffff0f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, 807 [7] = {0x000000ff, 0x000000ff, {"AC"} }, 808 }; 809 810 static GPIOSetProperties ast2600_3_6v_set_props[] = { 811 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, 812 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, 813 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, 814 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, 815 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, 816 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, 817 [6] = {0xffff0000, 0x0fff0000, {"Y", "Z", "", ""} }, 818 }; 819 820 static GPIOSetProperties ast2600_1_8v_set_props[] = { 821 [0] = {0xffffffff, 0xffffffff, {"18A", "18B", "18C", "18D"} }, 822 [1] = {0x0000000f, 0x0000000f, {"18E"} }, 823 }; 824 825 static const MemoryRegionOps aspeed_gpio_ops = { 826 .read = aspeed_gpio_read, 827 .write = aspeed_gpio_write, 828 .endianness = DEVICE_LITTLE_ENDIAN, 829 .valid.min_access_size = 4, 830 .valid.max_access_size = 4, 831 }; 832 833 static void aspeed_gpio_reset(DeviceState *dev) 834 { 835 AspeedGPIOState *s = ASPEED_GPIO(dev); 836 837 /* TODO: respect the reset tolerance registers */ 838 memset(s->sets, 0, sizeof(s->sets)); 839 } 840 841 static void aspeed_gpio_realize(DeviceState *dev, Error **errp) 842 { 843 AspeedGPIOState *s = ASPEED_GPIO(dev); 844 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 845 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 846 int pin; 847 848 /* Interrupt parent line */ 849 sysbus_init_irq(sbd, &s->irq); 850 851 /* Individual GPIOs */ 852 for (pin = 0; pin < agc->nr_gpio_pins; pin++) { 853 sysbus_init_irq(sbd, &s->gpios[pin]); 854 } 855 856 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, 857 TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE); 858 859 sysbus_init_mmio(sbd, &s->iomem); 860 } 861 862 static void aspeed_gpio_init(Object *obj) 863 { 864 AspeedGPIOState *s = ASPEED_GPIO(obj); 865 AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); 866 int pin; 867 868 for (pin = 0; pin < agc->nr_gpio_pins; pin++) { 869 char *name; 870 int set_idx = pin / GPIOS_PER_SET; 871 int pin_idx = aspeed_adjust_pin(s, pin) - (set_idx * GPIOS_PER_SET); 872 int group_idx = pin_idx >> GPIO_GROUP_SHIFT; 873 const GPIOSetProperties *props = &agc->props[set_idx]; 874 875 name = g_strdup_printf("gpio%s%d", props->group_label[group_idx], 876 pin_idx % GPIOS_PER_GROUP); 877 object_property_add(obj, name, "bool", aspeed_gpio_get_pin, 878 aspeed_gpio_set_pin, NULL, NULL, NULL); 879 g_free(name); 880 } 881 } 882 883 static const VMStateDescription vmstate_gpio_regs = { 884 .name = TYPE_ASPEED_GPIO"/regs", 885 .version_id = 1, 886 .minimum_version_id = 1, 887 .fields = (VMStateField[]) { 888 VMSTATE_UINT32(data_value, GPIOSets), 889 VMSTATE_UINT32(data_read, GPIOSets), 890 VMSTATE_UINT32(direction, GPIOSets), 891 VMSTATE_UINT32(int_enable, GPIOSets), 892 VMSTATE_UINT32(int_sens_0, GPIOSets), 893 VMSTATE_UINT32(int_sens_1, GPIOSets), 894 VMSTATE_UINT32(int_sens_2, GPIOSets), 895 VMSTATE_UINT32(int_status, GPIOSets), 896 VMSTATE_UINT32(reset_tol, GPIOSets), 897 VMSTATE_UINT32(cmd_source_0, GPIOSets), 898 VMSTATE_UINT32(cmd_source_1, GPIOSets), 899 VMSTATE_UINT32(debounce_1, GPIOSets), 900 VMSTATE_UINT32(debounce_2, GPIOSets), 901 VMSTATE_UINT32(input_mask, GPIOSets), 902 VMSTATE_END_OF_LIST(), 903 } 904 }; 905 906 static const VMStateDescription vmstate_aspeed_gpio = { 907 .name = TYPE_ASPEED_GPIO, 908 .version_id = 1, 909 .minimum_version_id = 1, 910 .fields = (VMStateField[]) { 911 VMSTATE_STRUCT_ARRAY(sets, AspeedGPIOState, ASPEED_GPIO_MAX_NR_SETS, 912 1, vmstate_gpio_regs, GPIOSets), 913 VMSTATE_UINT32_ARRAY(debounce_regs, AspeedGPIOState, 914 ASPEED_GPIO_NR_DEBOUNCE_REGS), 915 VMSTATE_END_OF_LIST(), 916 } 917 }; 918 919 static void aspeed_gpio_class_init(ObjectClass *klass, void *data) 920 { 921 DeviceClass *dc = DEVICE_CLASS(klass); 922 923 dc->realize = aspeed_gpio_realize; 924 dc->reset = aspeed_gpio_reset; 925 dc->desc = "Aspeed GPIO Controller"; 926 dc->vmsd = &vmstate_aspeed_gpio; 927 } 928 929 static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) 930 { 931 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 932 933 agc->props = ast2400_set_props; 934 agc->nr_gpio_pins = 216; 935 agc->nr_gpio_sets = 7; 936 agc->gap = 196; 937 agc->reg_table = aspeed_3_6v_gpios; 938 } 939 940 static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) 941 { 942 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 943 944 agc->props = ast2500_set_props; 945 agc->nr_gpio_pins = 228; 946 agc->nr_gpio_sets = 8; 947 agc->gap = 220; 948 agc->reg_table = aspeed_3_6v_gpios; 949 } 950 951 static void aspeed_gpio_ast2600_3_6v_class_init(ObjectClass *klass, void *data) 952 { 953 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 954 955 agc->props = ast2600_3_6v_set_props; 956 agc->nr_gpio_pins = 208; 957 agc->nr_gpio_sets = 7; 958 agc->reg_table = aspeed_3_6v_gpios; 959 } 960 961 static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) 962 { 963 AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); 964 965 agc->props = ast2600_1_8v_set_props; 966 agc->nr_gpio_pins = 36; 967 agc->nr_gpio_sets = 2; 968 agc->reg_table = aspeed_1_8v_gpios; 969 } 970 971 static const TypeInfo aspeed_gpio_info = { 972 .name = TYPE_ASPEED_GPIO, 973 .parent = TYPE_SYS_BUS_DEVICE, 974 .instance_size = sizeof(AspeedGPIOState), 975 .class_size = sizeof(AspeedGPIOClass), 976 .class_init = aspeed_gpio_class_init, 977 .abstract = true, 978 }; 979 980 static const TypeInfo aspeed_gpio_ast2400_info = { 981 .name = TYPE_ASPEED_GPIO "-ast2400", 982 .parent = TYPE_ASPEED_GPIO, 983 .class_init = aspeed_gpio_ast2400_class_init, 984 .instance_init = aspeed_gpio_init, 985 }; 986 987 static const TypeInfo aspeed_gpio_ast2500_info = { 988 .name = TYPE_ASPEED_GPIO "-ast2500", 989 .parent = TYPE_ASPEED_GPIO, 990 .class_init = aspeed_gpio_2500_class_init, 991 .instance_init = aspeed_gpio_init, 992 }; 993 994 static const TypeInfo aspeed_gpio_ast2600_3_6v_info = { 995 .name = TYPE_ASPEED_GPIO "-ast2600", 996 .parent = TYPE_ASPEED_GPIO, 997 .class_init = aspeed_gpio_ast2600_3_6v_class_init, 998 .instance_init = aspeed_gpio_init, 999 }; 1000 1001 static const TypeInfo aspeed_gpio_ast2600_1_8v_info = { 1002 .name = TYPE_ASPEED_GPIO "-ast2600-1_8v", 1003 .parent = TYPE_ASPEED_GPIO, 1004 .class_init = aspeed_gpio_ast2600_1_8v_class_init, 1005 .instance_init = aspeed_gpio_init, 1006 }; 1007 1008 static void aspeed_gpio_register_types(void) 1009 { 1010 type_register_static(&aspeed_gpio_info); 1011 type_register_static(&aspeed_gpio_ast2400_info); 1012 type_register_static(&aspeed_gpio_ast2500_info); 1013 type_register_static(&aspeed_gpio_ast2600_3_6v_info); 1014 type_register_static(&aspeed_gpio_ast2600_1_8v_info); 1015 } 1016 1017 type_init(aspeed_gpio_register_types); 1018